JPS632150B2 - - Google Patents
Info
- Publication number
- JPS632150B2 JPS632150B2 JP16533281A JP16533281A JPS632150B2 JP S632150 B2 JPS632150 B2 JP S632150B2 JP 16533281 A JP16533281 A JP 16533281A JP 16533281 A JP16533281 A JP 16533281A JP S632150 B2 JPS632150 B2 JP S632150B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- power supply
- circuit
- voltages
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 22
- 230000005669 field effect Effects 0.000 claims description 17
- 230000005856 abnormality Effects 0.000 claims description 4
- 238000002955 isolation Methods 0.000 description 11
- 230000003071 parasitic effect Effects 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 10
- 238000009413 insulation Methods 0.000 description 8
- 230000002159 abnormal effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 229920006395 saturated elastomer Polymers 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 239000008188 pellet Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に係り、特にPN接合分離
によつて構成された集積回路（IC）の寄生効果
の防止回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a circuit for preventing parasitic effects in an integrated circuit (IC) configured by PN junction isolation.
ICが完全に良品であるという場合、特性がす
べての規格を満足していることを意味しているこ
とはもちろんであるが、寄生効果（寄生サイリス
タ効果、寄生MOS効果等）によるラツチアツプ
現象や誤動作等がないということも重要な要素に
入つている。ところで寄生効果に関しては、正常
な電源電圧がICに印加された状態において発生
する熱や各種ドリフト等に助長されてICを動作
不良にしたり、あるいは正常な電源を投入した瞬
間における各電源の投入順序や投入時に発生する
パルス等が引き金となつてICを動作不良に陥ら
せるものに限られるとする考え方が従来から認め
られている。しかしながら今日、ICは一層の高
集積化，多機能化の道をたどつており、素子の多
様化とともに多数の電源を必要とする場合も多く
なつてきている。 When we say that an IC is perfectly good, it of course means that its characteristics satisfy all standards, but it also means that it has latch-up and malfunction due to parasitic effects (parasitic thyristor effect, parasitic MOS effect, etc.). The fact that there are no such things is also an important factor. By the way, regarding parasitic effects, when a normal power supply voltage is applied to the IC, the heat generated and various drifts may cause the IC to malfunction, or the order in which each power supply is turned on at the moment when the normal power supply is turned on. It has long been accepted that ICs are limited to those that cause ICs to malfunction due to triggers such as pulses generated during power-on. However, today, ICs are becoming more highly integrated and multi-functional, and with the diversification of elements, the need for multiple power supplies is increasing.
このような傾向にともなつて従来は必要とされ
なかつた特性が要求されることが多くなつてき
た。その一つとして、ICに必要とされる電源電
圧全てが印加されず、特定の電源のみが印加され
る場合においてもその特定の電源が印加されてい
る回路ブロツクは正常な動作を期待すること等を
上げることができる。具体的には、＋5V及びOV
の低耐圧回路と、−25V及びOVが印加されている
高耐圧回路とを１チツプに集積したICにおいて、
なんらかの原因で−25Vが印加されないような状
態においても、前記低耐圧回路は正常な動作を要
求する場合が当てはまる。ところで、一般にPN
接合分離によつて構成されているICにおいて、
多数の電源のうち最も低い電圧が半導体基板に接
続されるのが原則であり、上に述べた具体例にお
いても正常な電源印加時には−25Vが半導体基板
に接続されている。この−25Vが印加されない場
合の半導体基板の電圧は、印加されているのこり
の電源電圧OVから＋5Vまでのいずれかの電圧と
なつている。このため、PN接合によつて各素子
を分離しているという根本的な原則が崩れて、寄
生効果特に寄生サイリスタによるラツチ現象が発
生しやすく、低耐圧回路の正常な動作を得ること
はむづかしくなつている。このような現象を説明
するため第１図の従来の回路を例にとることにす
る。 Along with this trend, characteristics that were not required in the past have become increasingly required. One of them is that even if not all the power supply voltages required by the IC are applied, and only a specific power supply is applied, the circuit block to which that specific power supply is applied is expected to operate normally. can be raised. Specifically, +5V and OV
In an IC that integrates a low voltage circuit and a high voltage circuit to which -25V and OV are applied on a single chip,
Even in a state where -25V is not applied for some reason, the low withstand voltage circuit is required to operate normally. By the way, in general PN
In ICs configured by junction separation,
In principle, the lowest voltage among a large number of power supplies is connected to the semiconductor substrate, and in the specific example described above, -25V is connected to the semiconductor substrate when normal power is applied. When this -25V is not applied, the voltage of the semiconductor substrate is any voltage from the remaining applied power supply voltage OV to +5V. For this reason, the fundamental principle of separating each element by a PN junction is broken, and parasitic effects, especially latching phenomena due to parasitic thyristors, are likely to occur, making it difficult to obtain normal operation of low voltage circuits. It's summery. In order to explain this phenomenon, the conventional circuit shown in FIG. 1 will be taken as an example.
第１図には、端子T1に印加された＋5V、端子
T3に印加されたOV（グランド電圧）、端子T4に印
加された−25Vの計３電源で駆動された高耐圧回
路VCと、前記＋5V及びOVで駆動された低耐圧
回路LCとが１チツプ（１つの半導体基板）に集
積されたICのうち特に低耐圧回路部分の出力部
を示している。低耐圧回路LCは、出力トランジ
スタQ1、負荷抵抗R1、増幅器A1より構成され回
路に何らかの異常が生じた場合、出力トランジス
タQ1がオフしてアウトプツト電圧の端子T2がハ
イレベル即ち約5Vとなつて異常を知らせる機能
を持つ。したがつて−25Vが端子T4に印加され
ないような異常な場合においても端子T2がハイ
レベルにならなければならないことが要求され
る。 Figure 1 shows +5V applied to terminal T 1 , terminal
A high voltage circuit VC driven by a total of three power supplies, OV (ground voltage) applied to T 3 and -25V applied to terminal T 4 , and a low voltage circuit LC driven by +5V and OV are connected to one It particularly shows the output section of the low-voltage circuit part of the IC integrated on a chip (one semiconductor substrate). The low voltage circuit LC is composed of an output transistor Q 1 , a load resistor R 1 , and an amplifier A 1 . If any abnormality occurs in the circuit, the output transistor Q 1 is turned off and the output voltage terminal T 2 becomes high level, that is, approximately It has the function of becoming 5V and notifying an abnormality. Therefore, even in an abnormal case where -25V is not applied to the terminal T4 , the terminal T2 is required to be at a high level.
しかし−25Vが印加されなくなると、半導体基
板および絶縁分離拡散領域（後述）がOV乃至＋
5Vの間の電圧となり、各素子のアイランドと絶
縁分離拡散領域および半導体基板とが順バイアス
になる場合が生じ、各アイランド間が活性化す
る。特に低耐圧回路に飽和するラテラルトランジ
スタ、飽和するNPNトランジスタ等が存在する
と、ホールが絶縁分離拡散領域や半導体基板に注
入されて、先に述べた各アイランド間に等価的に
働く寄生NPNトランジスタとともに寄生PNPN
サイリスタを形成する。以上述べてきたような過
程のもとに第１図の出力トランジスタQ1のアイ
ランド（コレクタ領域）をカソードとするサイリ
スタが形成され、−25Vが印加されないという異
常事態にもかかわらず、端子T2はローレベル即
ち約OVにラツチされ異常事態発生を知らせるこ
とが不可能となる。このような状態を打開するた
めに従来からとられてきた手段としては、飽和す
るトランジスタと並列にシヨツトキーダイオード
を加えて飽和を浅くして、半導体基板や絶縁分離
拡散領域等へのホールの注入を減少させたり、出
力トランジスタQ1と飽和するトランジスタとの
間をできるだけ離して設置したり、別の素子を間
にレイアウトしたりする消極的な改善策がとられ
てきた。しかしながら、このような消極的な改善
策においては、完全に正常な動作が保証されるわ
けではなくかつ追加するシヨツトキーダイオード
の数が多くペレツトの面積が大きくなり、マスク
レイアウトに新たな制限も加えられて、ICの製
造上不利になることが多かつた。 However, when -25V is no longer applied, the semiconductor substrate and insulation isolation diffusion region (described later)
The voltage becomes between 5V, and the islands of each element, the insulation isolation diffusion region, and the semiconductor substrate may become forward biased, and the areas between the islands become activated. In particular, if there are saturated lateral transistors, saturated NPN transistors, etc. in a low voltage circuit, holes will be injected into the insulation isolation diffusion region or the semiconductor substrate, and become parasitic along with the parasitic NPN transistors that equivalently act between each island. PNPN
form a thyristor. Based on the process described above, a thyristor is formed with the island (collector region) of the output transistor Q 1 shown in Figure 1 as its cathode, and despite the abnormal situation in which -25V is not applied, the terminal T 2 is latched at a low level, that is, approximately OV, making it impossible to notify the occurrence of an abnormal situation. Conventionally, measures taken to overcome this situation include adding a Schottky diode in parallel with the saturated transistor to reduce the saturation level and to prevent holes from entering the semiconductor substrate, insulation isolation diffusion region, etc. Negative improvements have been taken to reduce the injection, to place the output transistor Q 1 and the saturated transistor as far apart as possible, and to lay out another element in between. However, with such passive improvement measures, completely normal operation cannot be guaranteed, and the number of added Schottky diodes increases, the area of the pellet increases, and new restrictions are placed on the mask layout. In addition, it was often disadvantageous in the manufacture of ICs.
本発明の目的は、上で述べたように、半導体基
板や絶縁分離拡散領域の電圧が浮き上り寄生効果
が生じやすい状態になつても、これを解決するた
めシヨツトキーダイオード等を用いてペレツト面
積を大幅に拡大する改善策をとることなく、レイ
アウトの自由度を確保しつつ例えば出力トランジ
スタの端子T2の電圧を強制的に目的とする電圧
に固定する半導体装置を提供することにある。 As stated above, an object of the present invention is to solve the problem by using a Schottky diode or the like to reduce the voltage of a semiconductor substrate or an insulating isolation diffusion region, even if the voltage rises and the parasitic effect is likely to occur. It is an object of the present invention to provide a semiconductor device in which, for example, the voltage of a terminal T2 of an output transistor is forcibly fixed to a target voltage while ensuring freedom in layout without taking any improvement measures to significantly increase the area.
本発明は、少なくとも３つの相異なる電源電圧
によつて動作する回路を有し、前記電源電圧のう
ち最も低い電源電圧が半導体基板等に接続されて
いる半導体装置において、前記最も低い電源電圧
がゲートに接続され、かつ前記電源電圧のうち最
も低い電源電圧を除く他の電源電圧の一つがソー
ス又はドレインに接続された接合型電界効果トラ
ンジスタを有し、前記他の電源電圧の１つが接続
されていないドレイン又はソースが電圧異常を知
らせるための出力となつていることを特徴とする
半導体装置にある。 The present invention provides a semiconductor device having a circuit that operates with at least three different power supply voltages, and in which the lowest power supply voltage among the power supply voltages is connected to a semiconductor substrate, etc., in which the lowest power supply voltage is connected to a gate. and has a junction field effect transistor whose source or drain is connected to one of the other power supply voltages other than the lowest power supply voltage among the power supply voltages, and one of the other power supply voltages is connected. The semiconductor device is characterized in that a drain or a source that is not connected to the semiconductor device serves as an output for notifying a voltage abnormality.
例えば本発明の半導体装置は、従来の半導体基
板内にゲートが半導体基板と絶縁分離拡散領域と
からなる接合型電界効果トランジスタ（以後
JFETと記す）を一つだけ用いればこと足りるも
のである。 For example, in the semiconductor device of the present invention, a junction field effect transistor (hereinafter referred to as
It is sufficient to use just one (denoted as JFET).
本発明によれば、電源電圧がすべて正常に印加
された状態では、あたかもこのJFETを無くした
がごとき回路構成とすることができる。 According to the present invention, when all power supply voltages are normally applied, the circuit configuration can be made as if the JFET were eliminated.
次に図面を用いて本発明を詳細に説明する。第
２図が本発明の第１の実施例の回路図であり、負
荷R1と並列に１つのＮチヤンネルJFETJ1を設け
ている。（なお、説明を容易にするため回路構成、
素子の記号等は第１図と同じものを用る。第３図
も同様。）第２図より、３つの電源電圧＋5V（端
子T1），OV（端子T3），−25V（端子T4）のすべて
が正常に印加されている時はJFETJ1のゲート・
ソース間電圧は大きく｜VGS｜＞25Vとなつてお
りJFETJ1のピツチオフ電圧Vpを｜Vp｜＜｜VGS
｜つまり本実施では｜Vp｜＜25Vとすれば、
JFETJ1はピンチオフして機能上回路から除外さ
れたと同然である。したがつて正常な電源電圧が
印加された時はJFETJ1は何ら回路に影響を及ぼ
さない。一方、何らかの原因で−25Vが印加され
ない場合は、JFETJ1のゲート電位は浮き上りゲ
ート・ソース電圧は小さくなる。そこでJFETJ1
のオン抵抗Rpoを十分小さく設計していれば、導
通状態でそのインピーダンスは低いため、たとえ
出力トランジスタに寄生のサイリスタ動作が生じ
ても出力を強制的にハイレベルの＋5V近くにす
ることができる。 Next, the present invention will be explained in detail using the drawings. FIG. 2 is a circuit diagram of the first embodiment of the present invention, in which one N-channel JFETJ 1 is provided in parallel with the load R 1 . (For ease of explanation, the circuit configuration is
The same symbols for elements as in FIG. 1 are used. The same applies to Figure 3. ) From Figure 2, when all three power supply voltages +5V (terminal T 1 ), OV (terminal T 3 ), and -25V (terminal T 4 ) are applied normally, the gate of JFETJ 1
The source voltage is large |V GS |＞25V, and the pitch-off voltage V p of JFETJ 1 is |V p |<|V GS
｜In other words, in this implementation, if ｜V p ｜＜25V,
JFETJ 1 is as if pinched off and functionally removed from the circuit. Therefore, when a normal power supply voltage is applied, JFETJ 1 has no effect on the circuit. On the other hand, if -25V is not applied for some reason, the gate potential of JFETJ 1 rises and the gate-source voltage becomes small. So JFETJ 1
If the on-resistance R po is designed to be sufficiently small, its impedance is low in the conducting state, so even if parasitic thyristor operation occurs in the output transistor, the output can be forced to a high level near +5V. .
第３図は本発明の第２の実施例の回路図であ
り、前記第１の実施例と同様に最低電源に電圧が
印加されない場合のような異常事態が発生した
時、端子T2の電圧をローレベルにする。第１の
実施例と同様にJFETJ1のオン抵抗Rpoを十分小
さく、かつ｜Vp｜＜25Vとすると、端子T4に−
25Vが印加されないような異常時には、端子T2
の電圧を強制的にOV付近のローレベルにもつて
くることができる。この様に、最低電圧が何らか
の原因で印加されない場合において、低耐圧回路
の電圧を強制的に目的とする電圧とすることがで
きる。 FIG. 3 is a circuit diagram of a second embodiment of the present invention, and as in the first embodiment, when an abnormal situation occurs such as when no voltage is applied to the lowest power supply, the voltage at terminal T2 to low level. As in the first embodiment, if the on-resistance R po of JFETJ 1 is sufficiently small and |V p |<25V, the terminal T 4 -
In an abnormal situation such as when 25V is not applied, terminal T 2
The voltage can be forced to a low level near OV. In this way, even if the lowest voltage is not applied for some reason, the voltage of the low voltage circuit can be forced to the target voltage.
第４図は、本発明の第１，第２の実施例をそれ
ぞれ示す第２図，第３図の接合型電界効果トラン
ジスタJ1の断面図で、半導体基板および絶縁分離
拡散領域（ボトムゲート）１と、チヤンネル領域
としてのエピタキシヤル領域２と、ソース３と、
アツパーゲート領域４と、ドレイン領域５と、ソ
ース電極７と、ドレイン電極６と、半導体基板お
よび絶縁分離拡散領域１の基板電極８とからな
る。 FIG. 4 is a cross-sectional view of the junction field effect transistor J1 of FIGS. 2 and 3 showing the first and second embodiments of the present invention, respectively, showing the semiconductor substrate and the insulating isolation diffusion region (bottom gate). 1, an epitaxial region 2 as a channel region, a source 3,
It consists of an upper gate region 4 , a drain region 5 , a source electrode 7 , a drain electrode 6 , and a substrate electrode 8 of the semiconductor substrate and insulation isolation diffusion region 1 .
第４図のドレイン電極６は第２図の端子T1に、
ソース電極７は端子T2に、基板電極８は端子T4
に対応しており、第２図の端子T3は第４図に示
された半導体領域と電気的に絶縁されて存在する
が、第４図には図示していない。 The drain electrode 6 in FIG. 4 is connected to the terminal T 1 in FIG.
Source electrode 7 is connected to terminal T 2 , and substrate electrode 8 is connected to terminal T 4.
The terminal T3 shown in FIG. 2 is present electrically insulated from the semiconductor region shown in FIG. 4, but is not shown in FIG.
また、第４図のドレイン電極６は第３図におい
ては端子T2に、ソース電極７は端子T3に、基板
電極８は端子T4に対応しており、第３図の端子
T1は第４図には図示されていない。 In addition, the drain electrode 6 in FIG. 4 corresponds to the terminal T 2 in FIG. 3, the source electrode 7 corresponds to the terminal T 3 , and the substrate electrode 8 corresponds to the terminal T 4 in FIG. 3.
T 1 is not shown in FIG.
第４図において、ドレイン電極６，ソース電極
７の印加される電圧V1，V2は基板電極８の電圧
V3（領域１および４アツパーゲート領域に印加さ
れる電圧）よりも大きく、
V1＞V3，V2＞V3 …(1)
の関係にさる。今、この接合型電界効果トランジ
スタJ1のピンチオフ電圧をVpとして、
｜Vp｜＜V1−V3，｜Vp｜＜V2−V3 …(2)
｜Vp｜＞｜V1−V2｜ …(3)
のように選ぶと、
電圧V1，V2，V3の３つが印加される時は、
この接合型電界効果トランジスタJ1はピンチオ
フして、ほとんど接合のリーク電流しか流さず
ひじように高いインピーダンスを持つ。 In FIG. 4, the voltages V 1 and V 2 applied to the drain electrode 6 and source electrode 7 are the voltage of the substrate electrode 8.
It is larger than V 3 (the voltage applied to the regions 1 and 4 upper gate regions), and the relationship is as follows: V 1 >V 3 , V 2 >V 3 (1). Now, assuming that the pinch-off voltage of this junction field effect transistor J 1 is V p , |V p |<V 1 −V 3 , |V p |<V 2 −V 3 …(2) |V p |>|V 1 −V 2 | …(3) When three voltages V 1 , V 2 , and V 3 are applied,
This junction field effect transistor J1 is pinched off, allowing only junction leakage current to flow, and has an elbow-high impedance.
いつぽう、電圧V1，V2のみが印加され、電
圧V3が印加されない時はこの接合型電界効果
トランジスタJ1はオンして端子６，７間に低い
インピーダンスを持つ。 On the other hand, when only voltages V 1 and V 2 are applied and voltage V 3 is not applied, this junction field effect transistor J 1 is turned on and has a low impedance between terminals 6 and 7.
したがつて第５図に示すように、前記式(2)，(3)
の関係にあるピンチオフ電圧をもつ接合型電界効
果トランジスタ９に、前記式(1)，(2)，(3)の関係を
もつ３つの電圧V1，V2，V3を印加すると、その
接合型電界効果トランジスタはオフし第６図と等
価となり、電圧V1，V2が印加された端子間には
高耐圧の２つのダイオード１０，１１が直列には
いり電流を遮断する。 Therefore, as shown in Figure 5, the above equations (2) and (3)
When three voltages V 1 , V 2 , and V 3 having the relationships expressed by equations ( 1 ), (2), and ( 3 ) above are applied to the junction field effect transistor 9 having pinch-off voltages having the relationship, the junction The type field effect transistor is turned off and becomes equivalent to that shown in FIG. 6, and two high voltage diodes 10 and 11 are connected in series between the terminals to which voltages V 1 and V 2 are applied to cut off the current.
一方、前述の接合型電界効果トランジスタに電
圧V3を印加せず、電圧V1，V2のみを印加する
と、前記式(3)および｜Vp｜＞V1，｜Vp｜＞V2が
成立し接合型電界効果トランジスタは低抵抗とな
り第７図の等価回路の抵抗１２となる。 On the other hand, if voltage V 3 is not applied to the above-mentioned junction field effect transistor and only voltages V 1 and V 2 are applied, then the above formula (3) and |V p |>V 1 , |V p |>V 2 holds, the junction field effect transistor has a low resistance, and becomes the resistor 12 in the equivalent circuit of FIG.
以上のように、本発明では、少なくとも３つの
相異なる電圧を電源電圧とし、該電圧のうち最も
低い電圧が絶縁分離拡散領域および半導体基板に
接続された半導体装置において、前記絶縁分離拡
散領域および半導体基板をゲートとしかつソース
又はドレインが前記最も低い電圧を除いた前記電
圧によつて動作する接合型電界効果トランジスタ
を有し、該接合型電界効果トランジスタが前記少
なくとも３つの相異なる電圧のすべてが印加され
た時はオフし、前記最も低い電圧が印加されない
時は抵抗として動作するように構成されているこ
とを特徴としている。 As described above, in the present invention, in a semiconductor device in which at least three different voltages are used as power supply voltages, and the lowest voltage among the voltages is connected to an insulation isolation diffusion region and a semiconductor substrate, the insulation isolation diffusion region and the semiconductor substrate are connected to each other. a junction field effect transistor whose gate is the substrate and whose source or drain is operated by the voltages other than the lowest voltage, the junction field effect transistor being applied with all of the at least three different voltages; It is characterized in that it is configured to be turned off when the lowest voltage is applied, and to operate as a resistor when the lowest voltage is not applied.
以上述べてきたように、本発明を採用すること
により、正常な電源電圧が印加された時は何ら動
作に支障をきたすことがないことはもちろん、ペ
レツト面積の大幅な増加を招かず、かつマスクレ
イアウトの自由度を失なうことなく、最低電圧が
印加されなくなるような異常事態に対処できる。 As described above, by adopting the present invention, there is no problem in operation when a normal power supply voltage is applied, there is no significant increase in pellet area, and the mask It is possible to cope with an abnormal situation where the minimum voltage is not applied without losing the degree of freedom in layout.
第１図は本発明を説明する上で理解を助けるべ
く用意された従来の半導体装置の回路図、第２図
は本発明の第１の実施例を示す回路図、第３図は
本発明の第２の実施例を示す回路図、第４図は第
２図又は第３図で示された接合型電界効果トラン
ジスタの構造を示す断面図、第５図は第４図の等
価回路、第６図は３電源に電圧が印加された場合
の第４図の等価回路、第７図は２電源にのみ電圧
が印加された場合の第４図の等価回路である。
尚図において、Q1…出力トランジスタ、R1…
負荷抵抗、A1…アンプ、J1…Ｎチヤネル接合型
電界効果トランジスタ、VC…高耐圧回路、LC…
低耐圧回路、T1，T2，T3，T4…端子、１…半導
体基板および絶縁分離拡散領域、２…エピタキシ
ヤル領域、３…ソース領域、４…アツパーゲート
領域、５…ドレイン領域、６…ドレイン電極、７
…ソース電極、８…基板電極、９…接合型電界効
果トランジスタ、１０，１１…ダイオード、１２
…抵抗。
FIG. 1 is a circuit diagram of a conventional semiconductor device prepared to facilitate understanding in explaining the present invention, FIG. 2 is a circuit diagram showing a first embodiment of the present invention, and FIG. A circuit diagram showing the second embodiment, FIG. 4 is a sectional view showing the structure of the junction field effect transistor shown in FIG. 2 or 3, FIG. 5 is an equivalent circuit of FIG. 4, and FIG. The figure shows the equivalent circuit of FIG. 4 when voltages are applied to three power sources, and FIG. 7 shows the equivalent circuit of FIG. 4 when voltages are applied to only two power sources. In the figure, Q 1 ...output transistor, R 1 ...
Load resistance, A 1 ...Amplifier, J 1 ...N-channel junction field effect transistor, VC...High voltage circuit, LC...
Low voltage circuit, T 1 , T 2 , T 3 , T 4 ... terminal, 1 ... semiconductor substrate and insulation isolation diffusion region, 2 ... epitaxial region, 3 ... source region, 4 ... upper gate region, 5 ... drain region, 6 ...Drain electrode, 7
...Source electrode, 8...Substrate electrode, 9...Junction field effect transistor, 10, 11...Diode, 12
…resistance.
Claims (1)
動作する回路を有し、前記電源電圧のうち最も低
い電源電圧が半導体基板等に接続されている半導
体装置において、前記最も低い電源電圧がゲート
に接続され、かつ前記電源電圧のうち最も低い電
源電圧を除く他の電源電圧の１つがソース又はド
レインに接続された接合型電界効果トランジスタ
を有し、前記他の電源電圧の１つが接続されてい
ないドレイン又はソースが電圧異常を知らせるた
めの出力となつていることを特徴とする半導体装
置。 ２ 少なくとも３つの相異なる電源電圧の１つ
が、グランド電圧となつていることを特徴とする
特許請求の範囲第１項記載の半導体装置。[Scope of Claims] 1. In a semiconductor device having a circuit that operates with at least three different power supply voltages, and in which the lowest power supply voltage among the power supply voltages is connected to a semiconductor substrate or the like, the lowest power supply voltage is A junction field effect transistor has a junction field effect transistor having a gate connected to a voltage, and one of the other power supply voltages other than the lowest power supply voltage among the power supply voltages is connected to a source or a drain, and one of the other power supply voltages is connected to a source or a drain. A semiconductor device characterized in that an unconnected drain or source serves as an output for notifying a voltage abnormality. 2. The semiconductor device according to claim 1, wherein one of the at least three different power supply voltages is a ground voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16533281A JPS5867040A (en) | 1981-10-16 | 1981-10-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16533281A JPS5867040A (en) | 1981-10-16 | 1981-10-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5867040A JPS5867040A (en) | 1983-04-21 |
| JPS632150B2 true JPS632150B2 (en) | 1988-01-18 |
Family
ID=15810318
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16533281A Granted JPS5867040A (en) | 1981-10-16 | 1981-10-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5867040A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20200051884A (en) * | 2018-11-05 | 2020-05-14 | 삼성디스플레이 주식회사 | Carrier, apparatus for manufacturing a display apparatus having the same and method for manufacturing a display apparatus |
| WO2020183552A1 (en) * | 2019-03-08 | 2020-09-17 | シャープ株式会社 | Deposition device and method for manufacturing display device |
| KR20230068065A (en) * | 2021-11-10 | 2023-05-17 | 주식회사 선익시스템 | In-line deposition system having mask chucking mechanism with a magnetic shield |
-
1981
- 1981-10-16 JP JP16533281A patent/JPS5867040A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20200051884A (en) * | 2018-11-05 | 2020-05-14 | 삼성디스플레이 주식회사 | Carrier, apparatus for manufacturing a display apparatus having the same and method for manufacturing a display apparatus |
| WO2020183552A1 (en) * | 2019-03-08 | 2020-09-17 | シャープ株式会社 | Deposition device and method for manufacturing display device |
| KR20230068065A (en) * | 2021-11-10 | 2023-05-17 | 주식회사 선익시스템 | In-line deposition system having mask chucking mechanism with a magnetic shield |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5867040A (en) | 1983-04-21 |
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