JPS63209145A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63209145A JPS63209145A JP4185187A JP4185187A JPS63209145A JP S63209145 A JPS63209145 A JP S63209145A JP 4185187 A JP4185187 A JP 4185187A JP 4185187 A JP4185187 A JP 4185187A JP S63209145 A JPS63209145 A JP S63209145A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- film
- wiring
- intersection
- lower layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000010410 layer Substances 0.000 claims abstract 13
- 239000011229 interlayer Substances 0.000 claims abstract 2
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims 1
- 239000003990 capacitor Substances 0.000 abstract description 4
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法特に多１）＃配線の
パターン形成法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for forming a pattern for multi-line wiring.
第２Ａ図〜第２Ｄ図は従来の多層配線構造の形成方法を
示し、第２Ａ図は、絶縁膜上に下層配線を形成した半導
体装置の平面図、第２Ｂ図は、下層配線上に絶縁膜を形
成しその上に金属膜を形成した後の半導体装置の、第２
Ａ図におけるｎＢ −■Ｂ断面図、第２Ｃ図は上層配線
形成のためのマスクパターン、第２Ｄ図は上層配線をバ
ターニングした後の半導体装置の平面図である。2A to 2D show a conventional method for forming a multilayer wiring structure, FIG. 2A is a plan view of a semiconductor device in which a lower wiring is formed on an insulating film, and FIG. 2B is a plan view of a semiconductor device in which a lower wiring is formed on an insulating film. of the semiconductor device after forming the metal film and forming the metal film thereon.
FIG. 2C is a mask pattern for forming upper layer wiring, and FIG. 2D is a plan view of the semiconductor device after patterning the upper layer wiring.
第２Ａ図〜第２Ｄ図において、半導体基板（１）上に、
熱ｑ化法、ＣＶＤ法などにより絶縁膜（２ａ）例えばシ
リコン酸化膜を形成し、その上に下層配線（３）を蒸着
法、スパッタ法、ＣＶＤ法などにより、例えばアルミニ
ウム合金膜、高融点金属膜、金属シリサイド膜、多結晶
シリコン膜あるいはこれらの多層膜などを形成し、写真
製版やエツチング法などによりパターニングする。In FIGS. 2A to 2D, on the semiconductor substrate (1),
An insulating film (2a), for example, a silicon oxide film, is formed by a thermal q process, a CVD method, etc., and a lower layer wiring (3) is formed thereon by, for example, an aluminum alloy film, a high melting point metal, by a vapor deposition method, a sputtering method, a CVD method, etc. A film, a metal silicide film, a polycrystalline silicon film, or a multilayer film thereof is formed and patterned by photolithography, etching, or the like.
次に、スピンコード法や、ＣｔＶＤ法などにより絶縁膜
（２′ｂ）、例えばシリコン酸化膜を形成しその上に蒸
着法、スパッタ法、ＣＶＤ法などにより金属膜（４）、
例えばアルミニウム合金膜、高融点金属膜、金２ｇシリ
サイド膜、多結晶シリコン膜あるいはこれらの多層膜な
どを形成する。Next, an insulating film (2'b), for example, a silicon oxide film, is formed by a spin code method, a CtVD method, etc., and a metal film (4) is formed thereon by a vapor deposition method, a sputtering method, a CVD method, etc.
For example, an aluminum alloy film, a high melting point metal film, a gold 2g silicide film, a polycrystalline silicon film, or a multilayer film thereof is formed.
次にマスクパターン（５）用いて、写真製版を行い、エ
ツチング法により金属膜（４）をパターニングし、上層
配線（６）を形成する。Next, photolithography is performed using the mask pattern (5), and the metal film (4) is patterned by an etching method to form an upper layer wiring (6).
〔発明が解決しようとする問題点〕
上記のような従来の半導体装置の製造方法においては、
第２Ｃ図に示すように、マスクパターン（５）は、両配
線＋３１ 、 （６）の交差部と、その周囲の配線部の
線幅が等しい。従って、交差部の容量が大きく、（１号
伝達の遅延時間が長くなるという問題がある。[Problems to be solved by the invention] In the conventional semiconductor device manufacturing method as described above,
As shown in FIG. 2C, the mask pattern (5) has the same line width at the intersection of both wires +31 and (6) and the surrounding wiring portion. Therefore, there is a problem that the capacity of the intersection is large and the delay time of No. 1 transmission becomes long.
この発明は、上記の問題点を解決するため、上記配線の
交差部の面積を小さくすることにより、より遅延時間の
短い半導体装置を提供することを目的とする。In order to solve the above-mentioned problems, it is an object of the present invention to provide a semiconductor device with a shorter delay time by reducing the area of the intersection of the wirings.
この元り］に係る半導体装ｉ藏の製造方法は、下層配線
膜の上にｌ＃１間絶間膜縁膜成し、その上に上層配線膜
を形成し、上記の下層配線膜と上層配線膜との交差部で
形成される、上層、下層配線パターンの少くとも一方の
配線パターン面線を、周囲パターンより小さくしたマス
クを用いて、配線膜のパターニングを行い、３２１′差
部の容量小さくする製造方法である。The method for manufacturing a semiconductor device according to this invention is to form an l#1 insulating film on a lower wiring film, form an upper wiring film on top of that, and then combine the lower wiring film with the upper wiring. The wiring film is patterned using a mask that makes at least one of the wiring pattern surface lines of the upper layer and lower layer wiring patterns smaller than the surrounding pattern, which is formed at the intersection with the film, to reduce the capacitance of the 321' difference part. This is the manufacturing method.
この発明においては交差部の配線膜の小面積化は、上ｊ
９ＩＪ及び下層の配線膜で形成されるコンデンサの璽極
面積を、縮小させることにより小容量化を実現し、又差
部以外の配ＷＷＪ積を減少させないことにより、抵抗の
増分を最小限に留めるものである。In this invention, the reduction in the area of the wiring film at the intersection is achieved by
By reducing the electrode area of the capacitor formed by the 9IJ and the underlying wiring film, the capacitance is reduced, and by not reducing the distribution WWJ product other than the difference portion, the increase in resistance is kept to a minimum. It is something.
以下、この発明の一実施例を図につｈて説明する。＄１
Ａ１Ａ第１Ｄ図は、本発明の半導体装置の製造方法を示
し、（１）は半導体基板、（２ａ）Ｉ （２１））は絶
縁膜、（３）は下層配線、（４）は金属膜（７）は上層
配線形成の為のマスクパターン、（８）は、マスクパタ
ーンの上層下層配線交差部に相当し、周囲配線部よりも
細くなった部分、（９）は、上層配線膜である。An embodiment of the present invention will be described below with reference to the drawings. $1
A1A and 1D show a method for manufacturing a semiconductor device according to the present invention, in which (1) is a semiconductor substrate, (2a) I (21)) is an insulating film, (3) is a lower wiring, and (4) is a metal film ( 7) is a mask pattern for forming upper layer wiring, (8) corresponds to the intersection of the upper layer and lower layer wiring of the mask pattern and is thinner than the surrounding wiring portion, and (9) is the upper layer wiring film.
従来の製造方法と同様に、ｆｐｆ、 ｌ １図の金属膜
（４）を、第１Ｃ図の（７）に示すようなマスクパター
ンによって写真製版を行い、エツチング法によって２４
１Ｄ図の（９）に示すような上層配線をパターニングす
る。Similar to the conventional manufacturing method, the metal film (4) shown in FIG.
The upper layer wiring as shown in (9) in the 1D diagram is patterned.
第１Ｃ図（８）の部分のみを線幅を小さくし念ので、上
ノー下層配線の交差部のみ面積を小さくすることができ
る。しかも上Ｉ葡配線の？Ｒ幅は、交差部のみ小さくし
たので、配線抵抗の増加は最小に留めることができる。By reducing the line width only in the portion shown in FIG. 1C (8), it is possible to reduce the area only at the intersection of the upper and lower layer interconnections. And what about the upper wiring? Since the R width is made smaller only at the intersection, the increase in wiring resistance can be kept to a minimum.
尚、上記実施例では、上層配房の交差部を細くしたが、
下層配祖の交差部を細くしてもよく、上層下層配線の交
差部の線幅を共に小さくしてもよ（、第１０図に示すよ
うなマスクパターンを上層下層いずれの配線のパターニ
ングに用いてもよい。In addition, in the above embodiment, the intersection of the upper layer arrangement was made thinner, but
The intersections of the lower layer interconnects may be made thinner, and the line widths of the intersections of the upper and lower layer interconnects may be made smaller (a mask pattern as shown in Figure 10 can be used for patterning both the upper and lower layer interconnects). It's okay.
また、この発明の特徴は、多″層配線の交差部の面積を
小さくすることであり、第１０図の（８）に示すマスク
パターンの形状は任意である。Further, a feature of the present invention is to reduce the area of the intersection of multi-layer wiring, and the shape of the mask pattern shown in (8) in FIG. 10 can be arbitrary.
ま之、配線として金属膜のみならず、半導体基板に形成
された不純物拡散層なども含む０また、上記実施例では
２層配線の場合を示したが、３ノ一以上の多Ｉ−配肩の
場合も同様の効果を奏することに言うまでもない。However, the wiring includes not only a metal film but also an impurity diffusion layer formed on a semiconductor substrate.Also, although the above example shows the case of two-layer wiring, it is possible to Needless to say, the same effect can be achieved in the case of .
以上のように、この発明によれば、多層配線に訃いて、
コンデンサを形成する上層下層配線の交差部のみ配線面
積を減少させることにより、より遅延時間の短い、半導
体装置を提供できる効果がある。As described above, according to the present invention, by using multilayer wiring,
By reducing the wiring area only at the intersection of the upper and lower layer wiring forming the capacitor, it is possible to provide a semiconductor device with a shorter delay time.
第１Ａ図〜第１Ｄ図は、この発明の一実施例を示すそれ
ぞれ平面図、断面図、平面図、平面図。
第２Ａ図〜第２Ｄ図は、従来の半導体装置の夷遣方法を
示すそれぞれ平面図、断面図、平面図、平面図である。
（１）は、半導体基板、（２ａ）、 （２ｂ）は、絶縁
膜、（３）は、下層配線、（４）は、金属膜、（５）
、 （７）は、上１）４配線形成の為のマスクパターン
、（８）は、マスクパターンの上層下層配線の交差部に
相当する部分（９） 、 （６）は上層配線である。
なお各図中、同一符号は同一または相当部分を示す。1A to 1D are a plan view, a sectional view, a plan view, and a plan view, respectively, showing an embodiment of the present invention. FIGS. 2A to 2D are a plan view, a sectional view, a plan view, and a plan view, respectively, showing a conventional method for distributing a semiconductor device. (1) is a semiconductor substrate, (2a), (2b) is an insulating film, (3) is a lower layer wiring, (4) is a metal film, (5)
, (7) is a mask pattern for forming the upper 1) four wirings, (8) is a portion corresponding to the intersection of the upper and lower layer wirings of the mask pattern, (9) and (6) are upper layer wirings. In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (6)
絶縁する層間絶縁膜とを有する半導体装置の製造方法に
おいて上記配線の少くとも一方をその上記交差部分が他
の部分より狭くされたマスクパターンで微細加工したこ
とを特徴とする半導体装置の製造方法。(1) In a method for manufacturing a semiconductor device having upper layer and lower layer wirings that intersect with each other and an interlayer insulating film that insulates between the two wirings, at least one of the wirings is formed so that the crossing portion thereof is narrower than the other portion. A method for manufacturing a semiconductor device, characterized in that it is microfabricated using a mask pattern.
る特許請求の範囲第１項記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the lower wiring is an impurity diffusion layer.
むことを特徴とする特許請求の範囲第１項記載の半導体
装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein at least one of the upper and lower layer interconnects includes a metal film.
多結晶シリコン膜を含むことを特徴とする特許請求の範
囲第１項記載の半導体装置の製造方法。(4) At least one of the above upper layer and lower layer wiring is
2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device includes a polycrystalline silicon film.
リサイド膜を含むことを特徴とする特許請求の範囲第１
項記載の半導体装置の製造方法。(5) Claim 1, characterized in that at least one of the upper layer and lower layer interconnects includes a silicide film.
A method for manufacturing a semiconductor device according to section 1.
属窒化膜又は金属炭化膜又は金属ホウ化膜を含むことを
特徴とする特許請求の範囲第１項記載の半導体装置の製
造方法。(6) The method of manufacturing a semiconductor device according to claim 1, wherein at least one of the upper layer wiring and the lower layer wiring includes a metal nitride film, a metal carbide film, or a metal boride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4185187A JPS63209145A (en) | 1987-02-25 | 1987-02-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4185187A JPS63209145A (en) | 1987-02-25 | 1987-02-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63209145A true JPS63209145A (en) | 1988-08-30 |
Family
ID=12619757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4185187A Pending JPS63209145A (en) | 1987-02-25 | 1987-02-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63209145A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH036833U (en) * | 1989-06-07 | 1991-01-23 | ||
| JP2007259430A (en) * | 2006-02-24 | 2007-10-04 | Matsushita Electric Ind Co Ltd | Surface acoustic wave filter, antenna duplexer, high frequency module using the same, and communication device |
| JP2011217420A (en) * | 2006-02-24 | 2011-10-27 | Panasonic Corp | Surface acoustic wave filter, antenna duplexer, high-frequency module using them, and communication apparatus |
| JP2011259516A (en) * | 2011-10-06 | 2011-12-22 | Panasonic Corp | Surface acoustic wave filter and communication apparatus using the same |
-
1987
- 1987-02-25 JP JP4185187A patent/JPS63209145A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH036833U (en) * | 1989-06-07 | 1991-01-23 | ||
| JP2007259430A (en) * | 2006-02-24 | 2007-10-04 | Matsushita Electric Ind Co Ltd | Surface acoustic wave filter, antenna duplexer, high frequency module using the same, and communication device |
| JP2011217420A (en) * | 2006-02-24 | 2011-10-27 | Panasonic Corp | Surface acoustic wave filter, antenna duplexer, high-frequency module using them, and communication apparatus |
| JP2012157078A (en) * | 2006-02-24 | 2012-08-16 | Panasonic Corp | Surface acoustic wave filter, antenna duplexer, high frequency module using the same, and communication device |
| JP2011259516A (en) * | 2011-10-06 | 2011-12-22 | Panasonic Corp | Surface acoustic wave filter and communication apparatus using the same |
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