JPS63196136U - - Google Patents

Info

Publication number
JPS63196136U
JPS63196136U JP8589687U JP8589687U JPS63196136U JP S63196136 U JPS63196136 U JP S63196136U JP 8589687 U JP8589687 U JP 8589687U JP 8589687 U JP8589687 U JP 8589687U JP S63196136 U JPS63196136 U JP S63196136U
Authority
JP
Japan
Prior art keywords
transmission
output
balanced
delay circuit
bus driver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8589687U
Other languages
Japanese (ja)
Other versions
JPH062361Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987085896U priority Critical patent/JPH062361Y2/en
Publication of JPS63196136U publication Critical patent/JPS63196136U/ja
Application granted granted Critical
Publication of JPH062361Y2 publication Critical patent/JPH062361Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Dc Digital Transmission (AREA)
  • Small-Scale Networks (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を示す伝送回路図、
第２図は伝送コントローラの伝送データ構造を例
示する図、第３図は不平衡形伝送装置の構成図、
第４図は従来の平衡形伝送装置の構成図である。 １１……伝送コントローラ、１２……バスドラ
イバ、１３……遅延回路、１４……タイマ回路、
１５……バスカツト回路。 FIG. 1 is a transmission circuit diagram showing an embodiment of the present invention.
FIG. 2 is a diagram illustrating the transmission data structure of the transmission controller, FIG. 3 is a configuration diagram of the unbalanced transmission device,
FIG. 4 is a block diagram of a conventional balanced transmission device. 11...Transmission controller, 12...Bus driver, 13...Delay circuit, 14...Timer circuit,
15... Bass cut circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 平衡形バスとの接続に送信可能・不可能状態の
出力コントロール端子を持つバスドライバと、伝
送データの出力にイネーブル信号を生成しない伝
送コントローラと、この伝送コントローラの出力
データの先頭ビツトから最終ビツトまでの時間幅
以上のパルスで前記バスドライバの出力を送信可
能状態にするタイマ回路と、前記伝送コントロー
ラの出力データを前記バスドライバが出力可能状
態になるまでの時間以上遅らせて該バスドライバ
に送信データとして与える遅延回路とを備えたこ
とを特徴とする平衡形伝送装置。 A bus driver that has an output control terminal that can be used to connect to a balanced bus, a transmission controller that does not generate an enable signal for transmission data output, and a transmission controller that outputs data from the first bit to the last bit. a timer circuit that sets the output of the bus driver to a transmittable state with a pulse having a time width or more; A balanced transmission device characterized by comprising a delay circuit that provides a delay circuit.
JP1987085896U 1987-06-02 1987-06-02 Balanced transmission device Expired - Lifetime JPH062361Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987085896U JPH062361Y2 (en) 1987-06-02 1987-06-02 Balanced transmission device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987085896U JPH062361Y2 (en) 1987-06-02 1987-06-02 Balanced transmission device

Publications (2)

Publication Number Publication Date
JPS63196136U true JPS63196136U (en) 1988-12-16
JPH062361Y2 JPH062361Y2 (en) 1994-01-19

Family

ID=30941718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987085896U Expired - Lifetime JPH062361Y2 (en) 1987-06-02 1987-06-02 Balanced transmission device

Country Status (1)

Country Link
JP (1) JPH062361Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113595581A (en) * 2021-07-28 2021-11-02 深圳市永旭电气技术有限公司 Safe receiving and transmitting state control method and circuit of half-duplex serial port communication circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59160335U (en) * 1983-04-12 1984-10-27 カシオ計算機株式会社 Input/output control circuit
JPS59187253U (en) * 1983-05-28 1984-12-12 コアデジタル株式会社 Data transfer adapter
JPS6257048A (en) * 1985-09-06 1987-03-12 Nec Corp Decentralized processor system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59160335U (en) * 1983-04-12 1984-10-27 カシオ計算機株式会社 Input/output control circuit
JPS59187253U (en) * 1983-05-28 1984-12-12 コアデジタル株式会社 Data transfer adapter
JPS6257048A (en) * 1985-09-06 1987-03-12 Nec Corp Decentralized processor system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113595581A (en) * 2021-07-28 2021-11-02 深圳市永旭电气技术有限公司 Safe receiving and transmitting state control method and circuit of half-duplex serial port communication circuit

Also Published As

Publication number Publication date
JPH062361Y2 (en) 1994-01-19

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