JPS6318864B2 - - Google Patents
Info
- Publication number
- JPS6318864B2 JPS6318864B2 JP2138480A JP2138480A JPS6318864B2 JP S6318864 B2 JPS6318864 B2 JP S6318864B2 JP 2138480 A JP2138480 A JP 2138480A JP 2138480 A JP2138480 A JP 2138480A JP S6318864 B2 JPS6318864 B2 JP S6318864B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- voltage
- floating gate
- drain
- writing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 48
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 230000015654 memory Effects 0.000 claims description 11
- 238000002347 injection Methods 0.000 claims description 10
- 239000007924 injection Substances 0.000 claims description 10
- 230000015556 catabolic process Effects 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000002784 hot electron Substances 0.000 claims description 5
- XUFQPHANEAPEMJ-UHFFFAOYSA-N famotidine Chemical compound NC(N)=NC1=NC(CSCCC(N)=NS(N)(=O)=O)=CS1 XUFQPHANEAPEMJ-UHFFFAOYSA-N 0.000 description 11
- 239000000969 carrier Substances 0.000 description 6
- 230000008859 change Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000002474 experimental method Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7886—Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
Description
【発明の詳細な説明】
本発明は、電気的に書換え可能な不揮発性半導
体記憶装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrically rewritable nonvolatile semiconductor memory device.
不揮発性半導体記憶装置には周知のようにフロ
ーテイングゲートを持つもの、窒化膜を記憶領域
とするMNOS構造のものなどがあり、フローテ
イングゲート型のメモリ例えば電気的書込み、紫
外線消去型のEPROM、或いは電気的書込み、電
気的消去型EEPROM、EAROMでは書込みはい
ずれもアバランシエ降伏に伴なうホツトキヤリア
をフローテイングゲートに注入するという方法で
行なう。第１図はコントロールゲートCGを有す
るFAMOS素子の概略図で、SUBはシリコン半
導体基板（こゝではｐ型とする）である。Ｓ，Ｄ
は基板SUBの表面に浅く形成された反対導電型
のソース、ドレイン領域である。OX1は絶縁膜
で、通常は基板SUBの単結晶シリコンを酸化し
て得たシリコン酸化膜（SiO2）からなり、その
上部に多結晶シリコンまたはモリブデンなどで作
られるフローテイングゲートFGが形成される。
OX2は第２の絶縁膜で、例えばシリコンゲート
FGの上部を酸化して得たシリコン酸化膜からな
り、その上部にアルミニウム（Al）等からなる
コントロールゲートCGが形成される。通常の
FAMOSでは第１層のシリコン酸化膜OX1の厚み
は700〜1500Å程度、また第２層のシリコン酸化
膜OX2の厚みは700〜1500Å程度とする。基板
SUBは接地され、そして書込み時に選択された
メモリセルのドレインＤには該基板との間のpn
接合を逆バイアスする正電圧VDが印加される。
この時の電圧VDは、ドレインＤと基板SUBとの
間にアバランシエ降伏を生じさせるに足る電圧
VDBBを越えるものであり、一般には20〜40Vの高
電圧である。基板SUBにアバランシエ電流が流
れるとそれによりホツトキヤリアが発生するの
で、例えばコントロールゲートCGに正電圧VGを
印加しておけば、酸化膜OX1の障壁を越える高エ
ネルギのホツトエレクトロンがフローテイングゲ
ートFGに注入され、該ゲートを負に帯電させる。
この結果トランジスタのしきい値電圧Vthは上昇
する。このVthの上昇は、例えば情報“１”が書
込まれた状態に対応され、ホツトエレクトロンを
注入しない従つてVthが上昇していない状態は情
報“０”が書込まれた状態に対応される。勿論対
応関係はこの逆でもよい。情報“０”を書込む、
または消去するには通常は紫外線を照射するが、
電気的に行なうには前記アバランシエ降伏状態を
起しかつゲートCGに負の電圧VGを印加して基板
SUBに発生したホツトホールをフローテイング
ゲートFGへ注入し、先に注入したホツトエレク
トロンを消滅させてVthを低下させる。かかる書
込み、消去時にソースＳも接地し（VS＝0V）、ソ
ース、ドレイン間のチヤネル電流による異なるモ
ードのアバランシエ電流を併用することもある
が、いずれにしてもアバランシエ降伏によつて書
込みを行なう点に変りはない。 As is well known, non-volatile semiconductor memory devices include those with a floating gate and those with an MNOS structure in which a nitride film is used as a storage area.Floating gate type memories such as electrical writing and ultraviolet erasing type EPROM, Alternatively, in electrical writing, electrical erasing type EEPROM, and EAROM, writing is performed by injecting hot carriers caused by avalanche breakdown into the floating gate. FIG. 1 is a schematic diagram of a FAMOS element having a control gate CG, and SUB is a silicon semiconductor substrate (here, p-type). S,D
are source and drain regions of opposite conductivity type formed shallowly on the surface of the substrate SUB. OX 1 is an insulating film, usually consisting of a silicon oxide film (SiO 2 ) obtained by oxidizing the single crystal silicon of the substrate SUB, and a floating gate FG made of polycrystalline silicon or molybdenum is formed on top of it. Ru.
OX 2 is a second insulating film, for example a silicon gate.
It is made of a silicon oxide film obtained by oxidizing the upper part of the FG, and a control gate CG made of aluminum (Al) or the like is formed on top of the silicon oxide film. normal
In FAMOS, the thickness of the first layer silicon oxide film OX 1 is about 700 to 1500 Å, and the thickness of the second layer silicon oxide film OX 2 is about 700 to 1500 Å. substrate
SUB is grounded, and the drain D of the memory cell selected during writing has a pn connection between it and the substrate.
A positive voltage V D is applied that reverse biases the junction.
The voltage V D at this time is a voltage sufficient to cause avalanche breakdown between the drain D and the substrate SUB.
It exceeds V DBB and is generally a high voltage of 20 to 40V. When an avalanche current flows through the substrate SUB, it generates hot carriers, so if, for example, a positive voltage V G is applied to the control gate CG, high-energy hot electrons that cross the barrier of the oxide film OX 1 will be transferred to the floating gate FG. is injected into the gate, charging the gate negatively.
As a result, the threshold voltage V th of the transistor increases. This increase in V th corresponds to, for example, a state in which information "1" is written, and a state in which hot electrons are not injected and therefore V th does not rise corresponds to a state in which information "0" is written. be done. Of course, the correspondence relationship may be reversed. Write information “0”,
Or, to erase it, we usually irradiate it with ultraviolet rays, but
To do this electrically, the avalanche breakdown state is brought about and a negative voltage V G is applied to the gate CG to connect the substrate.
The hot holes generated in SUB are injected into the floating gate FG, and the previously injected hot electrons are extinguished to lower V th . During such writing and erasing, the source S is also grounded (V S = 0V), and different modes of avalanche current due to channel current between the source and drain may be used together, but in any case, writing is performed by avalanche breakdown. There is no difference in point.
このようにアバランシエ降伏を利用する
FAMOS素子では、前述したようにドレイン電圧
VDを20〜40Vに高くする必要があるので、一般
的な標準電源（12V、5V等）では不充分となり、
別途に高電圧電源が必要となる。これはメモリチ
ツプで考えれば、端子ピン数を増加させる必要が
あるということである。また半導体チツプには基
板電位を負にシフトする基板バイアス発生器が設
けられ、該基板バイアス発生器により基板を負電
位にするとドレインに与える書込み電圧を相対的
に低くすることが可能であるが、アバランシエ降
伏が生じると基板に大きな電流が流れ、このため
基板バイアス発生器でチヤージポンプして基板電
位を充分に負にすることができなくなる。このた
め従来のFAMOS素子では基板バイアス発生器に
よる基板電位低下、従つて書込み電圧の低減は断
念し、チツプに外部端子を設けて外部電源から基
板負電圧を供給するようにしている。これを要す
るに従来のFAMOSメモリセルでは書込み、消去
電圧が高く、基板バイアスを利用してこれを低減
しようとすると電源回路が複雑になる等の欠点が
ある。 Exploit Avalanche Surrender This Way
In the FAMOS element, as mentioned above, the drain voltage
Since it is necessary to increase V D to 20 to 40V, common standard power supplies (12V, 5V, etc.) are insufficient.
A separate high voltage power supply is required. In terms of memory chips, this means that the number of terminal pins needs to be increased. Furthermore, the semiconductor chip is provided with a substrate bias generator that shifts the substrate potential to a negative potential, and when the substrate bias generator makes the substrate a negative potential, it is possible to relatively lower the write voltage applied to the drain. When avalanche breakdown occurs, a large current flows through the substrate, making it impossible for the substrate bias generator to charge pump and make the substrate potential sufficiently negative. For this reason, in the conventional FAMOS element, the reduction of the substrate potential and therefore the write voltage by a substrate bias generator is abandoned, and an external terminal is provided on the chip to supply a negative substrate voltage from an external power supply. In short, conventional FAMOS memory cells require high write and erase voltages, and attempts to reduce them using substrate bias have drawbacks such as the complexity of the power supply circuit.
第２図のMNOS構造のメモリセルではトンネ
ル注入で書込みが行なわれる。同図においてOX
は20〜50Å程度の薄いシリコン酸化膜であり、そ
の上部にシリコン窒化膜（Si3N4）NIがCVD法
等で形成される。シリコン窒化膜NIはトラツプ
が多いので第１図のフローテイングゲートFGと
同様に機能する。Ｇはゲート電極である。このゲ
ート電極Ｇと基板SUBとの間に電圧Ｅ（25〜50V
程度）を印加して書込みを行なうが、この
MNOS素子で書込みつまり窒化膜NIに電子また
はホールを注入する原理は周知のように薄いシリ
コン酸化膜OXを貫通するトンネル効果である。
即ち酸化膜OXが薄い（50Å以下）とゲート電極
Ｇと基板SUBとの間に電圧を加えることにより
電子またはホールがトンネル効果により酸化膜
OXを通つて窒化膜NIに入り、該窒化膜中にトラ
ツプされる。こうしてアバランシエを利用せずに
不揮発性メモリセルへの書込み、消去を行なうこ
とができるが、この場合の酸化膜OXの厚みは薄
い必要があり、一方、酸化膜OXが薄いと長期間
の電荷保持の点で難がある。FAMOSでは20〜30
年以上の耐用年数があるが、MNOSでは10年持
つかどうか凝わしいという程度である。 In the memory cell of the MNOS structure shown in FIG. 2, writing is performed by tunnel injection. In the same figure, OX
is a thin silicon oxide film with a thickness of about 20 to 50 Å, and a silicon nitride film (Si 3 N 4 ) NI is formed on top of it by a CVD method or the like. Since the silicon nitride film NI has many traps, it functions similarly to the floating gate FG shown in FIG. G is a gate electrode. A voltage E (25 to 50V) is applied between this gate electrode G and the substrate SUB.
writing is performed by applying a
The principle of writing in the MNOS element, that is, injecting electrons or holes into the nitride film NI, is the well-known tunnel effect that penetrates the thin silicon oxide film OX.
In other words, when the oxide film OX is thin (less than 50 Å), when a voltage is applied between the gate electrode G and the substrate SUB, electrons or holes are tunneled through the oxide film.
It enters the nitride film NI through OX and is trapped in the nitride film. In this way, it is possible to write to and erase nonvolatile memory cells without using an avalanche, but in this case the thickness of the oxide film OX needs to be thin, and on the other hand, if the oxide film OX is thin, the charge can be retained for a long time. There are difficulties in this respect. 20-30 at FAMOS
It has a useful life of over 10 years, but MNOS is only concerned about whether it will last 10 years.
ところでFAMOSの書込み（消去）電圧の低電
圧化が要請される中で、本発明者等によりなされ
た実験で注目すべきデータが得られた。その一例
を第３図に示す。同図に示す特性は、第１図の素
子構造で第１層のシリコン酸化膜OX1の厚みを
100Åにした時のドレイン電圧VDとしきい値Vth
の関係、従つて書込み（消去）特性を示したもの
で、チヤネル長Ｌをパラメータ（３、４、５、
7μｍ）としたものである。チヤネル幅Ｗはいず
れも10μｍであり、またソースＳおよび基板SUB
は接地してある。なおこの実験では第１層絶縁膜
OX1として熱窒化膜を使用し、また充分飽和した
Vthを得るため書込み時間は200secとした。勿論、
実際には書込みはVthが飽和するまで長時間行な
う必要はなく、書込み時間は上記より遥かに短い
ものにしてよい。Initは初期状態のVthを示すも
ので、曲線C1〜C4はVG＝0Vとしたホール注入の
時の特性、また曲線C5〜C8はVG＝12Vとしたエ
レクトロン注入時の特性である。これらの素子の
アバランシエ電圧は9Vであるが、9V＞VD＞3V
の範囲でVthが大きく変化する点が注目される。
このことはアバランシエ降伏によらずに多量のホ
ツトエレクトロン（C5〜C8の場合）またはホツ
トホール（C1〜C4の場合）がフローテイグゲー
トFGに注入されることを示している。そして、
VD＜3Vの範囲ではVthに変化はないので、例えば
VG＝12V、VD＝6Vで書込み（エレクトロン注
入）、そしてVG＝0Vで読出し動作を行なえば、
Vth＝−３〜−6VとVth＝10〜12Vの差に基づく
相違（一方がオン、他方がオフ）を検出できる。 By the way, while there is a demand for lower write (erase) voltages for FAMOS, noteworthy data was obtained in experiments conducted by the present inventors. An example is shown in FIG. The characteristics shown in the figure are based on the thickness of the first layer of silicon oxide film OX 1 in the device structure shown in Figure 1.
Drain voltage V D and threshold value V th when set to 100 Å
This shows the relationship between the channel length L and the write (erase) characteristics.
7 μm). The channel width W is 10 μm in both cases, and the source S and substrate SUB
is grounded. Note that in this experiment, the first layer insulating film
A thermal nitride film was used as OX 1 , and a sufficiently saturated
The writing time was set to 200 seconds to obtain V th . Of course,
In reality, writing does not need to be performed for a long time until V th is saturated, and the writing time may be much shorter than the above. Init indicates V th in the initial state, curves C 1 to C 4 are the characteristics when hole injection is performed with V G = 0V, and curves C 5 to C 8 are the characteristics when electron injection is performed when V G = 12V. It is a characteristic. The avalanche voltage of these devices is 9V, but 9V > V D > 3V
It is noteworthy that V th changes significantly in the range of .
This indicates that a large amount of hot electrons (in the case of C 5 to C 8 ) or hot holes (in the case of C 1 to C 4 ) are injected into the floating gate FG without avalanche breakdown. and,
There is no change in V th in the range of V D < 3V, so for example
If a write operation (electron injection) is performed with V G = 12V and V D = 6V, and a read operation is performed with V G = 0V, then
Differences (one is on and the other is off) based on the difference between V th =-3 to -6V and V th =10 to 12V can be detected.
本発明はかかる実験事実に基いてなされたもの
で、その特徴とするところはシリコン半導体基板
にソース、ドレイン領域を形成し、これらの領域
間の該基板上にフローテイングゲート及びコント
ロールゲートを設けたトランジスタよりなるメモ
リセルを有する電気的書換え可能な不揮発性記憶
装置において、該基板中のチヤージを吸収して該
基板に負のバツクバイアスを印加する基板バイア
ス発生器が設けられ、該フローテイングゲートと
シリコン基板間に80〜300Åのシリコン酸化膜が
設けられ、該基板とドレインとの間及び該ソース
とドレインとの間へのアバランシエ降伏電圧未満
の電圧の印加により該基板中に発生したホツトホ
ール又はホツトエレクトロンを前記コントロール
ゲートに印加した電位に応じて前記フローテイン
グゲートに注入するようにしたことにある。 The present invention was made based on such experimental facts, and is characterized by forming source and drain regions on a silicon semiconductor substrate, and providing a floating gate and a control gate on the substrate between these regions. In an electrically rewritable nonvolatile memory device having a memory cell made of a transistor, a substrate bias generator is provided that absorbs charge in the substrate and applies a negative back bias to the substrate, and the floating gate and A silicon oxide film with a thickness of 80 to 300 Å is provided between silicon substrates, and hot holes or hot spots are generated in the substrate by applying a voltage lower than the avalanche breakdown voltage between the substrate and the drain and between the source and the drain. Electrons are injected into the floating gate according to the potential applied to the control gate.
第３図の実験データはOX1＝100Åに関するも
のであるから、第２図のMNOS素子と同様にト
ンネル効果が生じたという可能性はなく、そして
VD＜8Vであるからアバランシエ降伏も否定され
る。従つて、このVthの変化は、アバランシエ注
入ではなく、またトンネル注入でもないメカニズ
ムでなされたものであり、これは基板SUBに発
生したホツトキヤリアがシリコン酸化膜OX1の電
位障壁を越えてフローテイングゲートFGに注入
されたためと考えられる。酸化膜OX1の膜厚は、
薄過ぎると電荷保持の点で難があり、厚過ぎると
ホツトキヤリアの通過および微細パターン化によ
る高集積化等の点で難があるから、実用上は300
〜80Å程度の範囲が好ましい。第３図の曲線C1
〜C4がホール注入によるVth変化で、またC5〜C8
がエレクトロン注入によるVth変化であり、これ
らが逆極性を示すことから、書込みおよび消去を
電気的に行ない得ることが分る。そして、アバラ
ンシエ電圧以下の電圧でこの書込み、消去ができ
ることから、次の利点が導びき出される。(1)書込
み、消去電圧VDが５〜6V程度に低下させ得るの
で標準電源だけで充分である。(2)アバランシエ電
流が流れないので基板電流は極く僅か（1μA以
下）であり、基板バイアス発生器で充分に吸収で
きる。このため書込み中も基板バイアス発生器の
みで基板SUBの電位を負側へシフトさせること
ができ、この負側へのシフト分だけ書込みに要す
るドレイン電圧VDを更に低下させることができ
る。なお書込み消去電圧が５〜6Vという本発明
素子の電圧条件は通常のMOSICの電源電圧
（ほゞ4V）に近いが、かゝる電圧条件で従来の
MOSICメモリに誤書込み、誤消去がなされない
のは、第１層絶縁膜OX1の厚み差等によると考え
られる。また本発明素子では読出し時にはドレイ
ン電圧VDは第３図などに示されるエレクトロン
又はホール注入のない電圧範囲の値とし、誤書込
み誤消去がないようにする。 Since the experimental data in Fig. 3 is for OX 1 = 100 Å, there is no possibility that a tunneling effect occurred as in the MNOS device shown in Fig. 2, and
Since V D <8V, avalanche breakdown is also ruled out. Therefore, this change in V th is caused by a mechanism that is neither avalanche injection nor tunnel injection, and is caused by hot carriers generated in the substrate SUB floating over the potential barrier of the silicon oxide film OX1 . This is thought to be because it was injected into the gate FG. The thickness of the oxide film OX 1 is
If it is too thin, it will be difficult to retain charge, and if it is too thick, it will be difficult to pass hot carriers and achieve high integration through fine patterning.
A range of approximately 80 Å is preferable. Curve C 1 in Figure 3
~ C4 is V th change due to hole injection, and C5 ~ C8
is the change in V th due to electron injection, and since these exhibit opposite polarities, it can be seen that writing and erasing can be performed electrically. Since writing and erasing can be performed with a voltage lower than the avalanche voltage, the following advantages are derived. (1) Since the write/erase voltage V D can be lowered to about 5 to 6 V, a standard power supply is sufficient. (2) Since no avalanche current flows, the substrate current is extremely small (1 μA or less) and can be sufficiently absorbed by the substrate bias generator. Therefore, even during writing, the potential of the substrate SUB can be shifted to the negative side using only the substrate bias generator, and the drain voltage V D required for writing can be further reduced by the amount of this shift to the negative side. Note that the voltage condition of the device of the present invention, where the write/erase voltage is 5 to 6 V, is close to the power supply voltage of a normal MOSIC (approximately 4 V);
The reason why erroneous writing and erasing are not performed in the MOSIC memory is considered to be due to the difference in thickness of the first layer insulating film OX1 . Further, in the device of the present invention, during reading, the drain voltage V D is set to a value within a voltage range in which no electron or hole injection occurs as shown in FIG. 3, etc., to prevent erroneous writing or erasing.
第４図は基板バイアス発生器を用いたFAMOS
のしきい値電圧に対するバツクバイアス効果を示
す実験データで、曲線C9〜C13はバツクゲートバ
イアスVBGをパラメータ（０、−１、−２、−３、−
4V）としたものである。実験に用いたFAMOS
メモリセルのアバランシエ電圧は13.5Vで、ゲー
ト電圧はVG＝6Vである。ソースは接地して電気
的書込みを行なつた。VBGを負方向へ増大するこ
とによつてより低いドレイン電圧VDでVthを変化
させることができる点は特性全体に共通すること
であるが、その変化幅はバツクバイアス相当分だ
けのものではない。例えば曲線C9とC13では4Vの
差があるのでC13のVD＝２はC9のVD＝６に相当す
るが、各々のVthは前者が２、後者が−７であり、
9Vの差がある。従つてVBG印加に対しては相乗的
な効果が期待される。 Figure 4 shows FAMOS using a substrate bias generator.
Curves C 9 to C 13 are experimental data showing the back bias effect on the threshold voltage of V BG .
4V). FAMOS used in the experiment
The avalanche voltage of the memory cell is 13.5V, and the gate voltage is V G =6V. The source was grounded for electrical writing. The fact that V th can be changed with a lower drain voltage V D by increasing V BG in the negative direction is common to all characteristics, but the width of the change is only equivalent to the back bias. isn't it. For example, there is a 4V difference between curves C 9 and C 13 , so V D = 2 for C 13 corresponds to V D = 6 for C 9 , but each V th is 2 for the former and -7 for the latter,
There is a difference of 9V. Therefore, a synergistic effect is expected with respect to VBG application.
以上述べたように本発明では、シリコン基板
SUBとフローテイングゲートFGとの間の絶縁膜
OX1の厚みを300〜80Åと薄くし、基板バイアス
発生器を動作させながらドレイン、基板間にアバ
ランシエ電圧未満の電圧を印加してホツトキヤリ
アを発生させ、コントロールゲートに印加する電
位によりそのホツトホール又はホツトエレクトロ
ンをフローテイングゲートに選択的に注入するよ
うにしたので、低いドレイン電圧での迅速な書込
み、消去が可能になり、FAMOSチツプの電源端
子数を減少でき、甚だ有効である。 As described above, in the present invention, silicon substrate
Insulating film between SUB and floating gate FG
The thickness of OX 1 is reduced to 300 to 80 Å, and a voltage lower than the avalanche voltage is applied between the drain and the substrate while operating the substrate bias generator to generate hot carriers, and the hot carriers are removed by the potential applied to the control gate. Since electrons are selectively injected into the floating gate, rapid writing and erasing can be performed with a low drain voltage, and the number of power supply terminals of the FAMOS chip can be reduced, which is extremely effective.
第１図はFAMOSの概略構成図、第２図は
MNOSの概略構成図、第３図は本発明の書込み、
消去法を説明する特性図、第４図はバツクバイア
ス効果を示す特性図である。
図中、SUBはシリコン半導体基板、Ｓはソー
ス、Ｄはドレイン、OX1はシリコン酸化膜、FG
はフローテイングゲートである。
Figure 1 is a schematic configuration diagram of FAMOS, Figure 2 is
A schematic configuration diagram of MNOS, Figure 3 shows the writing of the present invention,
FIG. 4 is a characteristic diagram illustrating the elimination method and a characteristic diagram showing the back bias effect. In the figure, SUB is a silicon semiconductor substrate, S is a source, D is a drain, OX 1 is a silicon oxide film, FG
is a floating gate.
Claims (1)
を形成し、これらの領域間の該基板上にフローテ
イングゲート及びコントロールゲートを設けたト
ランジスタよりなるメモリセルを有する電気的書
換え可能な不揮発性記憶装置において、 該基板中のチヤージを吸引して該基板に負のバ
ツクバイアスを印加する基板バイアス発生器が設
けられ、 該フローテイングゲートとシリコン基板間に80
〜300Åのシリコン酸化膜が設けられ、 該基板とドレインとの間及び該ソースとドレイ
ンとの間へのアバランシエ降伏電圧未満の電圧の
印加により該基板中に発生したホツトホール又は
ホツトエレクトロンを前記コントロールゲートに
印加した電位に応じて前記フローテイングゲート
に注入するようにしたことを特徴とする不揮発性
記憶装置。[Claims] 1. An electrically rewritable non-volatile memory cell having a memory cell formed of a transistor in which source and drain regions are formed on a silicon semiconductor substrate and a floating gate and a control gate are provided on the substrate between these regions. In the storage device, a substrate bias generator is provided which sucks charge in the substrate and applies a negative back bias to the substrate, and an 80° bias voltage is provided between the floating gate and the silicon substrate.
A silicon oxide film with a thickness of ~300 Å is provided, and hot holes or hot electrons generated in the substrate by applying a voltage lower than the avalanche breakdown voltage between the substrate and the drain and between the source and the drain are transferred to the control gate. 1. A nonvolatile memory device, characterized in that injection is carried out into the floating gate according to a potential applied to the floating gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2138480A JPS56129374A (en) | 1980-02-22 | 1980-02-22 | Writing and cancelling methods of fixed memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2138480A JPS56129374A (en) | 1980-02-22 | 1980-02-22 | Writing and cancelling methods of fixed memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56129374A JPS56129374A (en) | 1981-10-09 |
| JPS6318864B2 true JPS6318864B2 (en) | 1988-04-20 |
Family
ID=12053586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2138480A Granted JPS56129374A (en) | 1980-02-22 | 1980-02-22 | Writing and cancelling methods of fixed memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56129374A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6045999A (en) * | 1983-08-24 | 1985-03-12 | Hitachi Ltd | Semiconductor non-volatile storage device |
| JPH01123454A (en) * | 1987-11-07 | 1989-05-16 | Mitsubishi Electric Corp | Nonvolatile semiconductor memory |
| JP2848223B2 (en) * | 1993-12-01 | 1999-01-20 | 日本電気株式会社 | Erasing method and manufacturing method for nonvolatile semiconductor memory device |
| US7796442B2 (en) | 2007-04-02 | 2010-09-14 | Denso Corporation | Nonvolatile semiconductor memory device and method of erasing and programming the same |
-
1980
- 1980-02-22 JP JP2138480A patent/JPS56129374A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56129374A (en) | 1981-10-09 |
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