JPS6318638A - Testing method for semiconductor device - Google Patents
Testing method for semiconductor deviceInfo
- Publication number
- JPS6318638A JPS6318638A JP16331086A JP16331086A JPS6318638A JP S6318638 A JPS6318638 A JP S6318638A JP 16331086 A JP16331086 A JP 16331086A JP 16331086 A JP16331086 A JP 16331086A JP S6318638 A JPS6318638 A JP S6318638A
- Authority
- JP
- Japan
- Prior art keywords
- writing
- aging
- wafer
- time
- user
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 230000032683 aging Effects 0.000 claims abstract description 24
- 239000011347 resin Substances 0.000 claims abstract description 8
- 229920005989 resin Polymers 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 14
- 238000010998 test method Methods 0.000 claims description 3
- 238000007689 inspection Methods 0.000 abstract description 5
- 230000002950 deficient Effects 0.000 abstract description 4
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 230000007547 defect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 208000000044 Amnesia Diseases 0.000 description 1
- 208000026139 Memory disease Diseases 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006984 memory degeneration Effects 0.000 description 1
- 208000023060 memory loss Diseases 0.000 description 1
- 238000003878 thermal aging Methods 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
製品組立後1回だけ書込みが可能な、UPI”20M構
造のチップを樹脂モールドした、所謂ワンタイムE P
ROM (Onetime Erasable Pr
ogram−mable Read 0nly Mem
ory )において、ウェーハの状態で、通常の使用時
に書込む電荷量より少ない書込みを行い、ついでエージ
ングを挟んで読みだしテス)・を行い、電荷量の減少状
態を検査するもので、納期の短縮化とユーザでの書込み
が可能となる。[Detailed Description of the Invention] [Summary] A so-called one-time EP in which a chip with a UPI"20M structure is molded in resin and can be written only once after product assembly.
ROM (Onetime Erasable Pr
ogram-mable Read 0nly Mem
(ory), the wafer is written with a smaller amount of charge than would be written during normal use, and then read out after aging (test) to inspect the state of decrease in the amount of charge, which shortens the delivery time. It is now possible to create and write data by the user.
本発明はワンタイムEPRO〜1の試験方法に係わり、
詳しくは不充分書込みとエージングを含むワンタイムE
PROMの試験方法に[即する。The present invention relates to a test method for One Time EPRO~1,
For details, see One-time E including incomplete writing and aging.
Follow the PROM test method.
ワンタイムEPROMは一般のEFROMに使用する構
造の半導体素子を価格を安くするために、パッケージを
樹脂モールドとしたもので、消去が出来ないので機能的
にはFROMとなっており、ユーザに出荷された後でも
書込みが可能であるとして最近開発されたメモリ素子で
ある。One-time EPROM is a semiconductor element with a structure used in general EFROM, but in order to reduce the price, the package is molded in resin, and since it cannot be erased, it is functionally a FROM, and is shipped to the user. This is a recently developed memory element that can be written to even after it has been stored.
第2図はワンタイムEPROMの構造を示す断面模式図
である。FIG. 2 is a schematic cross-sectional diagram showing the structure of a one-time EPROM.
この図は、EPROMの一種のSへ〜10S(Stac
ked gat、e Avalanche 1njec
tion MOS)の−般的な構造のもので、ゲート酸
化膜33上に電荷を蓄積するフローティングゲート31
をもち、その上にゲート間酸化膜311を挟んでコント
ロールゲート32を形成した構造となっている。This figure shows a type of EPROM S to 10S (Stac
ked gat,e Avalanche 1njec
A floating gate 31 that accumulates charge on a gate oxide film 33 has a general structure of
, and a control gate 32 is formed thereon with an inter-gate oxide film 311 interposed therebetween.
このフローティングゲート31に書込みにより電荷が注
入され、半永久的に保存される。Charge is injected into this floating gate 31 by writing and is stored semi-permanently.
しかし、ゲート酸化膜33、ゲート間酸化膜34におけ
る欠陥等に基づくリーク不良により蓄積した電荷が減少
消失するものがある。 即ちメモリが消える不良素子が
僅かながら混入するため、これを除去してユーザに供給
する必要が生ずる。However, there are cases in which the accumulated charge decreases and disappears due to leakage failure due to defects in the gate oxide film 33 and the inter-gate oxide film 34. That is, since a small amount of defective elements that cause the memory to disappear are mixed in, it becomes necessary to remove them and supply them to the user.
このため、半導体メーカは工場で書込み、エージングし
て劣化するものを除去してユーザに出荷している状況で
ある。For this reason, semiconductor manufacturers are writing at the factory, removing anything that deteriorates due to aging, and then shipping it to users.
そのため、ユーザよりの注文を受けて出荷までの日数、
即ちターンアラウンドタイムは、エージングおよびテス
トがあるため1週間〜108間を要している。Therefore, the number of days from receiving an order from a user to shipping,
That is, the turnaround time is 1 week to 108 days due to aging and testing.
従って、ターンアラウンドタイムを短縮することと、ユ
ーザ自身で書込みが出来る当初の目標を実現することが
望まれている。Therefore, it is desired to shorten the turnaround time and realize the original goal of allowing users to write on their own.
第4図は従来例における装造工程ブロック図である。 FIG. 4 is a block diagram of the manufacturing process in a conventional example.
この図において、ウェーハプロセス(WP)1を完了し
たEPROM構造のウェーハは一次ブローブ(PP)2
1の工程に送られる。このPP21の工程においては、
まず消去2を行い、ついで通常の使用時と略同じ条件で
書込み3を行う。In this figure, a wafer with an EPROM structure that has completed wafer process (WP) 1 has a primary probe (PP) 2.
Sent to step 1. In this PP21 process,
First, erase 2 is performed, and then write 3 is performed under substantially the same conditions as during normal use.
更に、読みだしテスト4によりメモリの保存性について
テストし、ついで消去7により書き込んだものを全部消
去する。Furthermore, the read test 4 tests the storability of the memory, and then the erase 7 erases all written data.
上記のPP21の完了したウェーハは組立8の工程を経
て工場検査(FT)22の工程に送られる。The wafers that have undergone the above-mentioned PP21 are sent to the factory inspection (FT) 22 process through the assembly process 8.
組立8において、ウェーハは個々のチップに切り離され
た後、樹脂モールドのパッケージに収納される。In assembly 8, the wafer is cut into individual chips and then housed in a resin mold package.
FT22においては、ユーザの指定する仕様のメモリ内
容を書き込む書込みlOを行う。ついで、例えば125
〜150”C148時間のエージング5を行う。In FT22, a write operation is performed to write the memory contents according to the specifications specified by the user. Then, for example, 125
Perform aging 5 for 148 hours at ~150''C.
つぎに、読みだしテストを含んだDC−FNテスト9を
行うことにより、エージング5による劣化でメモリが消
失するものは除去する。Next, a DC-FN test 9 including a read test is performed to eliminate memory loss due to deterioration due to aging 5.
以上を半導体メーカで実施してユーザに出荷11をする
。The semiconductor manufacturer carries out the above steps and ships the product 11 to the user.
このような方法によると、ユーザがメモリの仕様を決め
て発注し品物を受は取るまでのターンアラウンドタイム
は大体7〜10日間を要する。According to this method, the turnaround time for a user to decide on memory specifications, place an order, and receive the item is approximately 7 to 10 days.
以上のような方法をとるのは、現在のワンタイムEPR
OMは組立だままでは、その品質が充分でなく使用中に
劣化してメモリが消える不良があり、これを熱エージン
グによる加速テストで除去するためである。The method described above is used in the current one-time EPR.
This is because when an OM is assembled, its quality is not sufficient and there is a defect that deteriorates during use and erases the memory, and this is removed by an accelerated test using thermal aging.
[発明が解決しようとする問題点]
従来例の半導体ノー力が書込みを行う出荷法によると、
ユーザから注文を受けて出荷までの所要日数が大である
。これの短縮化を図る。[Problems to be Solved by the Invention] According to the conventional shipping method in which writing is performed without any semiconductor power,
It takes a long time from receiving an order from a user to shipping. We will try to shorten this time.
上記問題点の解決は、EPROM構造の半導体チップを
樹脂モールドに封入し、製品組立完了後1回だけ書込み
が可能な半導体装置の試験方法において、ウェーハプロ
セス(1)完了後のウェーハに対して、通常の使用時の
書込み電荷量以下で書込む不充分書込み(3A)を行い
、その後エージング(5)を挟んで読みだしテスト(4
)および(6)を行い、エージング(5)の前後の電荷
量を比較検査する本発明による半導体装置の試験方法に
より達成される。The solution to the above problem is that in a testing method for semiconductor devices in which a semiconductor chip with an EPROM structure is encapsulated in a resin mold and can be written only once after product assembly, on a wafer after the wafer process (1) is completed, Insufficient writing (3A) is performed with less than the writing charge amount during normal use, and then a reading test (4) is performed with aging (5) in between.
) and (6) and compares and tests the amount of charge before and after aging (5).
[作用]
ワンタイムE P ROMにおいて、PP工程でウェー
ハの状態で、通常の使用時に書込む電荷量より少ない不
充分書込みを行い、ついでエージングを挟んで読みだし
テストを行い、電荷量の減少状態を検査し不良を除去す
るもので、エージングが先に行っであるので納期の短縮
化が可能となり、またユーザで不良が発生することがな
くなるため、ユーザでの書込みが可能となる。[Operation] In one-time EP ROM, insufficient writing is performed in the wafer state during the PP process, which is less than the amount of charge written during normal use, and then a reading test is performed after aging to determine the state in which the amount of charge has decreased. Since aging is performed first, delivery time can be shortened, and since defects are not generated by the user, it is possible to write by the user.
第1図は本発明における製造工程ブロック図である。 FIG. 1 is a block diagram of the manufacturing process in the present invention.
この図において、WPIを完了したEPROM構造のウ
ェーハはPP21の工程に送られ、消去2を行うまでは
従来例に示すものと同じである。In this figure, a wafer having an EPROM structure that has completed WPI is sent to the process of PP21, and is the same as that shown in the conventional example until erase 2 is performed.
つぎに、不充分書込み3Aにより通常の使用時に書き込
む電荷量よりは少ない電荷量の書込みを行う。電荷量は
電圧と時間を調整して通常値の1ノ10〜1/20のも
のを書き込む。これは、例えば、コントロールゲート・
ソース電圧VGS−21V、時間=50 m5ecの通
常値に対して、不充分書込みは、VG!!=21V、時
間−2〜5m5ec程度の書込みを行う。Next, insufficient writing 3A is performed to write an amount of charge smaller than the amount of charge written during normal use. The amount of charge is written at 1/10 to 1/20 of the normal value by adjusting the voltage and time. This is for example a control gate
For the normal value of source voltage VGS-21V, time = 50 m5ec, insufficient writing is VG! ! =21V, writing is performed for a time of about -2 to 5 m5ec.
ついで、読みだしテスト4を実施し、エージング前の初
期値を確認する。Next, readout test 4 is performed to confirm the initial value before aging.
つぎに、125〜150″C124時間のエージング5
を実施した後、再び読みだしテストロを行い電荷量消失
の大きいものを不良として除去する。Next, aging 5 at 125-150″C for 124 hours.
After carrying out the test, a readout test is performed again, and those with a large amount of charge dissipated are removed as defective.
ついで消去7により書き込んだものを全部消去する。Then, by erasing 7, all written data is erased.
上記のPP21の完了したウェーハは組立8の工程で樹
脂モールドパッケージに収容されてFT22の工程に送
られる。消去チェ・ツク+DC−FNテスト9を行った
後、ルーh (I)またはルート(II)のルートによ
り出荷11をされる。The wafer that has undergone the above PP21 is housed in a resin mold package in the assembly process 8 and is sent to the FT22 process. After performing the erase check + DC-FN test 9, the product is shipped 11 via route (I) or route (II).
ルート(■)のものはユーザの注文で半導体メーカが書
き込んで出荷11をするものであるが、従来例で示す如
きエージングを注文後行う必要がないので、ターンアラ
ウンドタイムはこのエージング時間だけ確実に短縮され
る。The route (■) is written by the semiconductor manufacturer based on the user's order and shipped 11, but there is no need to perform aging after placing the order as in the conventional example, so the turnaround time is guaranteed by this aging time. be shortened.
また、ルート(I)のものはユーザで書き込まれるもの
であるが、半導体メーカにおいてエージングにより、劣
化する可能性のあるものは充分選別除去されているので
、ユーザにおいて簡単なROMライターで書込み、安心
して使用することが可能となる。In addition, the root (I) data is written by the user, but semiconductor manufacturers have carefully selected and removed those that may deteriorate due to aging, so the user can write it with a simple ROM writer and safely. It can be used with care.
第3図は”)7タイムEPROM(7)In VG
S特性図である。■。はドレイン電流、■、3はコント
ロールゲート・ソース電圧で、メモリに電荷が注入され
ていない消去状態では特性曲線は図の左端の曲線となり
、所謂電荷“0”の状態である。また、通常の使用時の
書込み状態では右端の曲線となり、電荷“1”の状態と
なる。Figure 3 is 7-time EPROM (7) In VG.
It is an S characteristic diagram. ■. is the drain current, and 3 is the control gate/source voltage. In the erased state where no charge is injected into the memory, the characteristic curve becomes the curve at the left end of the figure, which is the so-called charge "0" state. Further, in the write state during normal use, the curve is at the right end, and the charge is "1".
不充分書込み状態では、前記三者の中間の曲線群となる
。In an insufficiently written state, a group of curves is in between the above three.
エージングを行ったとき酸化膜等に欠陥があると、電荷
が失われ曲線は左に移動する。If there is a defect in the oxide film or the like during aging, charge is lost and the curve shifts to the left.
同じエージングを行っても、使用時の書込み状態にある
ものに比べて、不充分書込み状態のものは変化率が大き
いこと及び最初の電荷量が少ないので、電荷“1”の状
態から、電荷“0”の状態に早くなる。従って、短時間
のエージングで不良品を除去することが可能となる。Even if the same aging is performed, the rate of change in the insufficiently written state is larger and the initial charge amount is smaller than that in the written state during use, so the charge changes from the state of charge "1" to "1". 0” state quickly. Therefore, it is possible to remove defective products with short aging time.
以上詳細に説明したように、本発明によるとワンタイム
EPROMの納期を短縮できるか、あるいはユーザによ
る書込みが可能となる。As described in detail above, according to the present invention, the delivery time for one-time EPROMs can be shortened or writing can be performed by the user.
第1図は本発明における製造工程ブロック図、第2図は
ワンタイムEPROMの構造を示す断面模式図、
第3図は’77タイムE P ROM ノIn V
cs特性図、
第4図は従来例における製造工程ブロック図である。
この図において、
■はウェーハプロセス(WP)、
2.7は消去、
3Aは不充分の込み、
4.6は読みだしテスト、
5はエージング、
8は組立、
9はDC,、FNテスト、
10は書込み、
11 は出荷、
21は一次プローブ(PP)、
22は工場4全査(FTン、
31はフコ−ティングゲート、
32はコントロールゲート、
33はゲート酸化膜、
34はゲート間酸化膜
旧宅ヱ狙;几゛(アを茨直工屁ブ゛ロツ20景 (口
ワレ2イb EPROr−q、y)$生り出消郵め欺因
不 2 叩
ゲートソーi−富凡(■シ
ワ″/9イ、 g P、r;20.1./I 01 D
−Vc、s ’rv+’rl’J界 3 ZFig. 1 is a manufacturing process block diagram of the present invention, Fig. 2 is a cross-sectional schematic diagram showing the structure of a one-time EPROM, and Fig. 3 is a block diagram of a one-time EPROM.
cs characteristic diagram, FIG. 4 is a manufacturing process block diagram in a conventional example. In this figure, ■ is wafer process (WP), 2.7 is erase, 3A is insufficient inclusion, 4.6 is read test, 5 is aging, 8 is assembly, 9 is DC, FN test, 10 is writing, 11 is shipping, 21 is primary probe (PP), 22 is full inspection of factory 4 (FT), 31 is front coating gate, 32 is control gate, 33 is gate oxide film, 34 is old house of oxide film between gatesヱAim; ゛〇゛ ゛ 〄〄 Birth, disappearance mail 2 Slap gate saw - /9i, g P,r;20.1./I 01 D
-Vc, s'rv+'rl'J world 3 Z
Claims (1)
、製品組立完了後1面だけ書込みが可能な半導体装置の
試験方法において、 ウェーハプロセス(1)完了後のウェーハに対して、通
常の使用時の書込み電荷量以下で書込む不充分書込み(
3A)を行い、 その後エージング(5)を挟んで読みだしテスト(4)
および(6)を行い、エージング(5)の前後の電荷量
を比較検査する ことを特徴とする半導体装置の試験方法。[Claims] In a test method for a semiconductor device in which a semiconductor chip with an EPROM structure is sealed in a resin mold and writing can be performed on only one side after the product assembly is completed, the wafer after the wafer process (1) is normally Insufficient writing (writing with less than the writing charge amount when using
3A), then aging (5) and reading test (4).
and (6), and compares and inspects the amount of charge before and after aging (5).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16331086A JPS6318638A (en) | 1986-07-11 | 1986-07-11 | Testing method for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16331086A JPS6318638A (en) | 1986-07-11 | 1986-07-11 | Testing method for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6318638A true JPS6318638A (en) | 1988-01-26 |
Family
ID=15771399
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16331086A Pending JPS6318638A (en) | 1986-07-11 | 1986-07-11 | Testing method for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6318638A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007184490A (en) * | 2006-01-10 | 2007-07-19 | Renesas Technology Corp | Manufacturing method of semiconductor device |
-
1986
- 1986-07-11 JP JP16331086A patent/JPS6318638A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007184490A (en) * | 2006-01-10 | 2007-07-19 | Renesas Technology Corp | Manufacturing method of semiconductor device |
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