JPS63185063A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63185063A JPS63185063A JP1758787A JP1758787A JPS63185063A JP S63185063 A JPS63185063 A JP S63185063A JP 1758787 A JP1758787 A JP 1758787A JP 1758787 A JP1758787 A JP 1758787A JP S63185063 A JPS63185063 A JP S63185063A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- oxide film
- emitter
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims description 18
- 230000003321 amplification Effects 0.000 abstract description 4
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000012298 atmosphere Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明に半導体装置の製造方法に関し、特に横型トラン
ジスタを備えた半導体集積回路の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor integrated circuit including a lateral transistor.
、〔従来の技術〕
従来の横型トランジスタに、マ撤埋込層を有するＰ型基
板上にＮ型エピタキシャル層を形成する。, [Prior Art] In a conventional lateral transistor, an N-type epitaxial layer is formed on a P-type substrate having a buried layer.
次に、Ｎ型エピタキシャル層上に形成された絶縁膜の所
定部を開口し、Ｐ型不純物を導入し、エミッタ、コレク
タを形成する。次に、絶縁膜の所定部を開口し、を型不
純物を導入し、ベースコンタクト用を層を形成し、横型
）’ＮＰトランジスタを得ている。Next, a predetermined portion of the insulating film formed on the N-type epitaxial layer is opened and a P-type impurity is introduced to form an emitter and a collector. Next, a predetermined portion of the insulating film is opened, a type impurity is introduced, and a base contact layer is formed to obtain a lateral NP transistor.
上述した従来の製造方法は、工程が短いといり長所はめ
るが、この方法で形成された横型トランジスタは次の様
な欠点がある。従来の横型トランジスタの不純物プロフ
ァイルを半河数目盛でめられした特性図を第５図に示す
。この濃度プロファイルはベース層の不純物濃度は均一
でコレクタ層の不純物濃度にベースに比べて十分高くな
っている。したがって、ベース・コレクタ間を逆バイア
スしたときの空乏層のほとんどに低濃度側のベース層に
のびる為、エミッタ・コレクタがパンチスルにより耐圧
が低下しない様にベース幅を十分大きくとる構造となっ
ている。この結果、電流増幅率ｈＦＢが小さく遮断周波
数ｆｒも小さいという欠点がおる。Although the conventional manufacturing method described above has the advantage of short process steps, the lateral transistor formed by this method has the following drawbacks. FIG. 5 shows a characteristic diagram showing the impurity profile of a conventional lateral transistor on a half-height scale. In this concentration profile, the impurity concentration in the base layer is uniform and the impurity concentration in the collector layer is sufficiently higher than that in the base. Therefore, when reverse bias is applied between the base and collector, most of the depletion layer extends to the base layer on the low concentration side, so the base width is designed to be sufficiently large so that the withstand voltage does not drop due to emitter-collector punch-slip. . As a result, there is a drawback that the current amplification factor hFB is small and the cutoff frequency fr is also small.
本発明の半導体装置の製造方法は、高濃度の第２導電型
埋込層をもつ第１導電型半導体基板の上に形成された第
２導電型エピタキシャル層に、不純物濃度が、前記エピ
タキシャル層の不純物濃度と同程度の第２導型のコレク
タ層を選択的に形成する工程と、前記コレクタ層に不純
物濃度が前記コレクタ層の不純物濃度より高い＠１４電
型のベース層を形成する工程と、前記ベース層に第１導
を型のエミツタ層を自己整合を有して選択的に形成する
工程とを含んで構成される。In the method for manufacturing a semiconductor device of the present invention, a second conductivity type epitaxial layer formed on a first conductivity type semiconductor substrate having a second conductivity type buried layer with a high concentration has an impurity concentration of the epitaxial layer. selectively forming a second conductivity type collector layer having an impurity concentration comparable to that of the collector layer; forming a @14 conductivity type base layer having an impurity concentration higher than the impurity concentration of the collector layer in the collector layer; selectively forming a first conductive type emitter layer on the base layer in a self-aligned manner.
矢に、本発明の実施例について図面を参照して説明する
。第１図に示すように、へ１型埋込層２を有ｆるＰ型シ
リコン基板１のＮ型エピタキシャル層の表面に厚さ０．
６μｍのフィールド酸化層を形成し、その後前記エピタ
キシャル層の表面から内部に向けて選択的に深さ２μｍ
で不純物濃度が１０ ｃＩＩＬ のＰ型コレクタ層を
形成する。Embodiments of the present invention will now be described with reference to the drawings. As shown in FIG. 1, the surface of an N-type epitaxial layer of a P-type silicon substrate 1 having a F1-type buried layer 2 has a thickness of 0.
Form a field oxide layer of 6 μm, then selectively inward from the surface of the epitaxial layer to a depth of 2 μm.
A P-type collector layer with an impurity concentration of 10 cIIL is formed.
次に、第２図に示すように、酸化膜よりなる絶縁膜」０
を形成し、選択的にエツチングし、表面から内部に向け
て、深さ２．５μｍで不純物濃度が１０７ｍ のへ型
ベース層を形成し、微小酸素を含む窒素雰囲気中またに
酸素雰囲気にひきつづき窒素雰囲気中で０．１μｍの酸
化膜１１を形成する。Next, as shown in FIG.
A hemi-shaped base layer with an impurity concentration of 107 m is formed from the surface to the inside with a depth of 2.5 μm. An oxide film 11 of 0.1 μm is formed in an atmosphere.
次に、第３図に示すよりに、フォトレジストを用いず、
全面にわたり酸化膜を０．１μｍエツチングしたのち、
表面から内部に向けて深さ２μｍで不純物濃度が１０２
０ロー２６エミツタ層を形成する。Next, as shown in FIG. 3, without using photoresist,
After etching the oxide film by 0.1 μm over the entire surface,
The impurity concentration is 102 at a depth of 2 μm from the surface to the inside.
0 row 26 emitter layer is formed.
第５図に、実施例の不純物プロファイルを半対数目盛で
表わした特性図である。FIG. 5 is a characteristic diagram showing the impurity profile of the example on a semi-logarithmic scale.
へ型ベース層６．エミッタ層であるｖ遅ｌ拡散層７が同
一の開口部よりネ細物を拡散することにょ）自己整合的
に設けられていること、コレクタがＮ型ベース層６より
低濃度のｆ型コレクタ層５から構成されていて、ペース
・コレクタ間ヲ逆バイアスしたときの空乏層はコレクタ
側に十分のみびことから、ベース幅を小さくすることが
でき、ベース幅のコントロールも容易である。従って電
流増＠率及び遮断周波数を大きくできる。以上ＰＮＰト
ランジスタを例に説明したが、導電型を逆にすればその
１まＮＰＮトランジスタにあてにまることはいうまでも
ない。Hem-shaped base layer 6. The v-slow l diffusion layer 7, which is an emitter layer, is provided in a self-aligned manner (by diffusing thin particles from the same opening), and the collector is an f-type collector layer with a lower concentration than the N-type base layer 6. When reverse bias is applied between the pace and the collector, the depletion layer is sufficiently extended toward the collector side, so the base width can be made small and the base width can be easily controlled. Therefore, the current increase rate and cutoff frequency can be increased. Although the above description has been made using a PNP transistor as an example, it goes without saying that the above description also applies to an NPN transistor if the conductivity type is reversed.
以上説明したように本発明に、低濃度のコレクタ層ｔ−
選択的に形成したのち、ペースの不純物導入後、微小酸
素を含む°窒素雰囲気またに、酸素雰囲気にひきつづき
窒素雰囲気でベース層を形成したのち、酸化膜厚差を利
用してエミッタ領域を開口し、エミッタの不純物を導入
することにょ夛、ペースおよびエミッタは自己整合とな
るのでベース幅を小さくでき、高電流増幅率及び高遮断
周数数をもつ横型トランジスタを容易に作ることができ
る。As explained above, the present invention has a low concentration collector layer t-
After selectively forming the base layer, a base layer is formed in a nitrogen atmosphere containing minute amounts of oxygen, or in an oxygen atmosphere followed by a nitrogen atmosphere, after introducing a pace of impurities, and then an emitter region is opened using the difference in oxide film thickness. By introducing impurities into the emitter, the paste and emitter become self-aligned, so the base width can be reduced, and a lateral transistor with a high current amplification factor and a high cut-off frequency can be easily manufactured.
第１図から第４図に本発明の一実施例を工程順に示す断
面図、第５図に第４図の工程での濃度プロファイルを示
す特性図、第６図に従来例の断面図、第７図に従来例の
濃度プロファイルを示す特性図である。
１・・・Ｐ型基板、２・・・マ畑埋込層、３・・・へ型
エピタキシャル層、４・・・ｖｌ拡散層、５・・・ｆ型
コレクタ層、６・・・Ｎ型ペース層、７・・・ｒ撤エミ
ッタ層、８・・・２撤拡散層、９・・・マ型拡散層、１
０．１１・・・酸化膜、１２・・・Ｉ撤コレクタ層
、′！−・−さ
代理人 弁理士 内 原 晋、４−・。
ゝ、−
第５図FIGS. 1 to 4 are cross-sectional views showing an embodiment of the present invention in the order of steps, FIG. 5 is a characteristic diagram showing the concentration profile in the process of FIG. 4, and FIG. FIG. 7 is a characteristic diagram showing a concentration profile of a conventional example. DESCRIPTION OF SYMBOLS 1...P-type substrate, 2...Mabata buried layer, 3...H-type epitaxial layer, 4...VL diffusion layer, 5...F-type collector layer, 6...N-type space layer, 7... r emitter layer, 8... 2 removed diffusion layer, 9... ma-shaped diffusion layer, 1
0.11...Oxide film, 12...I removed collector layer,'! −・−Sa’s agent, patent attorney Susumu Uchihara, 4−・.ゝ、- Figure 5
Claims (1)
対導電型の不純物を導入しコレクタを形成する工程と、
第二の開口部より一導電型の不純物を導入しベースを形
成する工程と、前記第二の開口部より反対導電型の不純
物を導入しエミッタを形成する工程とを含むことを特徴
とする半導体装置の製造方法。a step of introducing an impurity of an opposite conductivity type through a first opening of an insulating film on a semiconductor substrate of one conductivity type to form a collector;
A semiconductor characterized by comprising the steps of introducing an impurity of one conductivity type through a second opening to form a base, and forming an emitter by introducing an impurity of an opposite conductivity type through the second opening. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1758787A JPS63185063A (en) | 1987-01-27 | 1987-01-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1758787A JPS63185063A (en) | 1987-01-27 | 1987-01-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63185063A true JPS63185063A (en) | 1988-07-30 |
Family
ID=11948033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1758787A Pending JPS63185063A (en) | 1987-01-27 | 1987-01-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63185063A (en) |
-
1987
- 1987-01-27 JP JP1758787A patent/JPS63185063A/en active Pending
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