JPS63181355A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63181355A JPS63181355A JP1359187A JP1359187A JPS63181355A JP S63181355 A JPS63181355 A JP S63181355A JP 1359187 A JP1359187 A JP 1359187A JP 1359187 A JP1359187 A JP 1359187A JP S63181355 A JPS63181355 A JP S63181355A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- pellet
- aluminum metal
- area
- dummy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 239000008188 pellet Substances 0.000 claims abstract description 24
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 20
- 238000000034 method Methods 0.000 abstract description 12
- 238000001020 plasma etching Methods 0.000 abstract description 5
- 238000000059 patterning Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 13
- 150000004767 nitrides Chemical class 0.000 description 5
- 238000000992 sputter etching Methods 0.000 description 3
- -1 aluminum-silicon-copper Chemical compound 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 125000004433 nitrogen atom Chemical group N* 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 241000270708 Testudinidae Species 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にアルミ金属配線をリア
クティブイオンエツチング法にて形成する場合のアルミ
金属配線のサイドエッチを防ぐためのパターン構成に関
するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a pattern structure for preventing side etching of aluminum metal wiring when forming the aluminum metal wiring by a reactive ion etching method. It is something.
従来、アルミ金属配線を形成する場合、第２図に示す様
にマスクｊ−１４をマスクにしてアルミニウム層１３を
エツチング液１５による等方性でウェットエツチングす
る方法が用いられてき九。今日、半導体の集積度向上に
より、微細化が進み、第３図に示す様に異方性のりアク
ティブイオンエツチング法が用いられる様になう念。こ
のリアクティブイオンエツチング法は、アルミニウム金
属２３の上層に形成されたレジスト２４から放出され亀
物質とプラズマ２５の反応による生成物２６がアルミ金
属配線側壁に付着し、サイドエッチを抑制し、異方性の
エツチングを保持している。これらのエツチング法は、
配線に必要な部分のアルミ金属のみを残し、他はすべて
エツチングによシ取シ除いてい念。Conventionally, when forming aluminum metal wiring, a method has been used in which the aluminum layer 13 is isotropically wet-etched using an etching solution 15 using a mask J-14 as shown in FIG. Today, with the improvement in the degree of integration of semiconductors, miniaturization is progressing, and as shown in Figure 3, anisotropic adhesive active ion etching is now being used. In this reactive ion etching method, a product 26 emitted from the resist 24 formed on the upper layer of the aluminum metal 23 and resulting from the reaction between the tortoise material and the plasma 25 adheres to the side wall of the aluminum metal wiring, suppressing side etching, and anisotropic etching. Holds sexual etching. These etching methods are
Be sure to leave only the aluminum metal needed for the wiring and remove everything else by etching.
上述した従来のりアクティブイオンエツチング法は、異
方性のエツチング法であるが、アルミ金属配線の下層が
窒化膜で形成されている場合、アルミ金属のエツチング
が進み、下層が表われて米た時に、この窒化膜から放出
され７′２．Ｎ原子と、アルミ金属配線側壁に形成され
た生成物とが反応し、この生成物が取り除かれる。これ
は、Ｎ原子が多ければ、その反応の進行が早くなる。The conventional glue active ion etching method described above is an anisotropic etching method, but if the lower layer of the aluminum metal wiring is formed of a nitride film, the etching of the aluminum metal progresses and the lower layer is exposed and etched. , released from this nitride film, 7'2. The N atoms react with the products formed on the side walls of the aluminum metal wiring, and the products are removed. This is because the more N atoms there are, the faster the reaction will proceed.
この生成物が取シ除かれると、エツチングは異方性を保
持出来なくなシ、サイドエッチが進行するという欠点が
ある。When this product is removed, the etching cannot maintain anisotropy and side etching progresses.
本発明は、アルミ金属下層の窒化膜の露出量を小さく取
るべく配線としての役割シを持たないダミー配線をペレ
ット内に有している。In the present invention, in order to reduce the amount of exposure of the nitride film underlying the aluminum metal, the pellet includes dummy wiring that does not serve as a wiring.
次に本発唱について図面を参照して説明する。 Next, the main utterance will be explained with reference to the drawings.
第１図は本発明の一実施例の図である。FIG. 1 is a diagram of one embodiment of the present invention.
１はペレットであシ、ペレット上にパターニングされた
アルミ金属配線２のペレット内総面積がペレット面積の
５０％を割る場合、配線としての役割りを持念ないダミ
ー配線３をペレット上に配置し、内部配線２とダミー配
線３の面積を加え、ペレット面積の５０チ以上となる様
に、ダミー配？ｔＭ３の面積を調整し、ペレット内に配
置するものである。1 is a pellet, and if the total area within the pellet of the aluminum metal wiring 2 patterned on the pellet is less than 50% of the pellet area, a dummy wiring 3 that does not play a role as a wiring is placed on the pellet. , the dummy wiring is arranged so that the area of the internal wiring 2 and the dummy wiring 3 is added, and the pellet area becomes 50 inches or more. The area of tM3 is adjusted and placed within the pellet.
以上説明したように本発明は、ペレット内にペレット内
素子間の配線としての役割を持たないダミー配線を配置
することによシアルミ金属配線をリアクティブイオンエ
ツチング法にて形成する過程において、アルミ金属配線
に発生するサイドエッチを防ぐ事が出来る。As explained above, the present invention provides a process for forming sialumium metal wiring by reactive ion etching by arranging dummy wiring within the pellet that does not serve as wiring between elements within the pellet. It is possible to prevent side etching that occurs in wiring.
尚、本発明は純アルミ金属だけでなく、アルミ−シリコ
ン、アルミ−シリコン−銅等のアルミ合金についても適
用できる。The present invention is applicable not only to pure aluminum metal but also to aluminum alloys such as aluminum-silicon and aluminum-silicon-copper.
第１図は本発明の一実施例を示す平面図である。
１・・・・・・ペレット、２・・・・・・アルミ金属配
線、３・・・・・・ダミー配線、
第２図は従来のウェットエツチング法による形成断面図
である。
１１・・・・・・ウェーハ、窒化膜、１３・・・・・・
アルミ金層、１４・・・・・・レジスト、１５・・・・
・・エツチング液、第３図はりアクティブイオンエツチ
ング法による形成断面図である。
２１・・・・・・ウェーハ、２２・・・・・・窒化膜、
２３・・・・・・アルミ金属、２４・・・・・・レジス
ト、２５・・・・・・イオン２６・・・・・・生成物。
（、・
第１図
第２図
第３図FIG. 1 is a plan view showing one embodiment of the present invention. 1... Pellet, 2... Aluminum metal wiring, 3... Dummy wiring, FIG. 2 is a sectional view of formation by a conventional wet etching method. 11...Wafer, nitride film, 13...
Aluminum gold layer, 14...Resist, 15...
... Etching solution, Figure 3 is a cross-sectional view of formation by active ion etching method. 21... Wafer, 22... Nitride film,
23...Aluminum metal, 24...Resist, 25...Ion 26...Product. (,・ Figure 1 Figure 2 Figure 3
Claims (1)
線と同一層上に、配線としての役割りを持たないダミー
配線を、前記内部配線と前記ダミー配線の面積の和がペ
レット面積の５０％以上になる様に、ペレット内に配置
することを特徴とする半導体装置。A dummy wiring that does not have a role as a wiring is placed on the same layer as an internal wiring that serves as a wiring between elements within the pellet, and the sum of the areas of the internal wiring and the dummy wiring is 50% or more of the pellet area. A semiconductor device characterized in that it is arranged in a pellet so that
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1359187A JPS63181355A (en) | 1987-01-22 | 1987-01-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1359187A JPS63181355A (en) | 1987-01-22 | 1987-01-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63181355A true JPS63181355A (en) | 1988-07-26 |
Family
ID=11837438
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1359187A Pending JPS63181355A (en) | 1987-01-22 | 1987-01-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63181355A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0443811A2 (en) * | 1990-02-19 | 1991-08-28 | Nec Corporation | Semiconductor memory device |
| JPH06168946A (en) * | 1991-09-19 | 1994-06-14 | Samsung Electron Co Ltd | Semiconductor device provided with metal interconnection |
| EP0647966A1 (en) * | 1993-10-06 | 1995-04-12 | Kabushiki Kaisha Toshiba | Semiconductor device with wiring pattern and method for manufacturing same |
-
1987
- 1987-01-22 JP JP1359187A patent/JPS63181355A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0443811A2 (en) * | 1990-02-19 | 1991-08-28 | Nec Corporation | Semiconductor memory device |
| JPH06168946A (en) * | 1991-09-19 | 1994-06-14 | Samsung Electron Co Ltd | Semiconductor device provided with metal interconnection |
| EP0647966A1 (en) * | 1993-10-06 | 1995-04-12 | Kabushiki Kaisha Toshiba | Semiconductor device with wiring pattern and method for manufacturing same |
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