JPS63175583A - Plural input picture edition recording system - Google Patents

Plural input picture edition recording system

Info

Publication number
JPS63175583A
JPS63175583A JP782087A JP782087A JPS63175583A JP S63175583 A JPS63175583 A JP S63175583A JP 782087 A JP782087 A JP 782087A JP 782087 A JP782087 A JP 782087A JP S63175583 A JPS63175583 A JP S63175583A
Authority
JP
Japan
Prior art keywords
picture
image
information
events
plural
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP782087A
Other languages
Japanese (ja)
Inventor
Yoshitaka Kaneko
金子 義孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP782087A priority Critical patent/JPS63175583A/en
Publication of JPS63175583A publication Critical patent/JPS63175583A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/222Studio circuitry; Studio devices; Studio equipment
    • H04N5/262Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/2624Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects for obtaining an image which is composed of whole input images, e.g. splitscreen

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Studio Circuits (AREA)
  • Closed-Circuit Television Systems (AREA)

Abstract

PURPOSE:To store simultaneous events into a single recording medium as events occurred in parallel by combining plural picture memories in parallel so as to select an optional picture among plural input pictures and storing the result in one picture. CONSTITUTION:The 1st-n-th picture edit means 21, 22,...2n and a picture memory read address conversion means 5 reading the stored information in the picture memory 3 of n-set of picture edit means, reducing and arranging the information into the size of 1/n of one picture are provided. The 1st-n-th picture edit means 21, 22,...2n are provided respectively with the 1st-n-th picture information luminance/chrominance separation circuits 212, 222,...2n2, interpolation circuits 213, 223,...2n3, 214, 224,...2n4 and picture memories 215, 225,...2n5 storing the output information of the interpolation circuits. Thus, m-set of optional simultaneous events are displayed on one screen of a CRT 8 with reduction. That is, plural events progressed simultaneously are monitored.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は複数入力画像編集記録方式に関し、特に複数事
象の同時監視記録を行う複数入力画像編集記録方式に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiple input image editing and recording method, and more particularly to a multiple input image editing and recording method for simultaneously monitoring and recording a plurality of events.

〔従来の技術〕[Conventional technology]

従来、複数の監視入力画像を、後々、固定化した記録と
して時系列的に記録する場合には、それぞれの入力毎に
監視装置および収録装置を用意して各素材の監視記録を
していた。
Conventionally, when recording a plurality of monitoring input images in chronological order as a fixed record later on, a monitoring device and a recording device were prepared for each input to monitor and record each material.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の複数入力画像情報記録方式では、画像情
報の数だけ記録装置が必要となり、画像情報入力装置(
カメラ)、モニタ装置(CRTディスプレイ)、記録装
置(VTR)等の機器間の接続が複雑になり、機器収容
スペースも多く必要となる欠点があった。また、収録さ
れた複数の画像情報を再生してそれらを時間的に関連づ
けて詳細に見たい場合でも各再生機器間のタイミング調
整が容易でないという欠点があった。
In the conventional multiple input image information recording method described above, recording devices are required for the number of image information, and image information input devices (
This has the disadvantage that connections between devices such as a camera), a monitor device (CRT display), and a recording device (VTR) are complicated, and a large amount of space is required to accommodate the devices. Furthermore, even when it is desired to reproduce a plurality of pieces of recorded image information and view them temporally in detail, there is a drawback in that it is not easy to adjust the timing between each reproduction device.

本発明の目的は、複数の画像情報を等分縮小して一画面
にして出力することにより事象監視装置。
An object of the present invention is to provide an event monitoring device that reduces a plurality of image information into equal parts and outputs them on one screen.

記録装置の数量を減らし、且つ複数事象の同時記録を可
能にする複数入力画像編集記録方式を提供することにあ
る。
It is an object of the present invention to provide a multiple input image editing and recording method that reduces the number of recording devices and enables simultaneous recording of multiple events.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の複数入力画像編集記録方式は、第1〜第nの画
像編集手段と、これらn組の画像編集手段の画像メモリ
の蓄積情報を読み出して一画面の1、/nの大きさに縮
小配置して出力する画像メモリ読出しアドレス変換手段
とを備え、前記第1〜第nの画像編集手段はそれぞれ対
応して入力された第1〜第nの画像情報の輝度・クロマ
分離回路と、内挿回路と、この内挿回路の出力情報を蓄
積する前記画像メモリとを備えることを特徴とする。
The multiple input image editing and recording method of the present invention reads the accumulated information of the image memory of the first to nth image editing means and these n sets of image editing means and reduces the size to 1/n of one screen. image memory read address conversion means for arranging and outputting image memory; It is characterized by comprising an interpolation circuit and the image memory that stores output information of the interpolation circuit.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の複数入力画像編集記録方式の一実施例
を示すブロック図である。
FIG. 1 is a block diagram showing an embodiment of the multiple input image editing and recording method of the present invention.

同図に示すように、本実施例はn個の画像入力端子11
.12.〜1nにそれぞれ接続される画像編集装置21
,22.〜2nと、これら画像編集装置21.22’、
〜2nに蓄積されている画像情報をマイクロプロセッサ
(以下μP)6の制御によって読み出してその画サイズ
を縮小するとともにアドレス変換を行うメモリ続出制御
回路(以下RDC)5と、RDC5の指示により画像編
集装置21,22.〜2nから読み出された画像データ
を記憶する出力画像メモリ(以下MEM)3と、MEM
3の出力デ゛イジタルデータをアナログ変換するD/A
変換回路(以下D/A)4と、D/A4の出力を表示す
る画像モニタ用のディスプレイ装置(以下CRT)8と
、画像編集装置21゜22、〜2n、MEM3.RDC
5のシーケンス制御を行うμP6に所要の指示を入力す
る制御パネル(以下PNL)7を含んで構成される。
As shown in the figure, this embodiment has n image input terminals 11.
.. 12. Image editing devices 21 respectively connected to ~1n
, 22. ~2n, and these image editing devices 21.22',
A memory continuous control circuit (hereinafter referred to as RDC) 5 reads the image information stored in ~2n under the control of a microprocessor (hereinafter referred to as μP) 6, reduces the image size, and performs address conversion, and image editing according to instructions from the RDC 5. Devices 21, 22. An output image memory (hereinafter referred to as MEM) 3 that stores image data read out from ~2n;
D/A that converts the output digital data of 3 into analog
A conversion circuit (hereinafter referred to as D/A) 4, a display device (hereinafter referred to as CRT) 8 for displaying the output of the D/A 4, an image editing device 21, 22, to 2n, MEM3. RDC
The device includes a control panel (hereinafter referred to as PNL) 7 for inputting necessary instructions to μP 6 which performs sequence control of step 5.

例えば画像編集装置21は画像入力端子11からの画像
情報(アナログデータ)をディジタル変換するA/D変
換回路(以下A/D)21.1と、輝度・クロマ分離回
路(以下YCF)21.2と、垂直内挿回路(以下VI
S)21Bと、水平内挿回路(以下HIS)214と、
HI S 214の出力情報を蓄積する入力画像メモリ
(以下M)215とからなり、VIS21B、HIS2
]、4.μP15はμP6の指示に従って動作する。な
お他の画像編集装置22.〜2nもこれと同様の構成を
有する。
For example, the image editing device 21 includes an A/D conversion circuit (hereinafter referred to as A/D) 21.1 that digitally converts image information (analog data) from the image input terminal 11, and a luminance/chroma separation circuit (hereinafter referred to as YCF) 21.2. and vertical interpolation circuit (hereinafter VI
S) 21B, a horizontal interpolation circuit (hereinafter referred to as HIS) 214,
It consists of an input image memory (hereinafter referred to as M) 215 that stores the output information of the HIS 214, and the VIS 21B and the HIS 2
], 4. μP15 operates according to instructions from μP6. Note that other image editing devices 22. ~2n also has a similar configuration.

続いて本実施例の動作について説明する。Next, the operation of this embodiment will be explained.

画像入力端子11,12.〜]nから同時に入力された
画像情報は、それぞれ画像編集装置21゜22、〜2n
においてA/D21 L 221.〜2n 1、YCF
212,222.〜2n2、VIS213.223.〜
2n3、HIS214,224、〜2n4を通してμP
15,225.〜2n5に蓄積される。PNL7からの
指示に基づいてμP6がRDC5に制御信号を送ると、
RDC5はμP15,225.〜2n5のm個(m≦n
)を選択アクセスしてその内容を読み出し、この読み出
した各画像情報を1画面サイズの1 / mの大きさに
縮小した各縮小サイズ画像データの1画面上のアドレス
指定を行ってMEM3に書き込む。
Image input terminals 11, 12. ~] The image information input simultaneously from n is input to the image editing devices 21, 22, and ~2n, respectively.
In A/D21 L 221. ~2n 1, YCF
212, 222. ~2n2, VIS213.223. ~
μP through 2n3, HIS214, 224, ~2n4
15,225. ~2n5 is accumulated. When μP6 sends a control signal to RDC5 based on instructions from PNL7,
RDC5 is μP15,225. m pieces of ~2n5 (m≦n
) is selectively accessed to read its contents, each of the read image information is reduced to 1/m of one screen size, and each reduced size image data is addressed on one screen and written into MEM3.

MEM3に書き込まれた画像データはD/A4により映
像信号(アナログ信号)にされて画像出力端子つとCR
T8に出力される。
The image data written to MEM3 is converted into a video signal (analog signal) by D/A4 and sent to the image output terminal and CR.
It is output to T8.

従って、CRT8にはm個の同時事象が1つの画面に縮
小配置されて表示される。つ吐り同時進行した複数事象
をモニタすることができる。
Therefore, on the CRT 8, m simultaneous events are displayed in a reduced size arrangement on one screen. It is possible to monitor multiple events occurring simultaneously.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、複数の画像メモリを並列
的に組み合わせることにより、複数入力画像のうち任意
の画像を選択してその組み合わせ画像の数に応じて複数
入力画像を等分して縮小して一画面内に収容することが
できるので、同時事象を並行した事象として単一の記録
媒体内に収容することが可能となり、記録再現時に同時
進行した複数事象の認識に役立つ効果があり、また、記
録媒体容量の縮小、記録装置の数量の削減の効果がある
。さらに事象の監視に必要なディスプレイ装置および機
器接続ケーブル等の数量を減らす効果がある。
As explained above, the present invention combines multiple image memories in parallel, selects any image from among multiple input images, and divides the multiple input images into equal parts according to the number of combined images and reduces the size of the input images. Since simultaneous events can be stored in one screen, it is possible to store simultaneous events as parallel events in a single recording medium, which has the effect of helping to recognize multiple events that occurred simultaneously when reproducing records. Further, there is an effect of reducing the capacity of the recording medium and the number of recording devices. Furthermore, it has the effect of reducing the number of display devices, device connection cables, etc. required for event monitoring.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の複数入力画像編集記録方式の一実施例
を示すブロック図である。 3・・出力画像メモリ(MEM) 、4・・・D/A変
換回路(D/A)、5・・・メモリ読出制御回路(RD
C)、6・・・マイクロプロセッサ(μP)、7・・・
制御パネル(PNL)、8・・・ディスプレイ装置(C
RT)、9・・画像出力端子、11,12.〜1n・・
・画像入力端子、21,22.〜2n・・・画像編集装
置、211 、221 、〜2 n 1−・A/D変換
回路(A/D) 、212,222.〜2n2・・・輝
度・クロマ分離回路(YCF)、214.224゜〜2
 n 4−垂直内挿回路(VIS)、215.225 
、 ・2 n 5・・・水平内挿回路(HIS)、21
6.226.〜2n6・・入力画像メモリ(M)67一
FIG. 1 is a block diagram showing an embodiment of the multiple input image editing and recording method of the present invention. 3... Output image memory (MEM), 4... D/A conversion circuit (D/A), 5... Memory read control circuit (RD
C), 6... microprocessor (μP), 7...
Control panel (PNL), 8...Display device (C
RT), 9... image output terminal, 11, 12. ~1n...
- Image input terminal, 21, 22. ~2n... Image editing device, 211, 221, ~2n1-A/D conversion circuit (A/D), 212, 222. ~2n2...Luminance/chroma separation circuit (YCF), 214.224°~2
n 4 - Vertical interpolation circuit (VIS), 215.225
, ・2 n 5...Horizontal interpolation circuit (HIS), 21
6.226. ~2n6...Input image memory (M) 67-

Claims (1)

【特許請求の範囲】[Claims] 第1〜第nの画像編集手段と、これらn組の画像編集手
段の画像メモリの蓄積情報を読み出して一画面の1/n
の大きさに縮小配置して出力する画像メモリ読出しアド
レス変換手段とを備え、前記第1〜第nの画像編集手段
はそれぞれ対応して入力された第1〜第nの画像情報の
輝度・クロマ分離回路と、内挿回路と、この内挿回路の
出力情報を蓄積する前記画像メモリとを備えることを特
徴とする複数入力画像編集記録方式。
The first to n-th image editing means and the stored information of the image memory of these n sets of image editing means are read out and 1/n of one screen is read out.
image memory read address converting means for reducing and arranging image information to a size of A multiple-input image editing and recording method comprising a separation circuit, an interpolation circuit, and the image memory that stores output information of the interpolation circuit.
JP782087A 1987-01-14 1987-01-14 Plural input picture edition recording system Pending JPS63175583A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP782087A JPS63175583A (en) 1987-01-14 1987-01-14 Plural input picture edition recording system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP782087A JPS63175583A (en) 1987-01-14 1987-01-14 Plural input picture edition recording system

Publications (1)

Publication Number Publication Date
JPS63175583A true JPS63175583A (en) 1988-07-19

Family

ID=11676228

Family Applications (1)

Application Number Title Priority Date Filing Date
JP782087A Pending JPS63175583A (en) 1987-01-14 1987-01-14 Plural input picture edition recording system

Country Status (1)

Country Link
JP (1) JPS63175583A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2674090A1 (en) * 1991-03-15 1992-09-18 Video Scoper France METHOD FOR SIMULTANEOUSLY GENERATING A SET OF VIDEO IMAGES ON A VIEWING MEDIUM, AND SYSTEMS FOR ITS IMPLEMENTATION.
JPH0673977U (en) * 1991-05-22 1994-10-18 日本電気ホームエレクトロニクス株式会社 Image compression device and image decompression device
US20120212670A1 (en) * 2002-11-15 2012-08-23 Thomson Licensing S.A. Method and apparatus for composition of subtitles
US9462221B2 (en) 2002-11-15 2016-10-04 Thomson Licensing Method and apparatus for composition of subtitles

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2674090A1 (en) * 1991-03-15 1992-09-18 Video Scoper France METHOD FOR SIMULTANEOUSLY GENERATING A SET OF VIDEO IMAGES ON A VIEWING MEDIUM, AND SYSTEMS FOR ITS IMPLEMENTATION.
WO1992017035A1 (en) * 1991-03-15 1992-10-01 V.S.F. Video Scoper France Process for simultaneously generating a series of video images on a display, and systems for implementation thereof
JPH0673977U (en) * 1991-05-22 1994-10-18 日本電気ホームエレクトロニクス株式会社 Image compression device and image decompression device
US20120212670A1 (en) * 2002-11-15 2012-08-23 Thomson Licensing S.A. Method and apparatus for composition of subtitles
US20120219267A1 (en) * 2002-11-15 2012-08-30 Thomson Licensing S.A. Method and apparatus for composition of subtitles
US20120219266A1 (en) * 2002-11-15 2012-08-30 Thomson Licensing S.A. Method and apparatus for composition of subtitles
US8363163B2 (en) * 2002-11-15 2013-01-29 Thomson Licensing Method and apparatus for composition of subtitles
US8373800B2 (en) * 2002-11-15 2013-02-12 Thomson Licensing Method and apparatus for composition of subtitles
US8432493B2 (en) * 2002-11-15 2013-04-30 Thomson Licensing Method and apparatus for composition of subtitles
US8531609B2 (en) * 2002-11-15 2013-09-10 Thomson Licensing Method and apparatus for composition of subtitles
US8537282B2 (en) * 2002-11-15 2013-09-17 Thomson Licensing Method and apparatus for composition of subtitles
US8737810B2 (en) 2002-11-15 2014-05-27 Thomson Licensing Method and apparatus for cropping of subtitle elements
US20160211000A9 (en) * 2002-11-15 2016-07-21 Thomson Licensing Method and apparatus for composition of subtitles
US9462221B2 (en) 2002-11-15 2016-10-04 Thomson Licensing Method and apparatus for composition of subtitles
US9503678B2 (en) 2002-11-15 2016-11-22 Thomson Licensing Method and apparatus for composition of subtitles
US9595293B2 (en) * 2002-11-15 2017-03-14 Thomson Licensing Method and apparatus for composition of subtitles
US9635306B2 (en) 2002-11-15 2017-04-25 Thomson Licensing Method and apparatus for composition of subtitles
US9749576B2 (en) 2002-11-15 2017-08-29 Thomson Licensing Method and apparatus for composition of subtitles

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