JPS63174337A - Formation of solder bump - Google Patents
Formation of solder bumpInfo
- Publication number
- JPS63174337A JPS63174337A JP647287A JP647287A JPS63174337A JP S63174337 A JPS63174337 A JP S63174337A JP 647287 A JP647287 A JP 647287A JP 647287 A JP647287 A JP 647287A JP S63174337 A JPS63174337 A JP S63174337A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- core
- copper foil
- substrate
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 44
- 230000015572 biosynthetic process Effects 0.000 title description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000011889 copper foil Substances 0.000 claims abstract description 13
- 238000007747 plating Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 15
- 238000007789 sealing Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 238000000206 photolithography Methods 0.000 abstract description 4
- 238000003466 welding Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000010949 copper Substances 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
Abstract
Description
【発明の詳細な説明】
〔概要〕
被処理基板上に多数の半田バンプを形成する方法として
、パッド形成位置にあたる個所のレジスト層を窓開けし
た銅箔をメッキして窓開は個所に半田被覆の芯球を多数
形成したる後、レジスト層を溶解除去しておき、芯球を
被処理基板のパッドに位置合わせして加熱融着せしめた
後、銅箔を剥離して半田バンプを形成する方法。[Detailed Description of the Invention] [Summary] As a method for forming a large number of solder bumps on a substrate to be processed, the resist layer at the pad formation position is plated with copper foil with apertures, and the apertures are coated with solder. After forming a large number of core balls, the resist layer is dissolved and removed, the core balls are aligned with the pads of the substrate to be processed, and the core balls are heated and fused, and then the copper foil is peeled off to form solder bumps. Method.
本発明はＩＣ基板やチップ面などへの半田バンプの形成
方法に関する。The present invention relates to a method for forming solder bumps on an IC substrate, chip surface, etc.
大量の情報を高速に処理する必要性から情報処理装置の
進歩は著しく、使用部品の小形化と配線パターンの微細
化により、高密度実装が行われている。BACKGROUND OF THE INVENTION Due to the need to process large amounts of information at high speeds, information processing devices have made remarkable progress, and high-density packaging is being achieved through miniaturization of components and miniaturization of wiring patterns.
例えば、情報処理装置の主体を占める半導体装置は単位
素子の小形化によりＩＣやＬＳＩより一段と大容量化し
たＶＬＳ Ｉが実用化されているが、このように構成素
子数が増すに比例して端子数が増加しており、従来のよ
うに印刷配線しであるセラミック基板の中央凹部に半導
体チップを搭載し、この基板の側面に多数のリード端子
を備える今までのパッケージ構造では外部への回路接続
が困難になっている。For example, VLSI semiconductor devices, which are the main component of information processing equipment, have been put into practical use due to the miniaturization of unit elements and have a much larger capacity than ICs and LSIs, but as the number of components increases, the terminal capacity increases. The number of circuits is increasing, and the conventional package structure, in which a semiconductor chip is mounted in the central recess of a ceramic substrate with printed wiring, and many lead terminals on the side of this substrate, makes it difficult to connect the circuit to the outside. is becoming difficult.
そこで、半導体チップへのパフシベーション技術の進歩
と相いまって、半導体チップ面上にマトリックス状に多
数の半田バンプを設け、この半導体チップを多層配線基
板上に設けられている多数のパッドと位置合わせして加
熱溶着する装着方法が採られている。Therefore, along with advances in puffivation technology for semiconductor chips, a large number of solder bumps are provided in a matrix on the surface of a semiconductor chip, and this semiconductor chip is connected to a large number of pads provided on a multilayer wiring board. The installation method is to align and heat weld.
また、薄膜ＩＣ，厚膜ＩＣなどのハイブリッドＩＣにお
いても、同様にパターン形成されている基板上に多数の
半田バンプを設け、これを配線パターンが形成されてい
る別の基板のパッドに位置合わせして熔着する装着方法
が採られている。In addition, in hybrid ICs such as thin film ICs and thick film ICs, a large number of solder bumps are similarly provided on a patterned substrate, and these are aligned with pads on another substrate on which a wiring pattern is formed. The mounting method is to weld the parts together.
厚膜或いは薄膜ハイブリッドＩＣや半導体ＩＣなとの基
板上に半田バンプを形成するには次のような方法がとら
れている。The following method is used to form solder bumps on a substrate such as a thick film or thin film hybrid IC or semiconductor IC.
■ スクリーン印刷法により半田ペーストを厚めに印刷
した後に加熱溶融して形成する。■ Formed by printing a thick layer of solder paste using the screen printing method and then heating and melting it.
■ バンプを形成する被処理基板の上にバンプ形成部を
穴開けしたマスクを位置合わせし、このマスク穴に半田
ボールを充填し、加熱溶融させて形成する。(2) A mask with holes for bump formation is aligned on the substrate to be processed on which bumps are to be formed, solder balls are filled into the mask holes, and are heated and melted.
ここで、バンプの大きさは１００μｍ角〜３００μｍ角
と小さく、相互の間隔が接近しており、溶着後において
も高い位置精度を必要とすることから多くの場合、■の
方法が使用されている。Here, the size of the bumps is small, 100 μm square to 300 μm square, and the distance between them is close, and high positional accuracy is required even after welding, so method (2) is often used. .
ここで、形成するハンプの数が少ない場合はバンプの形
成を行うパッド上に半田ボールを正確に位置決めするこ
とが可能であるが、大部分の場合はバンプの数は膨大で
あり、そのため被処理基板と一体化したマスクを篩をか
けるように揺動して半田ボールを穴開は部に充填してい
るが、マスク穴の総てに詰らなかったり、一つの穴に二
個入ったりして半田バンプの製造歩留まりが低く、この
改良が必要であった。Here, if the number of humps to be formed is small, it is possible to accurately position the solder ball on the pad where the bumps are to be formed, but in most cases the number of bumps to be processed is enormous, and therefore the number of bumps to be processed is The mask, which is integrated with the board, is swung like a sieve to fill the holes with solder balls, but sometimes not all of the holes in the mask are clogged, or two balls get into one hole. However, the manufacturing yield of solder bumps was low, and this improvement was necessary.
以上記したように印刷配線基板へのハイブリッドＩＣ基
板の装着や半導体チップの装着を半田バンプを用いて行
う方法において、従来のようにマスク穴に半田ボールを
充填して加熱融着させる方法では製造歩留まりが低いこ
とが問題である。As mentioned above, in the method of mounting a hybrid IC board or semiconductor chip on a printed wiring board using solder bumps, the conventional method of filling solder balls into mask holes and heating and fusing them is not suitable for manufacturing. The problem is that the yield is low.
上記の問題は被処理基板のパッド形成位置にあたる個所
のレジスト層を窓開けした銅箔をメッキして該窓開は個
所に半田被覆の芯球を多数形成したる後、該レジスト層
を溶解除去しておき、該芯球を被処理基板のパッドに位
置合わせして加熱融着せしめた後、前記銅箔を剥離して
使用する半田ハンプの形成方法により解決することがで
きる。The above problem is solved by plating a copper foil with a window in the resist layer at the location where the pad is to be formed on the substrate, forming a large number of solder-coated core balls at the location of the window, and then dissolving and removing the resist layer. This problem can be solved by a method of forming a solder hump in which the core ball is aligned with the pad of the substrate to be processed and heat-fused, and then the copper foil is peeled off.
本発明はマスク穴に半田ボールを充填した後に加熱して
パッド上に融着させる従来法の製造歩留りの低い理由は
半田ボールが多数のマスク穴に確実に充填されないこと
が原因であることから、確実に位置決めする方法として
銅箔を用い、写真蝕刻技術（フォトリソグラフィ）を用
いて銅箔を芯とする半田被覆した多数の芯球を形成し、
この芯球を位置決めして加熱融着することにより、パッ
ドと半田ボールが確実に対応して過不足のない半田バン
プを形成するものである。The present invention solves the problem that the manufacturing yield of the conventional method of filling the mask holes with solder balls and then heating them to fuse them onto the pad is low because the solder balls are not reliably filled into a large number of mask holes. Copper foil is used as a method for reliable positioning, and photolithography is used to form a large number of solder-coated core balls with copper foil as the core.
By positioning this core ball and heat-sealing it, the pad and the solder ball reliably correspond to form a solder bump with no excess or deficiency.
第１図は本発明に係る半田バンプシートの断面図、また
第２図は被処理基板上に予め設けであるパッドに熔着し
て形成した半田バンプの断面図である。FIG. 1 is a sectional view of a solder bump sheet according to the present invention, and FIG. 2 is a sectional view of solder bumps formed by welding to pads provided in advance on a substrate to be processed.
すなわち、第１図において銅箔（Ｃｕ箔）１の上に写真
蝕刻技術を用いて多数のバンプ形成位置にメッキ法によ
り銅芯（Ｃｕ芯）２、拡散防止層３、半田液Ｎ４と層形
成して対称夫子ネジ形の芯球７を備えた半田バンプシー
トを作った後、第２図に示すように被処理基板５に予め
設けであるパッド６に位置合わせし、被処理基板５を加
熱して半田被覆４を融解させて芯球７を熔着させる。That is, in FIG. 1, a copper core (Cu core) 2, a diffusion prevention layer 3, and a solder liquid N4 are formed by plating on a copper foil (Cu foil) 1 at a large number of bump formation positions using photolithography. After making a solder bump sheet with a symmetrical screw-shaped core ball 7, as shown in FIG. Then, the solder coating 4 is melted and the core ball 7 is welded.
次に、相互のバンプを連結しているＣｕ箔１を引き千切
ることにより、それぞれ独立した半田バンプを得るもの
である。Next, by tearing off the Cu foil 1 that connects the bumps, independent solder bumps are obtained.
第３図（Ａ）〜（Ｅ’）は本発明に係る半田パンプシー
トの製法を示す実施例の断面図であって、厚さが２５μ
ｍのＣｕ箔１の上にスピンコード法を用いて表裏面に５
０μｍの厚さにレジスト膜８を形成した（以上同図Ａ）
。FIGS. 3(A) to 3(E') are cross-sectional views of an example showing a method for manufacturing a solder pump sheet according to the present invention, and the thickness is 25 μm.
5 m on the front and back surfaces using the spin code method on the Cu foil 1.
A resist film 8 was formed to a thickness of 0 μm (see A in the same figure).
.
次に、写真蝕刻技術を用いてバンプ形成位置９を窓開け
し、Ｃｕ箔ｌを露出させる（以上同図Ｂ）。Next, a window is opened at the bump formation position 9 using photolithography to expose the Cu foil 1 (see FIG. 1B).
次に、Ｃｕメッキを行ってＣｕ芯２を形成する（以上同
図Ｃ）。Next, Cu plating is performed to form a Cu core 2 (C in the same figure).
次に、この上にＮｉメッキを行って厚さが約３μｍのＮ
１ＪｉｌＯを形成した。Next, Ni plating was performed on this to give a thickness of approximately 3 μm.
1JilO was formed.
このＮｉ層１０は拡散防止層であってＣｕと半田との拡
散を阻止する（以上同図Ｄ）。This Ni layer 10 is a diffusion prevention layer and prevents the diffusion of Cu and solder (see D in the same figure).
次に、この上に３０μｍの厚さに半田メッキを行って半
田被覆４を行った（以上同図Ｅ）。Next, solder plating was performed on this to a thickness of 30 μm to form a solder coating 4 (see E in the same figure).
、次に溶剤に浸漬してレジスト層８を溶解除去すること
により第１図に示すような半田バンプシートができあが
る。Then, the resist layer 8 is dissolved and removed by immersion in a solvent, thereby completing a solder bump sheet as shown in FIG.
以上記したように本発明の実施により被処理基板上に予
め形成しであるバンドと半田被覆が行われている芯球と
の対応が完全に行われるので製造歩留りと位置精度の向
上が可能となる。As described above, by carrying out the present invention, the band pre-formed on the substrate to be processed and the core ball coated with solder are perfectly matched, making it possible to improve manufacturing yield and positional accuracy. Become.
第１図は本発明に係る半田バンブシートの断面図、
第２図はパッドに溶着した半田バンプの断面図、第３図
（Ａ）〜（Ｅ）は半田バンブシートの製造工程を説明す
る断面図、
である。
図において、
１はＣｕ箔、 ２はＣｕ芯、３は拡散防止
層、 ４は半田被覆、５は被処理基板、 ６
はパッド、８はレジスト層、 ９はバンプ形成位
置、ｌＯはＮｉ層、
である。
＄２囚FIG. 1 is a cross-sectional view of a solder bump sheet according to the present invention, FIG. 2 is a cross-sectional view of a solder bump welded to a pad, and FIGS. 3 (A) to (E) are cross-sectional views explaining the manufacturing process of the solder bump sheet. It is. In the figure, 1 is a Cu foil, 2 is a Cu core, 3 is a diffusion prevention layer, 4 is a solder coating, 5 is a substrate to be processed, 6
is a pad, 8 is a resist layer, 9 is a bump formation position, and IO is a Ni layer. $2 prisoner
Claims (1)
を窓開けした銅箔をメッキして該窓開け個所に半田被覆
の芯球を多数形成したる後、該レジスト層を溶解除去し
ておき、該芯球を被処理基板のパッドに位置合わせして
加熱融着せしめた後、前記銅箔を剥離して使用すること
を特徴とする半田バンプの形成方法。After plating a copper foil with apertures in the resist layer at the positions where the pads are to be formed on the substrate to be processed and forming a large number of core balls coated with solder at the apertures, the resist layer is dissolved and removed. 1. A method of forming a solder bump, which comprises aligning a core ball with a pad of a substrate to be processed and heat-sealing it, and then peeling off the copper foil.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP647287A JPS63174337A (en) | 1987-01-14 | 1987-01-14 | Formation of solder bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP647287A JPS63174337A (en) | 1987-01-14 | 1987-01-14 | Formation of solder bump |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63174337A true JPS63174337A (en) | 1988-07-18 |
Family
ID=11639399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP647287A Pending JPS63174337A (en) | 1987-01-14 | 1987-01-14 | Formation of solder bump |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63174337A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07193068A (en) * | 1993-12-27 | 1995-07-28 | Nec Corp | Flip chip bump and its manufacture |
| US5466635A (en) * | 1994-06-02 | 1995-11-14 | Lsi Logic Corporation | Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating |
| US5504035A (en) * | 1989-08-28 | 1996-04-02 | Lsi Logic Corporation | Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate |
| US5567648A (en) * | 1994-08-29 | 1996-10-22 | Motorola, Inc. | Process for providing interconnect bumps on a bonding pad by application of a sheet of conductive discs |
| US20130032934A1 (en) * | 2011-08-01 | 2013-02-07 | Tessera Inc. | Packaged microelectronic elements having blind vias for heat dissipation |
-
1987
- 1987-01-14 JP JP647287A patent/JPS63174337A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5504035A (en) * | 1989-08-28 | 1996-04-02 | Lsi Logic Corporation | Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate |
| JPH07193068A (en) * | 1993-12-27 | 1995-07-28 | Nec Corp | Flip chip bump and its manufacture |
| US5466635A (en) * | 1994-06-02 | 1995-11-14 | Lsi Logic Corporation | Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating |
| US5698465A (en) * | 1994-06-02 | 1997-12-16 | Lsi Logic Corporation | Process for manufacturing an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating |
| US5872404A (en) * | 1994-06-02 | 1999-02-16 | Lsi Logic Corporation | Interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating |
| US5567648A (en) * | 1994-08-29 | 1996-10-22 | Motorola, Inc. | Process for providing interconnect bumps on a bonding pad by application of a sheet of conductive discs |
| US20130032934A1 (en) * | 2011-08-01 | 2013-02-07 | Tessera Inc. | Packaged microelectronic elements having blind vias for heat dissipation |
| US8618647B2 (en) * | 2011-08-01 | 2013-12-31 | Tessera, Inc. | Packaged microelectronic elements having blind vias for heat dissipation |
| US9620433B2 (en) | 2011-08-01 | 2017-04-11 | Tessera, Inc. | Packaged microelectronic elements having blind vias for heat dissipation |
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