JPS63169747A - Resin sealed type semiconductor device - Google Patents
Resin sealed type semiconductor deviceInfo
- Publication number
- JPS63169747A JPS63169747A JP227187A JP227187A JPS63169747A JP S63169747 A JPS63169747 A JP S63169747A JP 227187 A JP227187 A JP 227187A JP 227187 A JP227187 A JP 227187A JP S63169747 A JPS63169747 A JP S63169747A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- coating film
- integrated circuit
- semiconductor device
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 title claims abstract description 18
- 229920005989 resin Polymers 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000002131 composite material Substances 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 238000005524 ceramic coating Methods 0.000 claims description 7
- 239000011224 oxide ceramic Substances 0.000 claims description 5
- 229910052574 oxide ceramic Inorganic materials 0.000 claims description 5
- 239000011225 non-oxide ceramic Substances 0.000 claims description 3
- 229910052575 non-oxide ceramic Inorganic materials 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 12
- 239000011248 coating agent Substances 0.000 abstract description 12
- 238000000576 coating method Methods 0.000 abstract description 12
- 239000000919 ceramic Substances 0.000 abstract description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 5
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 4
- 239000010931 gold Substances 0.000 abstract description 4
- 229910052737 gold Inorganic materials 0.000 abstract description 4
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 3
- 239000001257 hydrogen Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 1
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000277269 Oncorhynchus masou Species 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- 229910000476 molybdenum oxide Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- PQQKPALAQIIWST-UHFFFAOYSA-N oxomolybdenum Chemical compound [Mo]=O PQQKPALAQIIWST-UHFFFAOYSA-N 0.000 description 1
- 238000007750 plasma spraying Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、樹脂封止形半導体装置に関し、特に金属部
材（リードフレーム）の表面処理に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a resin-sealed semiconductor device, and particularly to surface treatment of a metal member (lead frame).
ｔ４４図は従来の集積回路フレームを示す平面図であり
、同図軸）は表面を、同図６）は裏面をそれぞれ示して
いる。図において、１は金属部材である集積回路フレー
ム、２はパッケージの外形線、３は集積回路素子、４は
ダイパッド、５はリード、６は集積回路素子３とリード
５とを接続する金線、７は樹脂の流れをせき止めるタイ
バ、８はボンディング・エリアである。Figure t44 is a plan view showing a conventional integrated circuit frame, where the axis) in the figure shows the front side, and the axis 6) in the figure shows the back side. In the figure, 1 is an integrated circuit frame which is a metal member, 2 is an outline of the package, 3 is an integrated circuit element, 4 is a die pad, 5 is a lead, 6 is a gold wire connecting the integrated circuit element 3 and the lead 5, 7 is a tie bar that blocks the flow of resin, and 8 is a bonding area.
従来の技術では、前記集積回路フレームと樹脂との接着
力にばらつきがあり不均一なので、熱ストレスによる応
力が接着力の弱い場所に集中し、クラックが発生するこ
とがある。これが原因となり、界面ひび割れ、金線切れ
が生じたり、クラックから水分が侵入するため耐湿性等
の品質が劣化する等の問題があった。In the conventional technology, since the adhesive strength between the integrated circuit frame and the resin varies and is non-uniform, stress due to thermal stress is concentrated in areas where the adhesive strength is weak, and cracks may occur. This causes problems such as interfacial cracks, breakage of gold wires, and deterioration of moisture resistance and other qualities due to moisture infiltration through the cracks.
この発明は上記の様な問題点を改善するためになされた
もので、フレームと樹脂との界面での接着力を向上させ
て均一にし、信頼度の高いｉｆＮ脂封止形半導体装置を
得ることを目的とする。This invention was made in order to improve the above-mentioned problems, and to obtain a highly reliable ifN resin-sealed semiconductor device by improving and making uniform the adhesive force at the interface between the frame and the resin. With the goal.
この発明に係る樹脂封止形半導体装置は、金属部材の表
面に、ファインセラミックスコーティング膜を設けたも
のである。A resin-sealed semiconductor device according to the present invention has a fine ceramic coating film provided on the surface of a metal member.
ファインセラミックスコーティング膜は、例えばプラズ
マ溶射法、ＣＶＤ法（化学的気相成膜法）。The fine ceramics coating film is formed by, for example, plasma spraying or CVD (chemical vapor deposition).
ＰＶＤＣ物理的気相成膜法）法等の手法にニジ形成され
た単一酸化物系または複合酸化物系セラミックスや、非
酸化物系セラミックス等からなるファインセラミックス
コーティング膜である。エリ具体的には、単一酸化物系
および複合酸化物系セラミックスとしては、アルミナ、
マグネシャ、酸化モリブデン、酸化シリコンとアルミナ
の複合酸化物等があり、非酸化物系セラミックスとして
は、シリコーンナイトライド、シリコーンカーバイト、
チツ化アルミ、ボロンナインライド等がある。It is a fine ceramic coating film made of single oxide or composite oxide ceramics, non-oxide ceramics, etc., formed by a method such as PVDC (physical vapor phase deposition method). Specifically, single oxide ceramics and composite oxide ceramics include alumina,
Examples include magnesia, molybdenum oxide, and composite oxides of silicon oxide and alumina. Non-oxide ceramics include silicone nitride, silicone carbide,
There are aluminum alloys, boron nineride, etc.
この発明による樹脂封止形半導体装置においては、金属
部材の表面に設けられ次ファインセラミックスコーティ
ング模と樹脂との間に水素結合が生じ、両者間の結合力
が増大する。In the resin-sealed semiconductor device according to the present invention, hydrogen bonding occurs between the fine ceramic coating provided on the surface of the metal member and the resin, increasing the bonding force between the two.
濱１図はこの発明の一実施例を示す平面図であり、第４
図と同一符号は同一のも−（７） ｆ示す。Figure Hama 1 is a plan view showing one embodiment of the present invention;
The same reference numerals as in the figure indicate the same numbers.
フレーム１の表面（同図（ａ））と裏面（同図（ｂ））
の全面に、図中斜−で示した工うに、ＣＶＤ法でアルミ
ナコーテイング膜１１を生成したのち、ダイパッド４に
集積回路素子３を接層する。次いで金［６で集積回路素
子３とリード５とを接続し、これらを樹脂封止する。２
がそのときの樹脂パッケージの外形−を示す。The front side ((a) of the same figure) and the back side ((b) of the same figure) of frame 1
After forming an alumina coating film 11 on the entire surface of the die pad 4 as indicated by diagonal lines in the figure, an alumina coating film 11 is formed by the CVD method, and then an integrated circuit element 3 is attached to the die pad 4 . Next, the integrated circuit element 3 and the leads 5 are connected with gold [6], and these are sealed with resin. 2
indicates the outer shape of the resin package at that time.
この結果、生成したアルミナコーテイング膜１１と図示
しない樹脂との間の強固な水素結合の生成等にニジ、フ
レーム１と樹脂との結合力が増大する。As a result, strong hydrogen bonds are formed between the produced alumina coating film 11 and the resin (not shown), and the bonding force between the frame 1 and the resin increases.
第２図はこの発明の他の実施例を示す平面図であり、ア
ルミナコーテイング膜１１Ａ？パツケージ外形ＩＷ２で
囲まれた範囲、すなわち図示しない樹脂で封止される金
属部材の部分のみに限って生成させたものである。FIG. 2 is a plan view showing another embodiment of the present invention, in which an alumina coating film 11A? This is generated only in the area surrounded by the package outer shape IW2, that is, only in the part of the metal member that is sealed with a resin (not shown).
第３図はこの発明の他の実施例を示す平面図である。第
１図、第２図のように表と裏との同じ範囲にアルミナコ
ーテイング膜を生成するのではなく、第２図の実施例に
おいて、表側の金ｍを接続する部分であるボンディング
エリア８とダイパッド４上に集積回路素子３が載る部分
とを除いて、アルミナコーティングＩｆｉ １１ Ｂ
（８）ｋ生成したものである。FIG. 3 is a plan view showing another embodiment of the invention. Instead of forming an alumina coating film in the same area on the front and back sides as shown in FIGS. 1 and 2, in the embodiment shown in FIG. Except for the part where the integrated circuit element 3 is placed on the die pad 4, alumina coating Ifi 11B
(8) k generated.
以上の工に、この発明は金属部材の表面にファインセラ
ミックスコーティング膜を設けて樹脂封止するようにし
たので、金属部材℃樹脂との接着力が増加し、Ｍｙ度が
上昇するという効果がある。In order to overcome the above problems, this invention provides a fine ceramic coating film on the surface of the metal member and seals it with resin, which has the effect of increasing the adhesive force of the metal member with the resin and increasing the degree of My degree. .
第１図はこの発明の一実施例金示す平面図、第２図お工
び第３図はそれぞれこの発明の他の実施例を示す平面図
。第４図は従来の樹脂封止形半導体装置に使用される金
属部材を示す。
１・・・・集積回路フレーム、２會・・φ樹脂パッケー
ジ外形線、３は集積回路素子、１１．ＩＩＡ。
１１Ｂ・・・・アルミナコーテイング膜。
代 理 人 大 岩 増 雌第１図
（０） （ｂ）２ ＃ｒｔ脳ｌ
ぐファージ外１ｔ３１１ ＋＋、＋１Ａ、Ｉ旧
・アルミナ］−テイゾ月黄第２図
（０１（１，）
第３図
（（１） （ｂ）第４図FIG. 1 is a plan view showing one embodiment of the present invention, and FIGS. 2 and 3 are plan views showing other embodiments of the invention. FIG. 4 shows a metal member used in a conventional resin-sealed semiconductor device. 1... integrated circuit frame, 2... φ resin package outline, 3 integrated circuit element, 11. IIA. 11B...Alumina coating film. Agent Masu Oiwa Female Figure 1 (0) (b) 2 #rt brain l
Guphage outside 1t311 ++, +1A, I old/Alumina] - Teizo Gekio Fig. 2 (01 (1,) Fig. 3 ((1) (b) Fig. 4
Claims (3)
に外部との信号の授受を行なう金属部材と、前記半導体
素子および金属部材を包囲する樹脂とからなる樹脂封止
形半導体装置において、前記金属部材の表面に、ファイ
ンセラミックスコーティング膜を備えたことを特徴とす
る樹脂封止形半導体装置。(1) In a resin-sealed semiconductor device comprising a semiconductor element, a metal member on which the semiconductor element is placed and which transmits and receives signals to and from the outside, and a resin surrounding the semiconductor element and the metal member, the metal A resin-sealed semiconductor device characterized by having a fine ceramic coating film on the surface of the member.
化物系または複合酸化物系セラミックスであることを特
徴とする特許請求の範囲第１項記載の樹脂封止形半導体
装置。(2) The resin-sealed semiconductor device according to claim 1, wherein the fine ceramic coating film is a single oxide ceramic or a composite oxide ceramic.
物系セラミックスであることを特徴とする特許請求の範
囲第１項記載の樹脂封止形半導体装置。(3) The resin-sealed semiconductor device according to claim 1, wherein the fine ceramic coating film is a non-oxide ceramic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP227187A JPS63169747A (en) | 1987-01-08 | 1987-01-08 | Resin sealed type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP227187A JPS63169747A (en) | 1987-01-08 | 1987-01-08 | Resin sealed type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63169747A true JPS63169747A (en) | 1988-07-13 |
Family
ID=11524705
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP227187A Pending JPS63169747A (en) | 1987-01-08 | 1987-01-08 | Resin sealed type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63169747A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02106939A (en) * | 1988-10-17 | 1990-04-19 | Semiconductor Energy Lab Co Ltd | Manufacture of member for electronic device |
| WO1998042022A1 (en) * | 1997-03-18 | 1998-09-24 | Seiko Epson Corporation | Semiconductor device and method of manufacturing same |
| KR100241476B1 (en) * | 1990-09-24 | 2000-02-01 | 윌리엄 비. 켐플러 | Insulated lead frame for integrated circuits and method of manufacture thereof |
| EP0867935B1 (en) * | 1997-03-25 | 2008-07-16 | Mitsui Chemicals, Inc. | Plastic package and semiconductor device |
-
1987
- 1987-01-08 JP JP227187A patent/JPS63169747A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02106939A (en) * | 1988-10-17 | 1990-04-19 | Semiconductor Energy Lab Co Ltd | Manufacture of member for electronic device |
| KR100241476B1 (en) * | 1990-09-24 | 2000-02-01 | 윌리엄 비. 켐플러 | Insulated lead frame for integrated circuits and method of manufacture thereof |
| WO1998042022A1 (en) * | 1997-03-18 | 1998-09-24 | Seiko Epson Corporation | Semiconductor device and method of manufacturing same |
| US6166446A (en) * | 1997-03-18 | 2000-12-26 | Seiko Epson Corporation | Semiconductor device and fabrication process thereof |
| EP0867935B1 (en) * | 1997-03-25 | 2008-07-16 | Mitsui Chemicals, Inc. | Plastic package and semiconductor device |
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