JPS63165915U - - Google Patents
Info
- Publication number
- JPS63165915U JPS63165915U JP5793787U JP5793787U JPS63165915U JP S63165915 U JPS63165915 U JP S63165915U JP 5793787 U JP5793787 U JP 5793787U JP 5793787 U JP5793787 U JP 5793787U JP S63165915 U JPS63165915 U JP S63165915U
- Authority
- JP
- Japan
- Prior art keywords
- turned
- power
- circuit
- output shows
- muting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005236 sound signal Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
Landscapes
- Amplifiers (AREA)
Description
第1図はこの発明の一実施例を示す回路構成図
、第2図は第1図の動作説明に供するための図、
第3図は従来回路の一例を示す回路構成図である
。
30はミユート回路、31は排他的論理和回路
、32,34及び33は第1の回路を構成する抵
抗器及びコンデンサ、35,36及び37は第2
の回路を構成する抵抗器及びコンデンサである。
FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of FIG. 1,
FIG. 3 is a circuit configuration diagram showing an example of a conventional circuit. 30 is a mute circuit, 31 is an exclusive OR circuit, 32, 34 and 33 are resistors and capacitors constituting the first circuit, and 35, 36 and 37 are second circuits.
These are the resistors and capacitors that make up the circuit.
Claims (1)
電源切断時に出力が急峻な立ち下がりを示す第1
の回路と、 電源投入時に出力がゆるやかな立ち上がりを示
し、電源切断時に出力がゆるやかな立ち下がりを
示す第2の回路と を備え、上記第1及び第2の回路の出力を排他的
論理和回路の入力側に夫々入力し、その出力によ
つて音声信号のミユーテイング制御を行なうよう
にしたことを特徴とするミユート回路。[Scope of utility model registration claim] The output shows a steep rise when the power is turned on,
The first case where the output shows a steep fall when the power is turned off.
and a second circuit whose output shows a gradual rise when the power is turned on and whose output shows a gradual fall when the power is turned off, and the outputs of the first and second circuits are connected to an exclusive OR circuit. What is claimed is: 1. A muting circuit, characterized in that the muting control of an audio signal is performed by inputting signals to the input sides of the respective input terminals, and controlling the muting of audio signals according to the output thereof.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5793787U JPS63165915U (en) | 1987-04-16 | 1987-04-16 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5793787U JPS63165915U (en) | 1987-04-16 | 1987-04-16 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63165915U true JPS63165915U (en) | 1988-10-28 |
Family
ID=30888083
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5793787U Pending JPS63165915U (en) | 1987-04-16 | 1987-04-16 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63165915U (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5611508B2 (en) * | 1977-08-30 | 1981-03-14 | ||
JPS59172813A (en) * | 1983-03-19 | 1984-09-29 | Fujitsu Ltd | Circuit for generating muting control signal |
-
1987
- 1987-04-16 JP JP5793787U patent/JPS63165915U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5611508B2 (en) * | 1977-08-30 | 1981-03-14 | ||
JPS59172813A (en) * | 1983-03-19 | 1984-09-29 | Fujitsu Ltd | Circuit for generating muting control signal |
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