JPS63157481A - Field-effect transistor - Google Patents
Field-effect transistorInfo
- Publication number
- JPS63157481A JPS63157481A JP30700486A JP30700486A JPS63157481A JP S63157481 A JPS63157481 A JP S63157481A JP 30700486 A JP30700486 A JP 30700486A JP 30700486 A JP30700486 A JP 30700486A JP S63157481 A JPS63157481 A JP S63157481A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- buffer layer
- electrodes
- source
- source electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 3
- 230000007423 decrease Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 230000003190 augmentative effect Effects 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 230000007935 neutral effect Effects 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電界効果トランジスタ〈以降ＦＥＴと称す）に
関し、特に低雑音の砒化ガリウムＦＥＴの構造に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to field effect transistors (hereinafter referred to as FETs), and particularly to the structure of low-noise gallium arsenide FETs.
従来、この種の低雑音のＦＥＴでは、主要パラメーター
であるトランスコンダクタンス−を大きくするために、
ｎ型の能動層と絶縁性基板の間に、低濃度のＰ型の不純
物層からなるバッファ層を設けている。Conventionally, in this type of low-noise FET, in order to increase the main parameter, transconductance,
A buffer layer made of a low concentration P-type impurity layer is provided between the n-type active layer and the insulating substrate.
通常、ＦＥＴのトランスコンダクタンスは、第３図に示
すように、バッファ層の不純物濃度が高くなる程大きく
なる。しかしながら通常ゲート電極及びソース電極の引
出し部分がバッファ層の上に直接あるいは酸化膜等の誘
電体膜を介して設けられているので、バッファ層の不純
物濃度が高くなるにつれてバッファ層の比抵抗が低くな
り、ゲート及びソース電極間の静電容量値は、第３図に
示すように増大する。Generally, the transconductance of an FET increases as the impurity concentration of the buffer layer increases, as shown in FIG. However, since the lead-out portions of the gate electrode and source electrode are usually provided on the buffer layer directly or through a dielectric film such as an oxide film, the resistivity of the buffer layer decreases as the impurity concentration of the buffer layer increases. Therefore, the capacitance value between the gate and source electrodes increases as shown in FIG.
又、低雑音ＦＥＴの利得は第４図に示すように、トラン
スコンダクタンスが大きくなる程増大するが、ゲート及
びソース電極間の静電容量値が太きくなるにつれて曲線
全体が下にシフトして利得は下がる。Furthermore, as shown in Figure 4, the gain of a low-noise FET increases as the transconductance increases, but as the capacitance value between the gate and source electrodes increases, the entire curve shifts downward and the gain decreases. goes down.
上述した従来のＦＥＴでは、バッファ層の不純物濃度及
びその厚さを制御することにより、トランスコンダクタ
ンス及び静電容量値の最適値を選び利得が最も良くなる
ようにしていたが、利得の大幅な改善が困難な上に制御
が難しいという欠点がある。In the conventional FET mentioned above, the optimal values of transconductance and capacitance are selected to obtain the best gain by controlling the impurity concentration and thickness of the buffer layer, but this method has significantly improved the gain. The disadvantage is that it is difficult to control and difficult to control.
本発明の電界効果トランジスタは、絶縁性基板上のバッ
ファ層表面に形成した所定のパターンの能動層上に設け
られたゲートと該ゲートと接続されかつ前記バッファ層
上に延長して設けられたゲート電極と前記能動層のソー
スの部分と接続しかつ前記バッファ層上に延長して設け
られたソース電極とを少くとも備え、前記バッファ層の
前記ゲート電極と前記ソース電極との間に表面から前記
絶縁性基板に至る絶縁領域が設けられてなる。The field effect transistor of the present invention includes a gate provided on an active layer having a predetermined pattern formed on the surface of a buffer layer on an insulating substrate, and a gate connected to the gate and provided extending on the buffer layer. a source electrode connected to a source portion of the active layer and extending above the buffer layer; An insulating region extending to the insulating substrate is provided.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）及び（ｂ）はそれぞれ本発明の第１の実施
例の平面図及びＡ−Ａ線断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line A--A, respectively, of a first embodiment of the present invention.
この実施例は、絶縁性基板１表面に形成した不純物濃度
が２ Ｘ １０ ”原子／ ｃｒｓ ３で厚さが３μｍ
のＰ型のバッファ層２表面に所定のパターンのＮ型の能
動層３を設け、能動層３表面上にゲート幅３００μｍの
ゲート４を設け、ゲート４に接続されかつバッファ層２
上に引出した面積が１６００μｍ２のゲート電極７を設
け、能動層のドレインと接続されたトレイン電極８及び
ソースと接続され、かつゲート電極４を囲むソース電極
６を設け、更にソース電極６とゲート電極７との間にバ
ッファ層２表面から絶縁性基板１に至る中性子のイオン
注入により形成されたイオン注入層５ａからなる絶縁領
域を設けている。In this example, the impurity concentration formed on the surface of the insulating substrate 1 is 2 x 10'' atoms/crs 3, and the thickness is 3 μm.
An N-type active layer 3 having a predetermined pattern is provided on the surface of the P-type buffer layer 2, a gate 4 with a gate width of 300 μm is provided on the surface of the active layer 3, and the gate 4 is connected to the buffer layer 2.
A gate electrode 7 with an area of 1600 μm2 drawn out above is provided, a train electrode 8 connected to the drain of the active layer and a source electrode 6 connected to the source and surrounding the gate electrode 4 are provided, and the source electrode 6 and the gate electrode An insulating region made of an ion implantation layer 5a formed by ion implantation of neutrons from the surface of the buffer layer 2 to the insulating substrate 1 is provided between the buffer layer 2 and the insulating substrate 1.
この実施例は、トランスコダクタンスが４５ｍ５で、ゲ
ート及びソース電極７及び６間の静電容量は０．１ｐＦ
となり、絶縁領域５ａが無い場合の０．４１）Ｆに比べ
て０．３ｐＦ程度低減されている。従って、この実施例
では、周波数が１２ Ｇ Ｈ２において、雑音指数１．
４ｄＢ、利得９．５ｄＢの特性が安定に得られる。In this example, the transcoductance is 45 m5 and the capacitance between the gate and source electrodes 7 and 6 is 0.1 pF.
This is reduced by about 0.3 pF compared to 0.41) F when there is no insulating region 5a. Therefore, in this example, at a frequency of 12 GH2, the noise figure is 1.
Characteristics of 4 dB and gain of 9.5 dB can be stably obtained.
第２図は本発明の第２の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the invention.
この実施例では、絶縁領域として、第１の実施例のイオ
ン注入層５ａの替りに絶縁用の溝５ｂを設けている。In this embodiment, an insulating groove 5b is provided as an insulating region instead of the ion-implanted layer 5a of the first embodiment.
以上説明したように本発明は、トランスコンダクタンス
を大きくするために設けたバッファ層上に形成したゲー
ト及びソース電極の間に、バッファ層表面から絶縁性基
板に至る絶縁領域を設けることにより、ゲート及びソー
ス電極間の静電容量を大幅に低減することが出来、その
結果として利得が高く高周波特性の優れた低雑音の砒化
ガリウム電界効果トランジスタを容易に実現できるとい
う効果がある。As explained above, the present invention provides an insulating region extending from the surface of the buffer layer to an insulating substrate between the gate and source electrodes formed on the buffer layer provided to increase transconductance. The capacitance between the source electrodes can be significantly reduced, and as a result, a gallium arsenide field effect transistor with high gain, excellent high frequency characteristics, and low noise can be easily realized.
第１図（ａ）及び（ｂ）はそれぞれ本発明の第１の実施
例の平面図及びＡ−Ａ線断面図、第２図は本発明の第２
の実施例の断面図、第３図はバッファ層の不純物濃度に
対するトランスコンダクタンス及びソース・ゲート電極
間の静電容重特性図、第４図はトランスコンダクタンス
−利得特性図である。
１・・・絶縁静基板、２・・・バッファ層、３・・・能
動層、４・・・ゲート、５ａ・・・イオン注入層、５ｂ
・・・溝、６・・・ソース電極、７・・・ゲート電極、
８・・・ドレイン電極。FIGS. 1(a) and (b) are a plan view and a sectional view taken along the line A-A of the first embodiment of the present invention, respectively, and FIG. 2 is a second embodiment of the present invention.
FIG. 3 is a graph showing the transconductance and capacitance between the source and gate electrodes with respect to the impurity concentration of the buffer layer, and FIG. 4 is a graph showing the transconductance-gain characteristics. DESCRIPTION OF SYMBOLS 1... Insulating static substrate, 2... Buffer layer, 3... Active layer, 4... Gate, 5a... Ion implantation layer, 5b
... Groove, 6... Source electrode, 7... Gate electrode,
8...Drain electrode.
Claims (1)
ーンの能動層上に設けられたゲートと該ゲートと接続さ
れかつ前記バッファ層上に延長して設けられたゲート電
極と前記能動層のソースの部分と接続しかつ前記バッフ
ァ層上に延長して設けられたソース電極とを少くとも備
え、前記バッファ層の前記ゲート電極と前記ソース電極
との間に表面から前記絶縁性基板に至る絶縁領域が設け
られたことを特徴とする電界効果トランジスタ。A gate provided on an active layer having a predetermined pattern formed on a surface of a buffer layer on an insulating substrate, a gate electrode connected to the gate and provided extending on the buffer layer, and a source of the active layer. an insulating region extending from the surface to the insulating substrate between the gate electrode and the source electrode of the buffer layer; A field effect transistor characterized by being provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30700486A JPH0673356B2 (en) | 1986-12-22 | 1986-12-22 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30700486A JPH0673356B2 (en) | 1986-12-22 | 1986-12-22 | Field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63157481A true JPS63157481A (en) | 1988-06-30 |
| JPH0673356B2 JPH0673356B2 (en) | 1994-09-14 |
Family
ID=17963858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30700486A Expired - Lifetime JPH0673356B2 (en) | 1986-12-22 | 1986-12-22 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0673356B2 (en) |
-
1986
- 1986-12-22 JP JP30700486A patent/JPH0673356B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0673356B2 (en) | 1994-09-14 |
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