JPS6315439A - Selective oxidization and isolation - Google Patents
Selective oxidization and isolationInfo
- Publication number
- JPS6315439A JPS6315439A JP15925886A JP15925886A JPS6315439A JP S6315439 A JPS6315439 A JP S6315439A JP 15925886 A JP15925886 A JP 15925886A JP 15925886 A JP15925886 A JP 15925886A JP S6315439 A JPS6315439 A JP S6315439A
- Authority
- JP
- Japan
- Prior art keywords
- nitride film
- resist
- wafer
- mask
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007254 oxidation reaction Methods 0.000 title claims abstract description 25
- 238000002955 isolation Methods 0.000 title claims abstract description 11
- 150000004767 nitrides Chemical class 0.000 claims abstract description 37
- 230000003647 oxidation Effects 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 14
- 238000001020 plasma etching Methods 0.000 claims abstract description 7
- 238000000926 separation method Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims 3
- 230000000873 masking effect Effects 0.000 claims 1
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid group Chemical group S(O)(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 4
- 239000007788 liquid Substances 0.000 abstract 2
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 29
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 241000218645 Cedrus Species 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高集積密度ＭＯ３ＩＣの製造に用いられる選
択酸化分離方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a selective oxidation separation method used in the production of high integration density MO3ICs.
本発明は、選択酸化分離方法において、選択酸化マスク
用窒化膜の形成時にウェハー裏面にデポされた窒化膜を
除去した後選択酸化を行うことにより、応力によるウェ
ハーのそりを低減するようにしたものである。The present invention is a selective oxidation separation method in which selective oxidation is performed after removing a nitride film deposited on the back surface of a wafer during formation of a nitride film for a selective oxidation mask, thereby reducing warping of the wafer due to stress. It is.
従来の選択酸化分離方法では、第２図に示すように、Ｓ
ｉ基板１上に界面応力緩衝用の酸化膜２を形成した後、
前記酸化膜２上に選択酸化マスク用の窒化膜３を形成す
る工程（第２図（ａ））と、活性領域をレジスト５でバ
ターニングし、前記レジスト５をマスクとして窒化膜３
をエツチングする工程（第２図（ｂ））と、熱酸化によ
り窒化膜３にマスクされていない分離領域上に分離用酸
化膜６を形成する選択酸化工程（第２図（Ｃ））とから
なる方法が知られている。In the conventional selective oxidation separation method, as shown in FIG.
After forming an oxide film 2 for interfacial stress buffering on the i-substrate 1,
A step of forming a nitride film 3 as a selective oxidation mask on the oxide film 2 (FIG. 2(a)), buttering the active region with a resist 5, and forming the nitride film 3 using the resist 5 as a mask.
(FIG. 2(b)) and a selective oxidation step (FIG. 2(C)) of forming an isolation oxide film 6 on the isolation region not masked by the nitride film 3 by thermal oxidation. There are known ways to do this.
従来の選択酸化分離方法では、裏面にデポされた窒化膜
のために、前記選択酸化時に裏面に酸化膜が十分成長し
ない。従って、ウェハー裏面と厚い分離用酸化膜６が形
成されるウェハー表面との間で応力に差が生し、ウェハ
ーが表面に凸に大きくそることになり、たとえばフォト
リソグラフィ一工程において、ウェハー吸着不良や合せ
精度劣化という問題が生じる。裏面に窒化膜３を形成し
ない目的で、２枚のウェハーの裏面をあわせて窒化膜３
を形成する方法も検討されたが、この場合、ウェハー間
のすきまから窒化膜生成ガスがはいりこみ部分的に窒化
膜が形成されるため、選択酸化時にウェハー裏面に酸化
膜が不均一に成長し、従って、ウェハーが波形にそり、
前記した問題を解決することができなかった。In the conventional selective oxidation separation method, the oxide film does not grow sufficiently on the back surface during the selective oxidation because of the nitride film deposited on the back surface. Therefore, a difference in stress occurs between the back surface of the wafer and the front surface of the wafer on which the thick isolation oxide film 6 is formed, causing the wafer to warp significantly toward the surface. This causes a problem of deterioration of alignment accuracy. In order to avoid forming the nitride film 3 on the back side, the back sides of the two wafers are combined to form the nitride film 3.
A method of forming a nitride film was also considered, but in this case, the nitride film-forming gas seeps into the gap between the wafers and forms a nitride film partially, resulting in the oxide film growing non-uniformly on the backside of the wafer during selective oxidation. , Therefore, the wafer warps into a waveform,
The above-mentioned problem could not be solved.
上記問題点を解決するために、本発明は、ウェハー裏面
にデポされた窒化膜をエツチングによって完全に除去し
、選択酸化時に裏面にも厚い酸化膜が形成されるように
した。In order to solve the above problems, the present invention completely removes the nitride film deposited on the back surface of the wafer by etching, so that a thick oxide film is also formed on the back surface during selective oxidation.
〔作用〕
ウェハー裏面にも厚い酸化膜が形成されるため、ウェハ
ー表面と裏面の応力が同程度になり、ウェハーのそりを
低減することができる。[Function] Since a thick oxide film is also formed on the back surface of the wafer, the stress on the front and back surfaces of the wafer becomes approximately the same, and warpage of the wafer can be reduced.
以下に本発明の実施例を図面にもとづいて説明する。第
１図（Ｂ）〜第１図（ｄ＋は、本発明の３Ｊ１沢酸化分
離法を説明するための工程順の断面図である。Embodiments of the present invention will be described below based on the drawings. FIG. 1(B) to FIG. 1(d+ are cross-sectional views in the order of steps for explaining the 3J1 oxidation separation method of the present invention.
第１図（ａｌは、Ｓｉ基板１上に、Ｓｉと窒化膜の界面
応力を緩和し、欠陥の発生を防ぐための酸化膜２を熱酸
化法により厚さ５００〜２０００ Ａ ” に形成した
後、化学気相成長法により、選択酸化マスク用の窒化Ｒ
グ３を厚さ５００〜２００ＯＡ ’に形成した工程を示
す。Figure 1 (al) shows the result of forming an oxide film 2 on a Si substrate 1 to a thickness of 500 to 2000 A'' by thermal oxidation to relieve the stress at the interface between the Si and the nitride film and to prevent the occurrence of defects. , nitrided R for selective oxidation mask by chemical vapor deposition method.
3 shows a step in which the groove 3 was formed to have a thickness of 500 to 200 OA'.
前記窒化膜形成は、ウェハー表面と裏面に窒化膜を形成
する方法（両面デポジション）でも、ウェハー表面のみ
に窒化膜を形成する方法（片面デポジション）のいずれ
でもかまわない。第１図ｆａｔでは両面デポジションの
場合を示す。）片面デポジションの場合でも、現在一般
に用いられている、たとえばウェハー裏面を他のウェハ
ー裏面と合わせて窒化膜成長させる方法では前記したよ
うにある程度の裏面上の窒化膜成長はさけられない。次
に、レジスト４をウェハー表面に厚さ１．５〜３μ鴎に
コートし、１００〜２００℃の温度でベークする。The nitride film formation may be performed by forming a nitride film on the front and back surfaces of the wafer (double-sided deposition) or by forming a nitride film only on the wafer surface (single-sided deposition). FIG. 1 fat shows the case of double-sided deposition. ) Even in the case of single-sided deposition, the currently commonly used method of growing a nitride film on the back side of a wafer along with the back side of another wafer cannot avoid growing a nitride film on the back side to some extent as described above. Next, the resist 4 is coated on the wafer surface to a thickness of 1.5 to 3 μm and baked at a temperature of 100 to 200°C.
通常のフォトリソグラフィ一工程にくらベレジスト厚が
厚いのは、次に行う裏面エツチングで、ウェハー表面を
下にしてエツチングする際に、ウェハ−表面を機械的を
員傷から保護するためである。The reason why the resist is thicker in one step of normal photolithography is to protect the wafer surface from mechanical damage when etching is performed with the wafer surface facing down in the next backside etching.
次に、たとえば、ＣＦ ａ系のガスを用いたプラズマエ
ツチング法により、ウェハー裏面の窒化膜を除去する。Next, the nitride film on the back surface of the wafer is removed by, for example, plasma etching using a CFa-based gas.
ウェハー裏面にプラズマが照射されるようにウェハーは
表面がウェハホルダーに接するようにセフ）する。（第
１図（ｂｌ）。裏面窒化膜除去後、レジスト４は硫酸系
のヱリ離液で除去する。Place the wafer so that the front side is in contact with the wafer holder so that the back side of the wafer is irradiated with plasma. (FIG. 1 (bl). After removing the nitride film on the back surface, the resist 4 is removed with a sulfuric acid-based solution.
次に、レジスト５をウェハー表面にコートし、フォトリ
ソグラフィ一工程により、活性領域上をマスクするよう
にレジスト５をバターニングした後に、たとえば、プラ
ズマエ・ンチング法、または反応性イオンエツチング法
により窒化膜３を、レジスト５をマスクとしてエツチン
グする。（第１図（Ｃ））。窒化膜３のエツチング後、
レジスト５は硫酸系の剥離液で除去する。次に、水蒸気
雰囲気中で、１０００−１１００℃の温度で熱酸化を行
い、前記窒化膜３でマスクされていない分離領域上に厚
さ０゜５〜１．５μ慣の分離用酸化膜を成長させる。（
第１図ｆｄｌ）、窒化膜３上は、酸化膜の成長がおそく
、厚さ数百Ａ°の酸化膜しかつかない。一方、ウェハー
裏面は、窒化膜が除去されているため、表面と同程度の
膜厚の酸化膜７が均一に形成される。Next, a resist 5 is coated on the wafer surface, and after patterning the resist 5 so as to mask the active region by one photolithography step, a nitride film is etched by, for example, a plasma etching method or a reactive ion etching method. 3 is etched using the resist 5 as a mask. (Figure 1 (C)). After etching the nitride film 3,
The resist 5 is removed using a sulfuric acid-based stripper. Next, thermal oxidation is performed at a temperature of 1000-1100°C in a steam atmosphere to grow an isolation oxide film with a thickness of 0°5-1.5 μm on the isolation region not masked by the nitride film 3. let (
(fdl) in FIG. 1, the oxide film grows slowly on the nitride film 3, and the oxide film is only several hundred angstroms thick. On the other hand, since the nitride film has been removed from the back surface of the wafer, an oxide film 7 having a thickness similar to that of the front surface is uniformly formed.
本発明は以上説明したように、選択酸化時に、ウェハー
表面と裏面の両方に均一に酸化膜が成長するため、表面
と裏面の応力差によりウェハーのそりが小さく抑えられ
る。従って、たとえば、フォトリソグラフィ一工程にお
けるウェハー吸着不良や合せ精度劣化のような問題発生
を防止できる。As described above, in the present invention, during selective oxidation, an oxide film is uniformly grown on both the front and back surfaces of the wafer, so that warping of the wafer can be suppressed to a minimum due to the difference in stress between the front and back surfaces. Therefore, for example, it is possible to prevent problems such as poor wafer suction and deterioration of alignment accuracy in one photolithography process.
第１図（ａｌ〜第１図ｆｄｌは本発明のｉ！沢酸酸化分
離方法製造工程順断面図、第２図（ａｌ〜第２図［Ｃ１
は従来の選択酸化分離方法の製造工程順断面図である。
１ ・ ・ ・Ｓｉ基板
２．７・・・酸化膜
３・・・窒化膜
４．５・・・レジスト
６・・・分離用酸化膜
以上
出願人 セイコー電子工業株式会社
代理人 弁理士 最 上 務（他１名）本私明の選２
杉１浚化分寥毬方法の蒙造ニオ里ｕ１氏Ｖケ面ｍ第１
図Fig. 1 (al to Fig. 1 fdl are cross-sectional views in the order of manufacturing steps of the i!sulfuric acid oxidation separation method of the present invention;
1A and 1B are cross-sectional views in the order of manufacturing steps of a conventional selective oxidation separation method. 1 ・ ・ ・Si substrate 2.7...Oxide film 3...Nitride film 4.5...Resist 6...Isolation oxide film and above Applicant Seiko Electronic Industries Co., Ltd. Agent Patent Attorney Mogami (1 other person) My selection 2
Cedar 1 Dredging branch method of Monzo Niori U1 Mr. V Kamen m 1st
figure
Claims (2)
前記酸化膜上に窒化膜を形成する工程と、前記半導体ウ
ェハー裏面側の前記窒化膜を除去する工程と、前記半導
体表面側の前記窒化膜を選択的にエッチングする工程と
、前記窒化膜をマスクとして前記酸化膜上に素子分離用
の熱酸化膜を形成する工程からなることを特徴とする選
択酸化分離方法。(1) Forming an oxide film on the semiconductor wafer surface;
a step of forming a nitride film on the oxide film, a step of removing the nitride film on the back side of the semiconductor wafer, a step of selectively etching the nitride film on the front side of the semiconductor, and a step of masking the nitride film. A selective oxidation isolation method comprising the step of forming a thermal oxide film for element isolation on the oxide film.
を用いて行うことを特徴とする特許請求の範囲第一項記
載の選択酸化分離方法。(2) The selective oxidation separation method according to claim 1, wherein the removal of the back surface nitride film is performed using a plasma etching method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15925886A JPS6315439A (en) | 1986-07-07 | 1986-07-07 | Selective oxidization and isolation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15925886A JPS6315439A (en) | 1986-07-07 | 1986-07-07 | Selective oxidization and isolation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6315439A true JPS6315439A (en) | 1988-01-22 |
Family
ID=15689827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15925886A Pending JPS6315439A (en) | 1986-07-07 | 1986-07-07 | Selective oxidization and isolation |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6315439A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5837378A (en) * | 1995-09-12 | 1998-11-17 | Micron Technology, Inc. | Method of reducing stress-induced defects in silicon |
| US7825004B2 (en) | 2006-08-23 | 2010-11-02 | Elpida Memory, Inc. | Method of producing semiconductor device |
| CN104347381A (en) * | 2013-07-25 | 2015-02-11 | 三菱电机株式会社 | Method of manufacturing semiconductor device |
| CN106033706A (en) * | 2015-03-11 | 2016-10-19 | 旺宏电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN107968039A (en) * | 2017-11-21 | 2018-04-27 | 长江存储科技有限责任公司 | Improve the method for wafer surface stress |
| CN112687524A (en) * | 2020-12-25 | 2021-04-20 | 长江存储科技有限责任公司 | Method for adjusting wafer curvature |
-
1986
- 1986-07-07 JP JP15925886A patent/JPS6315439A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5837378A (en) * | 1995-09-12 | 1998-11-17 | Micron Technology, Inc. | Method of reducing stress-induced defects in silicon |
| US7825004B2 (en) | 2006-08-23 | 2010-11-02 | Elpida Memory, Inc. | Method of producing semiconductor device |
| CN104347381A (en) * | 2013-07-25 | 2015-02-11 | 三菱电机株式会社 | Method of manufacturing semiconductor device |
| CN106033706A (en) * | 2015-03-11 | 2016-10-19 | 旺宏电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN107968039A (en) * | 2017-11-21 | 2018-04-27 | 长江存储科技有限责任公司 | Improve the method for wafer surface stress |
| CN112687524A (en) * | 2020-12-25 | 2021-04-20 | 长江存储科技有限责任公司 | Method for adjusting wafer curvature |
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