JPS6314501B2 - - Google Patents
Info
- Publication number
- JPS6314501B2 JPS6314501B2 JP4888181A JP4888181A JPS6314501B2 JP S6314501 B2 JPS6314501 B2 JP S6314501B2 JP 4888181 A JP4888181 A JP 4888181A JP 4888181 A JP4888181 A JP 4888181A JP S6314501 B2 JPS6314501 B2 JP S6314501B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- gate
- conductivity type
- impurity density
- cathode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000012535 impurity Substances 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 2
- 230000006698 induction Effects 0.000 description 11
- 238000000206 photolithography Methods 0.000 description 10
- 238000005530 etching Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 238000005498 polishing Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
本発明は、大電力でかつ高速な半導体装置、特
に静電誘導サイリスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a high-power, high-speed semiconductor device, particularly a static induction thyristor.
従来の静電誘導サイリスタは、ｎチヤンネル型
の例について説明するが、第１図ａに示すよう
に、１はアノードのp+領域、２はゲート・アノ
ード間のn-領域、３はゲートのp+領域、４はゲ
ート・カソード間のn-領域、５はカソードのn+
領域、６はアノード金属電極、７はカソード金属
電極、８はゲート・ゲード間、いわゆるチヤンネ
ルにより形成されている。この従来の静電誘導サ
イリスタの製造方法は、簡単に説明すると、まず
ゲート・アノード間のn-領域２をn-基板として、
ゲートのp+領域３を酸化、ホトリソグラフ技術、
選択エツチング、拡散又はイオン注入等により形
成する。このとき、アノードのp+領域１も同時
に形成することが多い。次にゲート・カソード間
のn-領域４をエピタキシヤル成長により形成し、
ゲートのp+領域３を埋め込む。次にカソードの
n+領域５を拡散又はエピタキシヤル成長、もし
くはイオン注入等により形成する。次に酸化、ホ
トリソグラフ技術、選択エツチングにより、カソ
ードのn+領域５及びゲート・カソード間のn-領
域４を除去してゲートのp+領域を露出させ、ゲ
ートのコンタクト領域を形成する。次にAl等の
金属を蒸着、ホトリソグラフ技術、選択エツチン
グ等により形成し、カソード、ゲート、アノード
の各金属電極を形成するものである。 A conventional electrostatic induction thyristor will be explained using an n-channel type example, and as shown in Figure 1a, 1 is the p + region of the anode, 2 is the n - region between the gate and anode, and 3 is the gate region. p + region, 4 is n - region between gate and cathode, 5 is n + of cathode
The regions are formed by an anode metal electrode 6, a cathode metal electrode 7, and a so-called channel between gates. Briefly, the conventional method for manufacturing a static induction thyristor is as follows: First, the n - region 2 between the gate and anode is used as an n - substrate.
Oxidize p + region 3 of gate, photolithography technique,
It is formed by selective etching, diffusion, ion implantation, etc. At this time, the p + region 1 of the anode is often formed at the same time. Next, an n - region 4 between the gate and cathode is formed by epitaxial growth,
Fill the p + region 3 of the gate. Next, the cathode
The n + region 5 is formed by diffusion, epitaxial growth, ion implantation, or the like. Next, by oxidation, photolithography, and selective etching, the n + region 5 of the cathode and the n − region 4 between the gate and cathode are removed to expose the p + region of the gate, thereby forming a contact region for the gate. Next, a metal such as Al is formed by vapor deposition, photolithography, selective etching, etc. to form each metal electrode of the cathode, gate, and anode.
第１図ａに示すような従来の静電誘導サイリス
タは、前述のような製造方法により製作さている
為、次のような欠点を有している。 Since the conventional electrostatic induction thyristor shown in FIG. 1a is manufactured by the manufacturing method described above, it has the following drawbacks.
ゲートのp+領域３を拡散あるいはイオン注入
により形成しているため、ゲート抵抗が大きい。
ゲート・カソード間のn-領域４のエピタキシヤ
ル成長は、ゲートのp+領域からのオートドーピ
ング補償のため比較的に不純物密度が高く（〜
1015〜1016／cm3）、又ゲート・カソードの対向面
積が大きいために、ゲート・カソード間容量が大
きい等の欠点により、素子の特性上、ターンオフ
タイムが大きい等の問題が生じている。 Since the p + region 3 of the gate is formed by diffusion or ion implantation, the gate resistance is large.
The epitaxial growth of n - region 4 between the gate and cathode has a relatively high impurity density (~
10 15 to 10 16 /cm 3 ), and because the facing area of the gate and cathode is large, the capacitance between the gate and cathode is large, which causes problems such as a long turn-off time due to the characteristics of the device. .
これらの欠点を除去したものとして第１図ｂに
示すような静電誘導サイリスタが提案されてい
る。この静電誘導サイリスタは、最大順方向阻止
電圧Vfnaxが大きく、順方向降下電圧Vfdが小さ
く、電圧利得μが大きく、ゲートターンオフ電流
Iaが大きく、ターンオフタイムTpffが小さく、タ
ーンオフ電流利得Ｇが大きい等の特性が得られる
ものとして提案されたものである。図中１〜８は
第１図ａと同じで、９は酸化膜等の絶縁物、１０
はｎ領域、１１はn+領域である。 An electrostatic induction thyristor as shown in FIG. 1b has been proposed to eliminate these drawbacks. This static induction thyristor has a large maximum forward blocking voltage V fnax , a small forward drop voltage V fd , a large voltage gain μ, and a gate turn-off current
This was proposed as a device that provides characteristics such as a large I a , a small turn-off time T pff , and a large turn-off current gain G. In the figure, 1 to 8 are the same as in Figure 1a, 9 is an insulator such as an oxide film, 10
is the n area, and 11 is the n + area.
以下第１図ｂの静電誘導サイリスタの本発明に
よる製造方法について述べる。 A method of manufacturing the electrostatic induction thyristor shown in FIG. 1b according to the present invention will be described below.
第２図ａに示すようにゲート・カソード間とな
るn-基板４の表面上に熱酸化等により酸化膜９
を形成し、ホトリソグラフ技術によりホトレジス
ト１３を形成する。次の工程によつては破線部分
まで形成する場合もある。 As shown in FIG. 2a, an oxide film 9 is formed on the surface of the n -substrate 4 between the gate and the cathode by thermal oxidation, etc.
A photoresist 13 is formed by photolithography. Depending on the next step, even the broken line portion may be formed.
次に第２図ｂに示すように異方性エツチを用い
て深さ5μ程度にn-基板４を除去する。又は第２
図b′に示す様に酸化膜９の開孔部をn-基板４を1μ
程度エツチ除去したのち、ホトリソグラフ技術に
より酸化膜９の開孔部を広げさらにn-基板４を
エツチ除去する工程を繰り返えし行なう事により
任意の傾斜を有するエツチ孔が形成できる。酸化
膜９の部分の寸法は５〜10μ程度、エツチ孔の底
部間は約50μ程度、深さは約5μ程度になる様に形
成する。 Next, as shown in FIG. 2b, the n - substrate 4 is removed to a depth of about 5 μm using anisotropic etching. or second
As shown in Figure b', the opening of the oxide film 9 is
After removing the etch to a certain extent, the opening of the oxide film 9 is enlarged by photolithography and the process of etching the n - substrate 4 is repeated, thereby forming an etch hole having an arbitrary slope. The size of the oxide film 9 is about 5 to 10 microns, the distance between the bottoms of the etched holes is about 50 microns, and the depth is about 5 microns.
次に第２図ｃに示す様にゲートとなるp+領域
３をエピ成長により形成する。エピ層の厚さは約
5μ程度とする。エピ成長によりp+領域は全体を
高不純物密度とすることができ、ゲート抵抗を小
さくすることができる。 Next, as shown in FIG. 2c, a p + region 3 which will become a gate is formed by epitaxial growth. The epi layer thickness is approx.
It should be about 5μ. By epitaxial growth, the entire p + region can have a high impurity density, and the gate resistance can be reduced.
次に第２図ｄに示す様に、ケミカル・メカニカ
ルポリツシユ技術により平面に研磨除去したのち
P+領域３からのオートドーピングをおさえる為
にｎ領域１４を約1μ程度エピ成長により形成し
た後、ホトリソグラフ技術によりホトレジスト１
３を形成する。 Next, as shown in Figure 2 d, after polishing it to a flat surface using chemical mechanical polishing technology,
In order to suppress autodoping from the P + region 3, the n region 14 is formed by epitaxial growth of about 1μ, and then the photoresist 1 is formed using photolithography.
form 3.
次に第２図ｅに示す様にｎ領域１４をエツチ除
去しホトレジスト１３を除去したのちゲート・ア
ノード間領域のn-領域２をエピ成長により形成
する。この時p+領域３の表面はｎ領域１４によ
りおおわれているのでp+の不純物の飛び出しは
なく、チヤンネル８がｐ型の不純物で接続するこ
ともなくかつn-領域２の不純物密度も低くする
ことができる。n-領域２の厚みは約70μ程度であ
る。続いてｎ領域１０をエピ成長により約4μ成
長し次いでアノードとなるp+領域１を１〜2μ程
度エピ成長により形成し、続いて熱酸化等により
酸化膜９を形成しホトリソグラフ技術によりホト
レジスト１３を形成する。 Next, as shown in FIG. 2e, after etching the n region 14 and removing the photoresist 13, the n - region 2 in the region between the gate and anode is formed by epitaxial growth. At this time, since the surface of the p + region 3 is covered with the n region 14, no p + impurity jumps out, the channel 8 is not connected with p type impurities, and the impurity density of the n - region 2 is also low. be able to. The thickness of n - region 2 is about 70 μm. Next, an n region 10 is grown by epitaxial growth of about 4 μm, and then a p + region 1, which will become an anode, is formed by epitaxial growth of about 1 to 2 μm. Next, an oxide film 9 is formed by thermal oxidation, etc., and a photoresist 13 is grown by photolithography. form.
次に第２図ｆに示す様に酸化膜９をエツチ除去
した後ホトレジスト１３を除去して拡散又はイオ
ン注入等によりn+領域１１を形成する。これは
ｎ領域１０と接続する様にする。 Next, as shown in FIG. 2F, after the oxide film 9 is etched away, the photoresist 13 is removed and an n + region 11 is formed by diffusion or ion implantation. This is connected to the n region 10.
次に第２図ｇに示す様にここから図面の上下が
逆になるがゲート・カソード間領域のn-領域４
をp+領域３が露出するまで研磨除去しn-領域４
の厚みを5μにする。続いて熱酸化膜９を形成す
る。 Next, as shown in Fig. 2g, the drawing is turned upside down from here, but n - region 4 is the region between the gate and cathode.
Polish away until p + area 3 is exposed and n - area 4
Make the thickness 5μ. Subsequently, a thermal oxide film 9 is formed.
次に第２図ｈに示す様に酸化膜９をホトリソグ
ラフ技術により除去しカソード領域のn+領域５
を拡散又はイオン注入等により形成する。 Next, as shown in FIG. 2h, the oxide film 9 is removed by photolithography, and the
is formed by diffusion or ion implantation.
次に第２図ｉに示す様にホトリソグラフ技術に
より酸化膜９をカソード領域のn+領域５及びゲ
ート領域のp+領域３のコンタクト孔の部分を除
去し、又アノード領域の酸化膜９を全面除去した
後Al等の金属を両面に亘り蒸着等によりAl電極
６，１５を形成する。 Next, as shown in FIG. 2i, the oxide film 9 is removed from the contact hole portions of the n + region 5 of the cathode region and the p + region 3 of the gate region by photolithography, and the oxide film 9 of the anode region is removed. After the entire surface is removed, Al electrodes 6 and 15 are formed by vapor deposition or the like over both surfaces of a metal such as Al.
次に第２図ｊに示す様にホトリソグラフ技術に
よりAl電極１５をカソード電極７とゲート電極
１２とにエツチ分離する。 Next, as shown in FIG. 2J, the Al electrode 15 is etched and separated into a cathode electrode 7 and a gate electrode 12 by photolithography.
以上の工程により静電誘導サイリスタが製造で
きる。このサイリスタはゲートとカソードが遠い
ためCGKが小さく、しかもチヤンネル８が狭いた
めμが大きい等の特徴を有し、前述の様なすぐれ
た特性を有するものである。ここではｎチヤンネ
ル型について述べるが導電型を変えればｐチヤン
ネル型静電誘導サイリスタもできることは明白で
ある。 An electrostatic induction thyristor can be manufactured through the above steps. This thyristor has characteristics such as a small C GK because the gate and the cathode are far apart, and a large μ because the channel 8 is narrow, and has the excellent characteristics described above. Although an n-channel type will be described here, it is clear that a p-channel type electrostatic induction thyristor can also be produced by changing the conductivity type.
第１図ａは従来の静電誘導サイリスタの断面
図、第１図ｂは本発明により製造された静電誘導
サイリスタの断面図、第２図ａ乃至ｊは本発明の
工程を示す工程断面図である。
１……アノード、２……ゲート・アノード間領
域、３……ゲート、４……ゲート・カソード間領
域、５……カソード、６……アノードの金属電
極、７……カソード金属電極、８……ゲート・ゲ
ート間いわゆるチヤンネルを示す。
FIG. 1a is a sectional view of a conventional electrostatic induction thyristor, FIG. 1b is a sectional view of an electrostatic induction thyristor manufactured according to the present invention, and FIGS. 2a to 2j are process sectional views showing the steps of the present invention. It is. DESCRIPTION OF SYMBOLS 1... Anode, 2... Gate-anode region, 3... Gate, 4... Gate-cathode region, 5... Cathode, 6... Anode metal electrode, 7... Cathode metal electrode, 8... ...Indicates a so-called channel between gates.
Claims (1)
不純物密度基板を用いて、主表面より壁面が傾斜
を有する孔を形成する工程と、前記孔にゲートと
して第２導電型の高不純物密度領域を充填する工
程と、前記第１導電型の主表面上に第１導電型の
低不純物密度領域をエピ成長により形成し第２導
電型の高不純物密度領域を埋め込む工程と、前記
第１導電型の低不純物密度基板の主表面の対向面
より第２導電型の高不純物領域を露出させる工程
と、カソード領域として前記露出された第１導電
型の低不純物密度基板の主表面の対向面の一部に
第１導電型の高不純物領域を形成する工程と、ア
ノード領域として前記第１導電型の低不純物密度
領域のエピ成長面に第２導電型の高不純物密度領
域を形成する工程と、カソード、アノード、ゲー
トに金属電極を形成する工程を含むことを特徴と
する半導体装置の製造方法。1. Forming a hole whose wall surface is inclined from the main surface using a low impurity density substrate of the first conductivity type as a gate/cathode region, and filling the hole with a high impurity density region of the second conductivity type as a gate. forming a low impurity density region of a first conductivity type on the main surface of the first conductivity type by epitaxial growth and embedding a high impurity density region of a second conductivity type; exposing a second conductivity type high impurity region from the opposite surface of the main surface of the impurity density substrate; and exposing a part of the exposed main surface of the first conductivity type low impurity density substrate as a cathode region. forming a high impurity density region of a second conductivity type on the epitaxial growth surface of the low impurity density region of the first conductivity type as an anode region; and forming a high impurity density region of a second conductivity type as an anode region. A method of manufacturing a semiconductor device, comprising the step of forming a metal electrode on a gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4888181A JPS57162463A (en) | 1981-03-31 | 1981-03-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4888181A JPS57162463A (en) | 1981-03-31 | 1981-03-31 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57162463A JPS57162463A (en) | 1982-10-06 |
| JPS6314501B2 true JPS6314501B2 (en) | 1988-03-31 |
Family
ID=12815619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4888181A Granted JPS57162463A (en) | 1981-03-31 | 1981-03-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57162463A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4782028A (en) * | 1987-08-27 | 1988-11-01 | Santa Barbara Research Center | Process methodology for two-sided fabrication of devices on thinned silicon |
-
1981
- 1981-03-31 JP JP4888181A patent/JPS57162463A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57162463A (en) | 1982-10-06 |
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