JPS63140521A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63140521A JPS63140521A JP28713686A JP28713686A JPS63140521A JP S63140521 A JPS63140521 A JP S63140521A JP 28713686 A JP28713686 A JP 28713686A JP 28713686 A JP28713686 A JP 28713686A JP S63140521 A JPS63140521 A JP S63140521A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- epitaxial
- layer
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 238000000034 method Methods 0.000 claims abstract description 39
- 239000012298 atmosphere Substances 0.000 claims abstract description 5
- 239000007789 gas Substances 0.000 claims description 13
- 229910052732 germanium Inorganic materials 0.000 claims description 12
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 239000012159 carrier gas Substances 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 claims 2
- 238000010438 heat treatment Methods 0.000 abstract description 31
- 238000000407 epitaxy Methods 0.000 abstract 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 6
- 229910052986 germanium hydride Inorganic materials 0.000 description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000007790 solid phase Substances 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 2
- 229910000070 arsenic hydride Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229940125904 compound 1 Drugs 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は半導体装置の製造方法に関し、特にシリコン基
板上に低温で８１のエピタキシャル膜を成長させる半導
体装置の製造方法に係わる。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device in which an epitaxial film 81 is grown on a silicon substrate at a low temperature.
［従来の技術］
従来、シリコン（Ｓｉ）基板−ににＳｉエピタキシャル
膜を形成する方法としては、例えば第６図〜第８図に示
す代表的なものが知られている。[Prior Art] Conventionally, as a method for forming a Si epitaxial film on a silicon (Si) substrate, typical methods shown in FIGS. 6 to 8, for example, are known.
（１）分子線エピタキシャル法（ＭＢＥ法）まず、第６
図（ａ）に示す如く、Ｓｉ基板１を塩酸と過酸化水素水
の混合液で洗浄し、炭素フリーな薄いＳｉ酸化膜２を形
成して表面を保護する。(1) Molecular beam epitaxial method (MBE method) First, the 6th
As shown in Figure (a), a Si substrate 1 is cleaned with a mixture of hydrochloric acid and hydrogen peroxide, and a thin carbon-free Si oxide film 2 is formed to protect the surface.
これを超高真空（〜ｌＸｌ０−９ｔｏｒｒ）のＭＢＥ装
置３中において、１８００〜９００℃に加熱して蒸発さ
せ、Ｓｔの清浄表面を得る（第６図（ｂ）図示）。この
際、ただ加熱するのみではなくて、Ｇａ、Ｓｉなどのビ
ームをＳｉ基板１表面に照射して、酸化膜をＧａ２０や
ＳｉＯのような揮発性の物質に変換して蒸発させ、Ｓｔ
の清浄表面を得る方法も用いられている。次に、清浄後
のＳｉ基板１にＳｉビームを入射させ、Ｓｉのエピタキ
シャル成長膜４を形成させる（第６図（Ｃ）図示）。This is heated and evaporated at 1800 to 900° C. in the MBE apparatus 3 of ultra-high vacuum (~lXl0-9 torr) to obtain a clean surface of St (as shown in FIG. 6(b)). At this time, instead of just heating, the surface of the Si substrate 1 is irradiated with a beam of Ga, Si, etc. to convert the oxide film into a volatile substance such as Ga20 or SiO and evaporate it.
A method of obtaining a clean surface has also been used. Next, a Si beam is applied to the cleaned Si substrate 1 to form an epitaxially grown Si film 4 (as shown in FIG. 6C).
（２）化学気相成長法（ＣＶＤ法）
まず、第７図（ａ）に示す如＜１１００℃でＮ２を流し
ている拡散炉５にＳｉ基板１を入れた後、Ｓｉ基板１上
の酸化膜２をＮ２と反応させ、Ｎ２０にして蒸発させる
（第７図（ｂ）図示）。(2) Chemical vapor deposition method (CVD method) First, as shown in FIG. 7(a), after placing the Si substrate 1 in a diffusion furnace 5 flowing N2 at <1100°C, oxidation on the Si substrate 1 is performed. The membrane 2 is reacted with N2, converted to N20, and evaporated (as shown in FIG. 7(b)).
次に、１１００℃でＮ２をキャリアにしてＳｉＨ４を流
し、清浄後のＳｉ基板１上にＳｉのエピタキシャル成長
膜４を形成させる（第７図（ｃ）図示）。Next, SiH4 is flowed at 1100° C. using N2 as a carrier to form an epitaxial growth film 4 of Si on the cleaned Si substrate 1 (as shown in FIG. 7(c)).
（３）固相エピタキシャル成長法
まず、第８図（ａ）に示す如＜１１００℃でＮ２を流し
ている拡散炉６にＳｉ基板１を入れ、Ｓｉ基板１−にの
Ｓｉ酸化膜２をＮ２と反応させＮ２０にして蒸発させ、
Ｓｉの清浄表面を得る（第８図（ｂ）図示）。次に、６
００℃でＮ２をキャリアにしてＳｉＨ４を流し、Ｓ ｋ
基板１」二にアモルファス膜６を形成する （第８図（
ｃ）図示）。次いで、Ｎ２雰囲気で６００℃で長時間熱
処理し、Ｓｉ基板１から順次アモルファスＳｉをエピタ
キシャル成長させ、Ｓｔの１１結晶膜７を得た（第８図
（ｄ）図示）。(3) Solid phase epitaxial growth method First, as shown in FIG. 8(a), the Si substrate 1 is placed in a diffusion furnace 6 in which N2 is flowing at <1100°C, and the Si oxide film 2 on the Si substrate 1- is grown with N2. React and evaporate with N20,
A clean surface of Si is obtained (as shown in FIG. 8(b)). Next, 6
SiH4 was flowed with N2 as a carrier at 00℃, and S k
An amorphous film 6 is formed on the substrate 1 (see Fig. 8).
c) As shown). Next, heat treatment was carried out at 600° C. for a long time in an N2 atmosphere, and amorphous Si was epitaxially grown one after another from the Si substrate 1, thereby obtaining an 11-crystalline film 7 of St (as shown in FIG. 8(d)).
［発明が解決しようとする問題点］
しかしながら、従来技術によれば、Ｓｉ酸化膜２を除去
してＳｉでの清浄表面を得るために、１１００℃の高嵩
処理（ＣＶＤ、固相エピタキシャル成長法の場合）、あ
るいは１×１０″″９ ｔｏｒｒの超高真空ドで８００
〜９００℃の熱処理を必要としている。従って、以ドに
列挙する問題点ををする。[Problems to be Solved by the Invention] However, according to the prior art, in order to remove the Si oxide film 2 and obtain a clean Si surface, a high bulk treatment (CVD, solid phase epitaxial growth method) at 1100° C. is used. ) or 1×10''9 torr ultra-high vacuum
Requires heat treatment at ~900°C. Therefore, we will address the problems listed below.
■効果な超高真空装置を必要とする。■Requires effective ultra-high vacuum equipment.
■高温熱処理を必要とするため、プロセスの使用材料が
増加するとともに、処理時間が増大する。■Since high-temperature heat treatment is required, the amount of materials used in the process increases and the processing time increases.
■高温熱処理によりＬＳＩのプロセスの工程が増加する
とともに、処理時間が増大する。(2) High-temperature heat treatment increases the number of LSI process steps and increases the processing time.
■高温熱処理によるランニングコストが高くなる。■Running costs increase due to high-temperature heat treatment.
■Ｓｉの表面清浄化処理にｔ′Ｐう汚染が生じ、素子特
性の劣化や歩留りを悪くさせる。(2) t'P contamination occurs during the Si surface cleaning process, resulting in deterioration of device characteristics and poor yield.
■高温熱処理によるドーピング元素の再分布などによる
素子特性のばらつきが生じる。■Differences in device characteristics occur due to redistribution of doping elements due to high-temperature heat treatment.
本発明は上記事情に鑑みてなされたもので、超高真空下
での熱処理Ｎ２雰囲気下での高温熱処理を必要とせず、
低温でＳｔのエピタキシャル膜を形成し得る半導体装置
の製造ノｊ法を提供することをに１的とする。The present invention was made in view of the above circumstances, and does not require heat treatment under ultra-high vacuum or high temperature heat treatment under N2 atmosphere.
One object of the present invention is to provide a method for manufacturing a semiconductor device that can form an epitaxial film of St at low temperatures.
Ｅ問題点を解決するための手段］
本願箱１の発明は、半導体基板」二にゲルマニウム（Ｇ
ｅ）層をエピタキシャル成長させる固定と、このＧｅ層
をａする前記基板を真空中又は水素ガス雰囲気中で４０
０℃の温度で熱処理し、該Ｇｅ層表面のＧｅの酸化層を
揮散させ、Ｇｅ層の表面を正常化する工程と、この正常
化されたＧｅ層上に半導体層をエピタキシャル成長させ
る工程とを具備することを要旨とする。Means for Solving Problem E] The invention in Box 1 of the present invention is based on the invention of box 1 which uses germanium (G) on a semiconductor substrate.
e) fixation for epitaxial growth of the layer and the substrate on which the Ge layer is grown for 40 minutes in vacuum or hydrogen gas atmosphere;
The method includes a step of performing heat treatment at a temperature of 0° C. to evaporate the Ge oxide layer on the surface of the Ge layer to normalize the surface of the Ge layer, and a step of epitaxially growing a semiconductor layer on the normalized Ge layer. The gist is to do so.
本願箱２の発明は、膜成長室内にＧｅＨ４ガスとキャリ
アガスを導入するとともにシリコン基板の温度を３００
℃以−にに保持し、前記基板表面のシリコン酸化膜を前
記Ｇ ｅ Ｈａガスと反応させて揮散させることにより
前記基板表面をＩＥ’Ｊ？ｌ化する工程と、前記基板上
にＧｅ層をエピタキシャル成長させる工程と、このＧｅ
層を有する前記基板を真空中又は水素ガス雰囲気中で４
００℃のｌＵ度で一熱処理し、該Ｇｅ層表面のＧｅの酸
化層を揮散させ、Ｇｅ層の表面を正常化する１−程と、
この正常化されたＧｅ層上にシリコン層をエピタキシャ
ル成長させる工程とを具備することを要旨とする。The invention in Box 2 introduces GeH4 gas and carrier gas into the film growth chamber, and at the same time raises the temperature of the silicon substrate to 300°C.
The silicon oxide film on the surface of the substrate is reacted with the G e Ha gas and volatilized, thereby exposing the surface of the substrate to IE'J? a step of epitaxially growing a Ge layer on the substrate, and a step of epitaxially growing a Ge layer on the substrate;
The substrate having the layer is heated in vacuum or in a hydrogen gas atmosphere for 4 hours.
1- heat treatment at 1U degrees of 00° C. to volatilize the Ge oxide layer on the surface of the Ge layer and normalize the surface of the Ge layer;
The gist is to include a step of epitaxially growing a silicon layer on this normalized Ge layer.
［作用］
（１）本発明は、Ｓｉ等の半導体基板の上に低温でＧｅ
のエビタキサル膜を形成させ、このＧｅ表面でＳｉ等の
エピタキシャル成長膜を形成させることを最も主要な特
徴とする。[Function] (1) The present invention allows Ge to be deposited on a semiconductor substrate such as Si at a low temperature.
The most important feature is to form an epitaxial film on the Ge surface, and to form an epitaxially grown film of Si or the like on this Ge surface.
（２）従来のＳｉ基板の−ＬにＳｉのエピタキシャル膜
を形成させる場合には、下地のＳｔの清浄表面を得るた
めに超高真空下での熱処理やＨ２雰囲気下での高温熱処
理が必要であったが、本発明ではこれらの処理を全く必
要としない。(2) When forming an Si epitaxial film on the -L of a conventional Si substrate, heat treatment under ultra-high vacuum or high temperature heat treatment under H2 atmosphere is required to obtain a clean surface of the underlying St. However, the present invention does not require these processes at all.
（３）本発明では、最初に半導体基板の上にＧｅのエピ
タキシャル膜を形成させる。この際、前記基板上の酸化
膜は４００℃程度の低温で飛来してきたＧｅ系ガスと反
応し、ＧｅＯとなって基板上から蒸発するので、容易に
Ｓｉなどの清浄表面が得られる。そして、清浄表面が得
られるやいなや自動的にＧｅがエピタキシャル成長する
（Ｈ，ｌ５ｂｉｌ、 ｃｔａｌ、 Ａ、 Ｐ、
Ｌ、 ４７ （８） 。(3) In the present invention, first, a Ge epitaxial film is formed on a semiconductor substrate. At this time, the oxide film on the substrate reacts with the incoming Ge-based gas at a low temperature of about 400° C., becomes GeO, and evaporates from the substrate, so that a clean surface of Si or the like can be easily obtained. Then, as soon as a clean surface is obtained, Ge is automatically grown epitaxially (H, l5bil, ctal, A, P,
L, 47 (8).
８６３ （１９８５）。863 (1985).
また、Ｇｅ膜形成後のＧｅ表面！−にはＧｅの酸化膜が
形成され、Ｓｉのエピタキシャル成長を阻害する。しか
し、４００℃程度の低温で熱処理すれば、Ｇｅの酸化膜
は揮散するので、Ｇｅの清浄表面が容易に得られる。故
に、飛来してきたＳｉ等は容易にＧｅ膜上でエピタキシ
ャル成長する。Also, the Ge surface after Ge film formation! A Ge oxide film is formed at -, which inhibits the epitaxial growth of Si. However, if the heat treatment is performed at a low temperature of about 400° C., the Ge oxide film will volatilize, so that a clean Ge surface can be easily obtained. Therefore, the flying Si and the like easily grow epitaxially on the Ge film.
本発明では、このようにＧｅのエピタキシャル膜を中間
層として用いることにより、低温で容易にＳｉなどのエ
ピタキシャル成長膜を得ることができる。In the present invention, by using the Ge epitaxial film as the intermediate layer in this way, an epitaxial growth film of Si or the like can be easily obtained at low temperatures.
（４）本発明では、低温プロセスであるので、ドーピン
グ元素の再分布や界面での相互拡散が生じず、素子特性
を劣化させない。(4) Since the present invention is a low-temperature process, redistribution of doping elements and interdiffusion at interfaces do not occur, and device characteristics do not deteriorate.
（５）本発明では、基板表面の正常化のために特別な操
作を必要としないので、汚染を生じる機会を少なくでき
る。(5) Since the present invention does not require any special operation to normalize the substrate surface, chances of contamination can be reduced.
［実施例］ 以下、本発明の一実施例を図を参照して説明する。[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
（実施例１） 第１図を参照する。(Example 1) Please refer to FIG.
まず、熱処理炉１１にＨ２をキャリアガスとして５ｉＨ
ａを流し、前記熱処理炉１１にＧｅのエピタキシャル層
１２を形成したＳｉ基板１３を挿入し、基板温度６５０
°Ｃて、処理する（第１図（ａ）図示）。ここで、基板
表面にはＧｅ酸化膜１４があるので、Ｓｉはエピタキシ
ャル成長しない。しかし、熱処理温度が６５０℃である
ので、Ｇｅ酸化膜１４はＧｅＯとなってＧｅ表面から脱
離し、短時間でＧｅ酸化膜１４は消滅する。そして、Ｇ
ｅの清浄表面が出現した段階で、熱分解反応５ｉＨ４−
＋Ｓｉ＋２Ｈ２により、Ｇ ｅ ７２面にＳｔのエピタ
キシャル成長膜１５が形成される（第１図（ｂ）図示）
。First, 5iH was heated in the heat treatment furnace 11 using H2 as a carrier gas.
A was poured, and the Si substrate 13 on which the Ge epitaxial layer 12 was formed was inserted into the heat treatment furnace 11, and the substrate temperature was set to 650.
°C (as shown in FIG. 1(a)). Here, since there is a Ge oxide film 14 on the substrate surface, Si does not grow epitaxially. However, since the heat treatment temperature is 650° C., the Ge oxide film 14 becomes GeO and desorbs from the Ge surface, and disappears in a short time. And G
At the stage when a clean surface of e appears, the thermal decomposition reaction 5iH4-
+Si+2H2 forms an St epitaxial growth film 15 on the G e 72 plane (as shown in FIG. 1(b)).
.
」１記実施例によれば、自動的にＧｅ表面が洗浄化され
、ＳｉＨ４を流すｔコけでＳｉのエピタキシャル成長膜
１５が形成できるため、従来の高真空・高温プロセスを
必要としない。According to the first embodiment, the Ge surface is automatically cleaned and the Si epitaxial growth film 15 can be formed by flowing SiH4, so the conventional high vacuum/high temperature process is not required.
（実施例２） 第２図を参照する。(Example 2) See Figure 2.
まず、熱処理炉１１のバルブ１６を閉にし、真空排気系
１７で熱処理炉１１を真空にする（第２図（ａ）図示）
。この結果、Ｇｅのエピタキシャル層１２表面上のＧｅ
酸化層１４がＧｅＯとなって蒸発し、Ｇｅの清浄表面が
出現する。次に、バルブ１６を開にし、Ｈ２のキャリア
ガスでＳｉＨ４を流すと、６５０℃の低温でもＳｔのエ
ピタキシャル成長膜１５が形成される（第２図（ｂ）図
示）。なお、Ｇｅの清浄表面を得る際、バ・ルブ１６を
開にしキャリアガスのＨ２のみを流し、真空排気系１７
を作動させ、熱処理炉１１を減圧下におき、約４００
’Ｃ以七の熱処理を行なうことでも同様にＧｅの清浄表
面が得られる。First, the valve 16 of the heat treatment furnace 11 is closed, and the heat treatment furnace 11 is evacuated using the vacuum exhaust system 17 (as shown in FIG. 2(a)).
. As a result, Ge on the surface of the Ge epitaxial layer 12
The oxide layer 14 becomes GeO and evaporates, leaving a clean surface of Ge. Next, by opening the valve 16 and flowing SiH4 with a carrier gas of H2, an epitaxial growth film 15 of St is formed even at a low temperature of 650° C. (as shown in FIG. 2(b)). Note that when obtaining a clean surface of Ge, the valve 16 is opened to allow only carrier gas H2 to flow, and the vacuum evacuation system 17 is
is operated, the heat treatment furnace 11 is placed under reduced pressure, and about 400
Similarly, a clean surface of Ge can be obtained by performing a heat treatment of C or higher.
（実施例３）
高真空装置を用い、実施例２と同様に高真空下で熱処理
し、Ｇｅ表面を清浄化した後に、ＳｉビームによるＭＢ
Ｅ蒸着により６５０℃よりも低温でＳｉのエピタキシャ
ル成長膜１５を形成させることができる。(Example 3) Using a high vacuum device, heat treatment was performed under high vacuum in the same manner as in Example 2 to clean the Ge surface, and then MB with Si beam was performed.
The epitaxial growth film 15 of Si can be formed at a temperature lower than 650° C. by E vapor deposition.
なお、上記実施例３において、Ｓｉビームと同時にＡｓ
、Ｓｂ等のビームも流し、Ｓｉエピタキシャル成長膜の
抵抗率を制御することかできる。In addition, in the above-mentioned Example 3, the Si beam and As
, Sb, etc. can also be applied to control the resistivity of the Si epitaxially grown film.
（実施例４）
第１図において、熱処理炉１１にＳｉ基板を人れ、真空
排気系１７を作動させてバルブ１６を開にし、Ｈ２をキ
ャリアガスとしてＧｅＨ４を流す。(Example 4) In FIG. 1, a Si substrate is placed in a heat treatment furnace 11, the evacuation system 17 is activated, the valve 16 is opened, and GeH4 is flowed using H2 as a carrier gas.
このとき、基板温度を約３００〜５００℃にしておくと
、前記Ｃｅ酸化層１４がＧｅＨ４のＧｅと反応しＧｅＯ
となって揮散してＳｉの清浄表面が出現し、この清浄Ｓ
ｉ表面に自動的にＧｅのエピタキシャル層１５が形成さ
れる。次に、ＧｅＨ４からＳｉＨ４にガスを切替えると
、実施例２で説明したように自動的にＣｅトにＳｉのエ
ピタキシャル成長膜が形成される。この操作を繰返すと
、容易にＳ ｉ ／ Ｇ ｅのエピタキシャル多層膜が
得られる。At this time, if the substrate temperature is kept at about 300 to 500°C, the Ce oxide layer 14 will react with Ge of GeH4 and become GeO2.
and volatilizes, a clean surface of Si appears, and this clean S
A Ge epitaxial layer 15 is automatically formed on the i surface. Next, when the gas is switched from GeH4 to SiH4, an epitaxial growth film of Si is automatically formed on Ce as explained in Example 2. By repeating this operation, an Si/Ge epitaxial multilayer film can be easily obtained.
しかるに、実施例４によれば、表面清浄化とエピタキシ
ャル膜形成を６４０℃以ドの温度で連続して進めること
ができ、従来のＭＢＥ法によるＳｉのエピタキシャル成
長では表面処理に９００００以」二の熱処理温度を必要
としたのに比べ、本発明の有利性が明らかである。However, according to Example 4, surface cleaning and epitaxial film formation can be performed continuously at a temperature of 640° C. or higher, and in the conventional MBE method for epitaxial growth of Si, surface treatment requires heat treatment of 90,000 or more degrees. The advantages of the present invention are clear compared to those that require temperature.
なお、１−記実施例４において、ＧｅＨ４の代わりにＧ
ｅＣ！等のガスを用いて同様のことを行なえる可能性が
ある。また、これらのガスを流すと同時に、ＡｓＨ３、
ＰＨ３，８２Ｈ６等のドーピングガスを流し、Ｓｉエピ
タキシャル成長膜の抵抗率を制御することができる。史
に、Ｇｅエピタキシャル層形成の代わりに、５ｉＧｅの
混晶層形成でもよい。但し、このときはＧｅ系ガスとＳ
ｉ系ガスを同時に流す。In addition, in Example 4 described in 1-1, G was used instead of GeH4.
eC! It is possible to do the same thing using gases such as Also, at the same time as flowing these gases, AsH3,
By flowing a doping gas such as PH3 or 82H6, the resistivity of the Si epitaxially grown film can be controlled. Historically, instead of forming a Ge epitaxial layer, a 5iGe mixed crystal layer may be formed. However, in this case, Ge-based gas and S
Flow i-based gases at the same time.
また、１°、記実施例１，２及び４において、キャリア
ガスとしてはＨ２、Ｈｅ、Ｎ２などのいずれも使用でき
る。Further, in Examples 1, 2, and 4, any of H2, He, N2, etc. can be used as the carrier gas.
更に、上記実施例１．２及び４において、ＳｉＨ４の代
わりにＳ ｉ２ Ｈ６、Ｓ １Ｈｃｊ？３゜５ｉ２Ｈ２
Ｃｊ？２のいずれも使用できる。また、これらのガスを
流すと同時に、ＡｓＨ３、ＰＨ３。Furthermore, in Examples 1.2 and 4 above, S i2 H6, S 1Hcj? 3゜5i2H2
Cj? Either of 2 can be used. Also, at the same time as flowing these gases, AsH3 and PH3.
Ｂ２ Ｈ，などのドーピングガスを流し、Ｓｉエピタキ
シャル成長膜の抵抗率を制御することができる。By flowing a doping gas such as B2H, the resistivity of the Si epitaxially grown film can be controlled.
（実施例５） 第３図を参照する。(Example 5) See Figure 3.
まず、Ｓｉ基板１３上に５ｉ０２膜１８を形成した後、
周知のりソグラフィ法により前記５ｉ０２膜１８の所定
の位置に開口部１８ａを形成する（第３図（ａ）図示）
。次に、ＧｅＨ４−Ｈ２系のＣＶＤ法により開口部１８
ａの底にＧｅのエピタキシャル層１９を選択的に形成し
た（第３図（ｂ）図示）。次いで、第１図及び第２図で
説明したｈ゛法により、前記エピタキシャル層１９上に
Ｓｉのエピタキシャル成長膜２０を形成した（第３図（
ｃ）図示）。ここで、５ｉ０２膜１８上に堆積したシリ
コン成長膜２０はアモルファスになる。そこで、Ｎ２雰
囲気中で６００℃で長時間熱処理すると、二−タキシャ
ルＳｉ層２１を種としてアモルファスＳｉは固相エピタ
キシャル成長し、Ｓｉのエピタキシャル基板２２が得ら
れた（第３図（ｄ）図示）。ここで、前記５ｉ０２膜１
８はプラズマＣＶＤ法や高圧酸化法により６００〜７０
０℃で形成できるので、第３図（ｃ）のエピタキシャル
基板２２は、７００℃以下の低温プロセスで形成できる
。First, after forming the 5i02 film 18 on the Si substrate 13,
An opening 18a is formed at a predetermined position in the 5i02 film 18 by a well-known lamination lithography method (as shown in FIG. 3(a)).
. Next, the opening 18 is formed using a GeH4-H2 based CVD method.
A Ge epitaxial layer 19 was selectively formed on the bottom of the layer a (as shown in FIG. 3(b)). Next, an epitaxial growth film 20 of Si was formed on the epitaxial layer 19 by the h method explained in FIGS. 1 and 2 (see FIG. 3).
c) As shown). Here, the silicon growth film 20 deposited on the 5i02 film 18 becomes amorphous. Therefore, by performing heat treatment at 600 DEG C. for a long time in an N2 atmosphere, amorphous Si was solid-phase epitaxially grown using the bi-taxial Si layer 21 as a seed, and an Si epitaxial substrate 22 was obtained (as shown in FIG. 3(d)). Here, the 5i02 film 1
8 is 600-70 by plasma CVD method or high pressure oxidation method.
Since it can be formed at 0°C, the epitaxial substrate 22 of FIG. 3(c) can be formed by a low temperature process of 700°C or less.
（実施例６）
第４図を参照する。ここで、第４図は第３図で説明した
Ｓｔのエピタキシャル基板を応用し、３次元デバイスで
ある。(Example 6) Refer to FIG. 4. Here, FIG. 4 shows a three-dimensional device by applying the St epitaxial substrate explained in FIG. 3.
本実施例では、まずＳｉＪ、Ｃ板１３に周知の方法でＭ
Ｏ３ＦＥＴ素子を作製し、電極配線形成後、５ｔ０２膜
１８をプラズマＣＶＤ法等により形成させ、第３図に説
明した方法によりＳｔのエピタキシャル基板２２を形成
した。つづいて、周知の技術により、このエピタキシャ
ル基板２２上にゲート酸化膜２３を介してゲー！・電極
２４を形成した。次いで、前記エピタキシャル基板２２
の表面にソース、ドリン領ｔ４２５，２６を形成しＭＯ
ＳＦＥＴを作製した。しかるに、このＭ ＯＳ Ｆ Ｅ
Ｔ ノ作製におイテハ、５ｉ０２膜１８の開口部１８
ａのＳｔ基板１３０表面の５ｉ０２膜１８を低温で除去
でき、Ｓｉ基板１４の表面に形成したＭＯＳＦＥＴのド
ーピング元素の再分布を生じしめることはない。In this embodiment, first, the SiJ, C plate 13 is
After producing an O3 FET element and forming electrode wiring, a 5t02 film 18 was formed by plasma CVD or the like, and an St epitaxial substrate 22 was formed by the method explained in FIG. Next, a gate oxide film 23 is formed on the epitaxial substrate 22 using a well-known technique. -The electrode 24 was formed. Next, the epitaxial substrate 22
Source and drain regions t425 and 26 are formed on the surface of the MO.
SFET was fabricated. However, this MOS F E
It is necessary to prepare the opening 18 of the 5i02 film 18.
The 5i02 film 18 on the surface of the St substrate 130 of a can be removed at a low temperature without causing redistribution of the doping elements of the MOSFET formed on the surface of the Si substrate 14.
（実施例７）
第５図を参照する。ここで、同図は新しい機能デバイス
への応用例を示すものである。まず、ＧａＡｓ基板３１
に周知のＭＢＥ法又はＭＯ−ＣＶＤ法によりＨＥＭＴを
作製し、ＧａＡｓ基板３１の一部にＧｅＨ４系のＣＶＤ
によりＧｅのエピタキシャル層１９を形成した。つづい
て、第１図及び第２図で説明した方法によりＳｉのエピ
タキシャル基板２２を形成し、この基板２２表面にＭＯ
ＳＦＥＴ等の素子を形成した。(Example 7) Refer to FIG. Here, the figure shows an example of application to a new functional device. First, the GaAs substrate 31
A HEMT is manufactured by the well-known MBE method or MO-CVD method, and GeH4-based CVD is applied to a part of the GaAs substrate 31.
A Ge epitaxial layer 19 was formed. Subsequently, an Si epitaxial substrate 22 is formed by the method explained in FIGS. 1 and 2, and an MO layer is formed on the surface of this substrate 22.
Elements such as SFET were formed.
しかるに、実施例７によれば、ＨＥ Ｍ Ｔ作製プロセ
ス及び５１−Ｍ０３ＦＥＴプロセスとも、プロセス温度
７００℃以下で形成することができ、又は化合物系半導
体素子とＳｉ系半導体素子を１つの基板上に共存させて
形成できるので、新しい機能結合デバイスを実現できる
。なお、ＨＥＭＴの代わりに他の化合物゛１′導体素子
でも同様である。However, according to Example 7, both the HEMT manufacturing process and the 51-M03FET process can be formed at a process temperature of 700° C. or lower, or a compound semiconductor element and a Si-based semiconductor element can coexist on one substrate. Since it can be formed in a single manner, new functionally combined devices can be realized. Note that the same applies to other compound 1' conductor elements instead of the HEMT.
以上説明したように、本発明ではＧｅ表面の酸化層が低
ｉＲで蒸発し、容易にＧｅの清浄表面が得られる性質を
利用している。このため、Ｓｔ上にＳｉをエピタキシャ
ル成長させる代わりに、５ｔ１−にＧｅのエピタキシャ
ル層を形成させてから、これを中間層としてＧｅ表面に
Ｓｉのエピタキシャル成長膜を形成させた方が低温のエ
ピタキシャル温度でＳｉのエピタキシャル膜を形成でき
る。As explained above, the present invention utilizes the property that the oxide layer on the Ge surface evaporates at a low iR and that a clean surface of Ge can be easily obtained. Therefore, instead of epitaxially growing Si on St, it is better to form an epitaxial layer of Ge on 5t1- and then use this as an intermediate layer to form an epitaxially grown film of Si on the Ge surface. epitaxial film can be formed.
つまり、本発明では、Ｓ ｉ−１：にＳｉをエピタキシ
ャル成長させる際に必要とされるＳｉ表面の高温熱処理
や超高真空下での熱処理二９の特別なＳｉ表面の清浄化
処理を不要とする利点がある。特に、本発明は、三次元
デバイスのＳｉエピタキシャルＵ板の形成、化合物半導
体素子とＳｔ系ｈａｔ、 ＬＱ体素子を同一基板上で結
合した新機能デバイスの形成。In other words, the present invention eliminates the need for high-temperature heat treatment of the Si surface or heat treatment under ultra-high vacuum that is required when epitaxially growing Si on Si-1: 29, which is a special cleaning treatment for the Si surface. There are advantages. In particular, the present invention relates to the formation of a Si epitaxial U plate for a three-dimensional device, and the formation of a new functional device in which a compound semiconductor element, an St-based hat, and an LQ element are combined on the same substrate.
Ｓｔ系Ｍ４導体素子のＳｉエピタキシャル膜形成などの
工程に使用すれば、これまでの不０■能であった低温プ
ロセスでのＳｔのエピタキシャル膜を容易に形成できる
。If used in a process such as forming a Si epitaxial film for an St-based M4 conductor element, it is possible to easily form an St epitaxial film in a low-temperature process that was previously impossible.
［発明の効果］
以上詳述した如く本発明によれば、特別な基板表面の清
浄化処理を必要とせず、低温でエピタキシャル膜を形成
し得、三次元デバイスのＳｔエピタキシャル基板の形成
等に有効な半導体装置の製造方法を提供できる。[Effects of the Invention] As detailed above, according to the present invention, an epitaxial film can be formed at a low temperature without the need for a special cleaning treatment of the substrate surface, and is effective for forming St epitaxial substrates for three-dimensional devices. A method for manufacturing a semiconductor device can be provided.
第１図（ａ）、（ｂ）は本発明の実施例１に係る半導体
装置の製造方法を工程順に示す図、第２図（ａ）、（ｂ
）は本発明の実施例２に係る半導体装置の製造方法を工
程順に示す図、第３図（ａ）〜（ｄ）は本発明の実施例
５に係る半導体装置の製造方法を工程順に示す断面図、
第４図は本発明の実施例６に係る３次元デバイスの断面
図、第５図は本発明の実施例７に係る新機能デバイスの
断面図、第６図（ａ） 〜（ｃ）はＭＢＥ法の説明図、
第７図（ａ） 〜（Ｃ）はＣＶＤ法の説明図、第８図は
固相エピタキシャル成長法の説明図である。
１１・・・熱処理炉、１２．１９・・・エピタキシャル
層、１３・・・Ｓｉ基板、１４・・・Ｇｅ酸化層、１５
・・・Ｓｔのエピタキシャル成長膜、１６・・・バルブ
、１７・・・真空排気系、１８・・・５ｉ０２膜、１９
・・・Ｇｅのエピタキシャル膜、２０・・・アモルファ
スＳｉ層、２１・・・エピタキシャルＳｉ層、２２・・
・エピタキシャル基板、３１・・・ＧａＡｓ基板。
出願人代理人 弁理士 鈴江武彦
第 １７３
１’ｆ Ｍ３ｒ！！Ｊ
箪４囚
Ｉｉ５囚
正立ら−−−ｌニ
ー−→Ｎ ２−−−−
ｌａｙ１1(a) and (b) are diagrams illustrating the manufacturing method of a semiconductor device according to Example 1 of the present invention in the order of steps, and FIGS. 2(a) and (b)
) is a diagram showing a method for manufacturing a semiconductor device according to Example 2 of the present invention in order of steps, and FIGS. 3(a) to 3(d) are cross sections showing a method for manufacturing a semiconductor device according to Example 5 of the present invention in order of steps figure,
FIG. 4 is a cross-sectional view of a three-dimensional device according to Example 6 of the present invention, FIG. 5 is a cross-sectional view of a new functional device according to Example 7 of the present invention, and FIGS. 6(a) to (c) are MBE. illustration of the law,
FIGS. 7(a) to (C) are explanatory diagrams of the CVD method, and FIG. 8 is an explanatory diagram of the solid phase epitaxial growth method. 11... Heat treatment furnace, 12.19... Epitaxial layer, 13... Si substrate, 14... Ge oxide layer, 15
...St epitaxial growth film, 16... Valve, 17... Vacuum exhaust system, 18... 5i02 film, 19
... Ge epitaxial film, 20 ... amorphous Si layer, 21 ... epitaxial Si layer, 22 ...
-Epitaxial substrate, 31...GaAs substrate. Applicant's agent Patent attorney Takehiko Suzue No. 173 1'f M3r! ! J 4th prisoner Ii 5th prisoner standing upright---l knee-→N 2---- lay1
Claims (2)
成長させる工程と、このゲルマニウム層を有する前記基
板を真空中又は水素ガス雰囲気中で４００℃の温度で熱
処理し、該ゲルマニウム層表面のゲルマニウムの酸化層
を揮散させ、ゲルマニウム層の表面を清浄化する工程と
、この清浄化されたゲルマニウム層上に半導体層をエピ
タキシャル成長させる工程とを具備することを特徴とす
る半導体装置の製造方法。(1) A step of epitaxially growing a germanium layer on the f-conductor substrate, and heat treating the substrate having the germanium layer at a temperature of 400°C in vacuum or in a hydrogen gas atmosphere to remove the germanium oxide layer on the surface of the germanium layer. A method for manufacturing a semiconductor device, comprising the steps of: cleaning the surface of a germanium layer by volatilization; and epitaxially growing a semiconductor layer on the cleaned germanium layer.
入するとともにシリコン基板の温度を３００℃以上に保
持し、前記基板表面のシリコン酸化膜を前記ＧｅＨ＿４
ガスと反応させて揮散させることにより前記基板表面を
清浄化する工程と、前記基板上にゲルマニウム層をエピ
タキシャル成長させる工程と、このゲルマニウム層を有
する前記基板を真空中又は水素ガス中で４００℃の温度
で熱処理し、該ゲルマニウム層表面のゲルマニウムの酸
化膜を揮散させ、ゲルマニウム層の表面を清浄化する工
程と、この清浄化されたゲルマニウム層上にシリコン層
をエピタキシャル成長させる工程とを具備することを特
徴とする半導体装置の製造方法。(2) Introducing GeH_4 gas and carrier gas into the film growth material, and maintaining the temperature of the silicon substrate at 300°C or higher, the silicon oxide film on the surface of the substrate is
a step of cleaning the substrate surface by reacting with a gas and volatilizing it; a step of epitaxially growing a germanium layer on the substrate; and a step of growing the substrate having the germanium layer in vacuum or in hydrogen gas at a temperature of 400°C. The method is characterized by comprising a step of heat-treating the surface of the germanium layer to volatilize the germanium oxide film on the surface of the germanium layer to clean the surface of the germanium layer, and a step of epitaxially growing a silicon layer on the cleaned germanium layer. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28713686A JPS63140521A (en) | 1986-12-02 | 1986-12-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28713686A JPS63140521A (en) | 1986-12-02 | 1986-12-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63140521A true JPS63140521A (en) | 1988-06-13 |
Family
ID=17713534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28713686A Pending JPS63140521A (en) | 1986-12-02 | 1986-12-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63140521A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5259918A (en) * | 1991-06-12 | 1993-11-09 | International Business Machines Corporation | Heteroepitaxial growth of germanium on silicon by UHV/CVD |
| US5286334A (en) * | 1991-10-21 | 1994-02-15 | International Business Machines Corporation | Nonselective germanium deposition by UHV/CVD |
| US5326721A (en) * | 1992-05-01 | 1994-07-05 | Texas Instruments Incorporated | Method of fabricating high-dielectric constant oxides on semiconductors using a GE buffer layer |
| RU2622092C1 (en) * | 2016-07-13 | 2017-06-09 | Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский Нижегородский государственный университет им. Н.И. Лобачевского" | Application of vacuum deposit germanium from the german gas medium as a method of removing silicon dioxide from the working surface of the silicon cover and method of manufacturing a germanium monocrystalline film on the silicon support including the used application |
-
1986
- 1986-12-02 JP JP28713686A patent/JPS63140521A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5259918A (en) * | 1991-06-12 | 1993-11-09 | International Business Machines Corporation | Heteroepitaxial growth of germanium on silicon by UHV/CVD |
| US5286334A (en) * | 1991-10-21 | 1994-02-15 | International Business Machines Corporation | Nonselective germanium deposition by UHV/CVD |
| US5326721A (en) * | 1992-05-01 | 1994-07-05 | Texas Instruments Incorporated | Method of fabricating high-dielectric constant oxides on semiconductors using a GE buffer layer |
| US5825055A (en) * | 1992-05-01 | 1998-10-20 | Texas Instruments Incorporated | Fabricating high-dielectric constant oxides on semiconductors using a GE buffer layer |
| RU2622092C1 (en) * | 2016-07-13 | 2017-06-09 | Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский Нижегородский государственный университет им. Н.И. Лобачевского" | Application of vacuum deposit germanium from the german gas medium as a method of removing silicon dioxide from the working surface of the silicon cover and method of manufacturing a germanium monocrystalline film on the silicon support including the used application |
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