JPS63136970A - Power source - Google Patents
Power sourceInfo
- Publication number
- JPS63136970A JPS63136970A JP61283966A JP28396686A JPS63136970A JP S63136970 A JPS63136970 A JP S63136970A JP 61283966 A JP61283966 A JP 61283966A JP 28396686 A JP28396686 A JP 28396686A JP S63136970 A JPS63136970 A JP S63136970A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- pulse
- pulse width
- circuit
- reference source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000003079 width control Methods 0.000 claims abstract description 20
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims description 6
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 abstract description 23
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 241000272525 Anas platyrhynchos Species 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Landscapes
- Pulse Circuits (AREA)
- Dc-Dc Converters (AREA)
- Inverter Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はスイッチング素子勿Mする電源回路、特にその
パルス幅側w4回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a power supply circuit that uses switching elements, particularly to its pulse width side w4 circuit.
一般に多くの′電源装置は第4図に示すように、入力端
子20.20′と出力端子21.21′間に接続された
主回路系22におけるインバータ回路、或いはチョッパ
回路、又はスイッチング型整流回路などのスイッチング
部22At−駆動する駆動回路23、この駆動回路にパ
ルス幅制御信号を与えるパルス幅制御回路24、及び本
発明のように軽負荷乃至は無負荷に至った場合にも比較
的厳しい出力電圧精度を要求される′1源にあっては列
負荷抵抗25’に備え1いる0ここで主回路系22Fi
前記回路の他に必要に応じて入力フィルタ或いは出力フ
ィルタなどの機能回路を備えておシ、またスイッチング
部22Aは1 m以上のスイッチングトランジスタ或い
はサイリスタのようなスイッチング素子を備えている。In general, many power supply devices include an inverter circuit, a chopper circuit, or a switching type rectifier circuit in the main circuit system 22 connected between the input terminal 20, 20' and the output terminal 21, 21', as shown in FIG. A driving circuit 23 that drives the switching unit 22At, a pulse width control circuit 24 that provides a pulse width control signal to this driving circuit, and a relatively strict output even when the load is light or no load as in the present invention. For sources that require voltage accuracy, the main circuit system 22Fi should be prepared for the column load resistance 25'.
In addition to the above-mentioned circuits, the switching section 22A is provided with functional circuits such as an input filter or an output filter as necessary, and the switching section 22A is provided with a switching element such as a switching transistor or a thyristor with a length of 1 m or more.
そしてスイッチング部22Aeパルス幅制−するパルス
1嘔制仰回路24はノイズによっても誤動作し難いとい
う点から積分型のものが−股に用いられ、これは出刃電
圧検出信号と基準源24Aの基準値との差に対応する誤
差信号を出力する演算増幅器24B、その誤差信号によ
りインピーダンスの変る可変インピーダンス回路24C
1可変インピーダンス回路24 Ct−iれる電流ft
積分する積分用コンデンサ24D、コンデンサ24Dの
t荷を胸勘的に放電するリセット用スイッチ24E、及
び積分用コンデンサ24L)の電圧と基準信号源24F
の基準レベルとを比較するコンパレータ24Gとからな
っている。The pulse 1 control circuit 24 that controls the pulse width of the switching unit 22Ae is of an integral type because it is unlikely to malfunction even due to noise, and this is based on the cutting voltage detection signal and the reference value of the reference source 24A. an operational amplifier 24B that outputs an error signal corresponding to the difference between
1 Variable impedance circuit 24 Ct-i current ft
The voltage of the integrating capacitor 24D that integrates, the reset switch 24E that discharges the load of the capacitor 24D, and the voltage of the integrating capacitor 24L) and the reference signal source 24F.
and a comparator 24G for comparing with a reference level.
このような構成のパルス幅制御回路によれば、出力電圧
検出信号の変動に伴い積分用コンデンサ24Dの充電時
定数が変化するので、積分用コンデンサ24Dの積分電
圧の上昇率、つまり傾斜が変化する。この積分電圧の傾
斜がパルス禍制御信号のパルス幅の変化となって現れる
のであり、前述し友ように出刃電圧検出信号の変化に関
連して変化する電流を積分しているので、このような積
分型のパルス編制g41!2回路はノイズによって誤動
作し難いという大きなメリットがある。According to the pulse width control circuit having such a configuration, the charging time constant of the integrating capacitor 24D changes as the output voltage detection signal changes, so the rate of increase, or slope, of the integrated voltage of the integrating capacitor 24D changes. . The slope of this integrated voltage appears as a change in the pulse width of the pulse damage control signal, and as mentioned above, since the current that changes in relation to the change in the blade voltage detection signal is integrated, such a The integral type pulse organization g41!2 circuit has the great advantage of being less likely to malfunction due to noise.
しかし前記の積分型のパルス鴨制御#回路24において
は積分用コンデンサ24Dの充電時定数を実質的に零に
することが出来ないので、この回路によるパルス幅制御
信号は必ず最小パルス幅をもってしまう0また、積分型
のパルス幅制御回路に限らず他の方式でも最小パルス幅
をもつ場合がある。この最小パルス幅がg5図に示すよ
うに軽負荷乃至は無負荷時に出力電圧を上昇させるので
おる。従って、出力電圧の積度が比較的厳しい電源装置
においては、、3g4図に示すように出力端子21 、
21’間に死負荷抵抗25を必ず接続せねばならず、こ
の死負荷抵抗が・電源装置の効率全低下させる大きな原
因となっていた。However, in the above-mentioned integral type pulse duck control # circuit 24, the charging time constant of the integrating capacitor 24D cannot be made substantially zero, so the pulse width control signal from this circuit always has a minimum pulse width of 0. Furthermore, not only the integral type pulse width control circuit but also other systems may have a minimum pulse width. This minimum pulse width increases the output voltage during light load or no load, as shown in diagram g5. Therefore, in a power supply device with relatively severe output voltage integration, the output terminal 21, as shown in Figure 3g4,
A dead load resistor 25 must be connected between 21' and this dead load resistor is a major cause of a total reduction in the efficiency of the power supply device.
〔問題点七屏決するた゛めの手段」
積分型のパルス幅側#回路に2いて、スイッチング素子
のスイッチング周仮数に同期し且つ出力電圧の大きさに
応じて低レベル幅の変化するオフ信号を発生するオフ信
号発生回路、及び前記スイッチング素子のスイッチング
周波数に同期して一定のオンパルス信号?生ずるオンメ
ルフ16号発生回路を備え これらオンパルス信号とオ
フパルス1ぎ号とによりパルス幅制御信号を形成する。[Means for determining the problem] Generates an off signal in the integral type pulse width side #2 circuit that is synchronized with the switching period mantissa of the switching element and whose low level width changes according to the magnitude of the output voltage. an off-signal generation circuit that generates a constant on-pulse signal in synchronization with the switching frequency of the switching element? A pulse width control signal is formed by the on-pulse signal and off-pulse No. 16.
軽負荷時乃至は無−)X荷時などにおいて出力電圧があ
るレベル以上に上昇すると、オンパルス信号の発生以前
に第2信号が有効になるためオンパルス1号がパルス幅
制御回路の出力端子に出現せず、従ってパルス幅制御信
号が欠相となる。つまり不発明によれば積分型のパルス
幅制御回路、或いは他の最小パルス幅をもつ回路の場合
でもパルス幅制御13号のパルス幅を完全に零に゛でき
る。When the output voltage rises above a certain level during light load or no load, etc., the second signal becomes valid before the on-pulse signal is generated, so on-pulse No. 1 appears at the output terminal of the pulse width control circuit. Therefore, the pulse width control signal has an open phase. In other words, according to the invention, even in the case of an integral type pulse width control circuit or other circuits having a minimum pulse width, the pulse width of the pulse width control No. 13 can be completely reduced to zero.
第1図により不発明に係るI!電源装置ノ(ルス嘱制御
回時の一実施例について説明する01は第4図に示した
パルス幅制御回路24とほぼ同様な構成のオフ信号発生
回路であp1第1の基準源2、この基準源の基準レベル
と出力電圧検出■号との差に比例する誤差(g号を生じ
る誤差増幅器6、その誤差信号の大きさによりインピー
ダンスの変化する可変インピーダンス回路4、積分用コ
ンデンサ5、スイッチング素子のスイッチング周波数に
同期して開閉する第1のリセット用スイッチ6、第2の
基準源7及びこの基準源の基準レベルと積分用コンデン
サ7の積分電圧とを比較するコンパレータ8からなる。According to Figure 1, I! 01 is an off signal generating circuit having a configuration substantially similar to the pulse width control circuit 24 shown in FIG. An error amplifier 6 that generates an error (g) proportional to the difference between the reference level of the reference source and the output voltage detection (■), a variable impedance circuit 4 whose impedance changes depending on the magnitude of the error signal, an integrating capacitor 5, and a switching element. It consists of a first reset switch 6 that opens and closes in synchronization with the switching frequency of , a second reference source 7 , and a comparator 8 that compares the reference level of this reference source with the integrated voltage of the integrating capacitor 7 .
9は制御用直流4源でめる0そして10はスイッチング
素子のスイッチング周波数と同期してオンパルス信号を
発生するオンパルス<g 号発生回路であり、抵抗器1
1、基準源12、積分用コンデンサi6、giのリセッ
ト用スイッチ6と同期して開閉する第2のリセット用ス
イッチ14及び基準源12の電圧と積分用コンデンサ1
6の積分電圧とを比較するコンパレータ15とからなる
1、16はパルス18制H4d号が出力される出力端子
でおる。Reference numeral 9 indicates an on-pulse<g generation circuit which generates an on-pulse signal in synchronization with the switching frequency of the switching element, and resistor 1.
1. Reference source 12, integrating capacitor i6, second reset switch 14 that opens and closes in synchronization with the reset switch 6 of gi, and the voltage of the reference source 12 and the integrating capacitor 1
1 and 16 are output terminals from which the 18-pulse signal H4d is output.
この様な構成の回路の動作t−[2図及び第6図をも用
いて説明する。The operation of the circuit having such a configuration will be explained using FIGS. 2 and 6.
先ずリセット用ヘイツチ6と1亀は第2図に示すように
クロツク1百号CによV開閉し、クロック信号Cのレベ
ルの高い期間で開き、レベルの低い期間で閉じるものと
する。オンパルス信号発生回路10において、リセット
用スイッチ14が開くと、コンデンサ13Fi抵抗11
などから決定される一定の充電時定数で充電されるので
、その光電電圧は一定の傾斜で上昇し、コンパレータ1
5は前記充電々圧が基準源12の電圧を超える時点でオ
ンパルス信号51t−出力する。一方オフ信号発生回路
1において、リセット用スイッチ6が閉じると、コンデ
ンサ5はqiインピーダンス回路4を流れる電流により
充電される。可変インピーダンス回路4のインピーダン
スは出力電圧の変化に応じて変化するので、当然に出力
電圧の変化に応じて可変インピーダンス回路4七流れる
4流も変化し、このことはコンデンサ5の充電々圧の上
昇率、つまり傾斜が変化することを示している。コンパ
レータ8は積分用コンデンサ5の充電々圧が基準源70
基準レベル以下の期間では高レベルの信号を出力し、前
記充電々圧が基準源70基準レベルを超えるとき低レベ
ル出力となる0この結果、オフ信号発生回路1は第2図
に示すようなオフ信号S2t″発生する。従って、端子
16には同図に示すように、オンパルス信号S、が立上
ってからオフ信号S2 が低レベルに降下するまでの
期間に等しいパルス幅をもつパルス幅制御信号S3
が得られる。First, the reset hatches 6 and 1 are opened and closed by the clock No. 100 C as shown in FIG. 2, and are opened during the high level period of the clock signal C and closed during the low level period. In the on-pulse signal generation circuit 10, when the reset switch 14 is opened, the capacitor 13Fi resistor 11
Since the photoelectric voltage is charged with a constant charging time constant determined from
5 outputs an on-pulse signal 51t- when the charging voltage exceeds the voltage of the reference source 12. On the other hand, in the off signal generation circuit 1, when the reset switch 6 is closed, the capacitor 5 is charged by the current flowing through the qi impedance circuit 4. Since the impedance of the variable impedance circuit 4 changes according to changes in the output voltage, naturally the four currents flowing through the variable impedance circuit 4 also change according to changes in the output voltage, and this causes an increase in the charging voltage of the capacitor 5. This shows that the rate, or slope, changes. The comparator 8 uses the charging voltage of the integrating capacitor 5 as a reference source 70.
During the period below the reference level, a high level signal is output, and when the charging voltage exceeds the reference level of the reference source 70, a low level signal is output.As a result, the off signal generating circuit 1 outputs an off signal as shown in FIG. Therefore, as shown in the figure, the terminal 16 receives a pulse width control signal having a pulse width equal to the period from the rise of the on-pulse signal S until the fall of the off-pulse signal S2 to a low level. signal S3
is obtained.
このようにt線装置の主回路系の出力′電圧が設定以下
の場合には、積分用コンデンサ50光電々圧の傾斜が設
定傾斜以下なのであるパルスvi、t−有するパルス幅
制御信号S3 がクロック信号Cに同期して端子16
に得られるが、前記出力電圧が設定値を超えるのに伴い
第6図に示すように積分用コンデンサ50充電々圧の傾
斜が夷#MW1 から点線R2に変ると、点線R1で示
すコンデンサ5の充電々圧が基準源7の基準レベルAt
−超える時点t0 はオンパルス信号S□の立上り時
点t、より早まる。従って、m線装置の主回路系の出力
電圧が設定以下になると、オンパルス信号発生回路10
からオンパルス信号S1 が発生される前にオフ信号
発生回路1のオフ1J号がM効な状態、つまりオフ信号
発生回路1の出力は低レベルになってお夕、端子16に
はパルス幅制御信号が出現しない。つまクバルス幅制呻
信号が欠相となる。In this way, when the output 'voltage of the main circuit system of the T-ray device is below the set value, the pulse width control signal S3 having the pulses vi, t- whose slope of the photoelectric voltage of the integrating capacitor 50 is less than the set slope is clocked. Terminal 16 in synchronization with signal C
However, as the output voltage exceeds the set value, the slope of the charging voltage of the integrating capacitor 50 changes from #MW1 to the dotted line R2 as shown in FIG. The charging pressure is the reference level At of the reference source 7
-The time point t0 exceeding the rising time point t of the on-pulse signal S□ is earlier. Therefore, when the output voltage of the main circuit system of the m-ray device falls below the setting, the on-pulse signal generation circuit 10
Before the on-pulse signal S1 is generated, the off-signal generating circuit 1's OFF No. 1J is in the M-effect state, that is, the output of the off-signal generating circuit 1 is at a low level. does not appear. Finally, the Kubarusu width control signal becomes out of phase.
そして次にクロック信号Cが低レベル期間になると、リ
セット用スイッチ6と14が閉じ、コンデンサ5,16
の電荷が放電される0以上のような動作はクロック信号
Cの各サイクルにおいて行われ、@負荷乃至は無負前状
態になるのに伴い゛4源装置の主回路系の出力電圧が設
定レベル金層えると、パルス幅制御信号が欠相となり、
そのクロックサイクルではスイッチング素子がオンしな
いので、前記出力電圧は減少する0
尚、前記実施例ではコンデンサ5.13の充電波形を利
用したが、それぞれの族1tte、形を利用してもよい
。この場合、可変インピーダンス回w!4はコンデンサ
5の放電回路に挿入され、コンデンサー肴の放′1回路
は所定の放寛時定数金もつよう設計される。Then, when the clock signal C becomes a low level period, the reset switches 6 and 14 are closed, and the capacitors 5 and 16 are closed.
An operation such as 0 or more in which the charge of When the gold layer increases, the pulse width control signal becomes open phase.
Since the switching element is not turned on in that clock cycle, the output voltage decreases.In the above embodiment, the charging waveform of the capacitor 5.13 is used, but the waveform of each group may be used. In this case, variable impedance times w! 4 is inserted into the discharge circuit of the capacitor 5, and the discharge circuit of the capacitor 5 is designed to have a predetermined discharge time constant.
以上述べた実施例では演算増幅器6の出力である誤差信
号によジコンデンサ50積分童の変る積分型のパルス幅
側(財)回路の場合についτ述べたが、演算増幅器乙の
誤差7号により基準源70基準信号のレベルが変化する
ようにしてもよく、積分型の構成でない回路でも勿論よ
い。In the embodiment described above, the case of an integral type pulse width circuit in which the dicapacitor 50 integrator is changed by the error signal which is the output of the operational amplifier 6 was described. The level of the reference signal of the reference source 70 may be changed, and of course a circuit other than an integral type may also be used.
以上述べたように、本発明では1源htitの主回路系
の出力電圧がある値以上に上昇した場付にはパルス幅制
御信号全欠相、つまりそのパルス幅七零とすることが出
来るので、ダミー抵抗を備えることなく、軽負荷乃至無
負前状態においても出力電圧を非常に相変の縄い範囲内
におさめることが可能でろる。従って、この発明に係る
電源展直によればダミー抵抗が不要なので効4t−同上
でき、ダミー抵抗による発熱の問題が解決されるので小
型化できるなど多大の効果を奏する。As described above, in the present invention, when the output voltage of the main circuit system of one source htit rises above a certain value, the pulse width control signal can be completely open, that is, the pulse width can be set to 70. , without providing a dummy resistor, it is possible to keep the output voltage within a very phase-variable range even under light load or no-negative conditions. Therefore, according to the power source extension according to the present invention, there is no need for a dummy resistor, so the efficiency can be increased by 4T, and the problem of heat generation caused by the dummy resistor is solved, so it can be miniaturized and has many effects.
第1図は本発明にがかるtS装置のパルス禍制御回路の
一実施例を示す図、第2図、第3図は第1図に図示した
回路を説明するための各部の波形図、第4図は従来例全
説明する次めの図、第5図は従来の負荷特性を示す図で
ある01・・・オフ信号発生tgl路 2,7・・・基
準源6・・・演算増幅器 4・・・可変インピーダンス
回路S、1&・・・積分用コンデンサ6
、1’@・・・リセット用スイッチS、1g・・・コ
ンパレータ 9・・・制御用直流電源10・・・オンパ
ルス信号発生回路特
許出願人 オリジン電気株式会社日
本電信電話株式会社
蔦 1 図FIG. 1 is a diagram showing an embodiment of the pulse damage control circuit of the tS device according to the present invention, FIGS. 2 and 3 are waveform diagrams of various parts for explaining the circuit shown in FIG. 1, and FIG. The figure is the next figure that explains the entire conventional example, and Figure 5 is a diagram showing the conventional load characteristics.01...OFF signal generation TGL path 2,7...Reference source 6...Operation amplifier 4. ...Variable impedance circuit S, 1 &... Integrating capacitor 6, 1'@... Reset switch S, 1g... Comparator 9... Control DC power supply 10... On-pulse signal generation circuit patent application People Origin Electric Co., Ltd. Nippon Telegraph and Telephone Corporation Tsuta 1 Figure
Claims (1)
信号と一定基準信号との誤差の大きさに比例する誤差信
号の大きさに応じてパルス幅の変るパルス幅制御回路を
備えた電源装置において、前記スイッチング素子のスイ
ッチング周波数に同期し且つ前記誤差信号の大きさに応
じて低レベル幅の変化するオフ信号を発生するオフ信号
発生回路、及び前記スイッチング素子のスイッチング周
波数に同期して一定のオンパルス信号を生ずるオンパル
ス発生回路を備え、前記出力電圧検出信号がある設定レ
ベルを超えるとき、前記オンパルス信号の発生以前に前
記オフ信号が有効になることによりパルス幅制御信号を
欠相させることを特徴とする電源装置。In the power supply device equipped with a pulse width control circuit that changes the pulse width according to the magnitude of an error signal that is proportional to the magnitude of the error between the output voltage detection signal of the voltage main circuit system equipped with the switching element and the constant reference signal, an off signal generation circuit that generates an off signal that is synchronized with the switching frequency of the switching element and whose low level width changes according to the magnitude of the error signal; and an off signal generation circuit that generates a constant on pulse signal that is synchronized with the switching frequency of the switching element. The power source is characterized in that the output voltage detection signal exceeds a certain set level, the off-signal becomes valid before the on-pulse signal is generated, and the pulse width control signal is made to have an open phase. Device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61283966A JP2585554B2 (en) | 1986-11-28 | 1986-11-28 | Power supply |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61283966A JP2585554B2 (en) | 1986-11-28 | 1986-11-28 | Power supply |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63136970A true JPS63136970A (en) | 1988-06-09 |
JP2585554B2 JP2585554B2 (en) | 1997-02-26 |
Family
ID=17672533
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61283966A Expired - Lifetime JP2585554B2 (en) | 1986-11-28 | 1986-11-28 | Power supply |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2585554B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008312335A (en) * | 2007-06-14 | 2008-12-25 | Mitsumi Electric Co Ltd | Switching power supply device and primary-side control circuit |
JP2010057361A (en) * | 1998-06-18 | 2010-03-11 | Linear Technol Corp | Voltage mode feedback burst mode circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5976171A (en) * | 1982-10-21 | 1984-05-01 | Nec Corp | Switching power source |
JPS62119025U (en) * | 1986-01-20 | 1987-07-28 |
-
1986
- 1986-11-28 JP JP61283966A patent/JP2585554B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5976171A (en) * | 1982-10-21 | 1984-05-01 | Nec Corp | Switching power source |
JPS62119025U (en) * | 1986-01-20 | 1987-07-28 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010057361A (en) * | 1998-06-18 | 2010-03-11 | Linear Technol Corp | Voltage mode feedback burst mode circuit |
JP2008312335A (en) * | 2007-06-14 | 2008-12-25 | Mitsumi Electric Co Ltd | Switching power supply device and primary-side control circuit |
Also Published As
Publication number | Publication date |
---|---|
JP2585554B2 (en) | 1997-02-26 |
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EXPY | Cancellation because of completion of term |