JPS6313534A - Bias voltage control circuit - Google Patents
Bias voltage control circuitInfo
- Publication number
- JPS6313534A JPS6313534A JP61157192A JP15719286A JPS6313534A JP S6313534 A JPS6313534 A JP S6313534A JP 61157192 A JP61157192 A JP 61157192A JP 15719286 A JP15719286 A JP 15719286A JP S6313534 A JPS6313534 A JP S6313534A
- Authority
- JP
- Japan
- Prior art keywords
- bias voltage
- apd
- voltage
- circuit
- conversion circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 31
- 230000003287 optical effect Effects 0.000 abstract description 21
- 230000035945 sensitivity Effects 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 11
- 238000001514 detection method Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 241000984642 Cura Species 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
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- Control Of Amplification And Gain Control (AREA)
- Optical Communication System (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、バイアス電圧制御回路に関し、特に出力イン
ピーダンスの影響を低減し、光受信部の最大受光感度の
高いバイアス電圧制御回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bias voltage control circuit, and particularly to a bias voltage control circuit that reduces the influence of output impedance and provides a high maximum light reception sensitivity of an optical receiver.
従来、第３図に示すとおり、この種の光受信器のアバラ
ンシェホトダイオード責以下、 ＡＰＤと略す）バイア
ス電圧制御回路は、 ＤＣ／ＤＣ変換回路３を有し、
ＡＰＤＩで受信した微弱な信号をできるだけ犬きく
、シかも雑音はできるだけ小さくするだめの最適な電流
増倍率が得られるように、振幅検出回路りで検出した利
得制御電圧をｂ端子に入力し、ＡＰＤバイアス電圧を制
御している。さらに光受信器は強い光を受信した場合も
動作するようにダイナミックレンジを大きくするように
々っている。つまり２強い光を受信した場合、利得制御
電圧は低くなるが。Conventionally, as shown in FIG. 3, the avalanche photodiode (hereinafter abbreviated as APD) bias voltage control circuit of this type of optical receiver has a DC/DC conversion circuit 3,
The gain control voltage detected by the amplitude detection circuit is input to the b terminal, and the gain control voltage detected by the amplitude detection circuit is input to the b terminal to obtain the optimal current multiplication factor that makes the weak signal received by the APDI as strong as possible and minimizes the noise. Controls bias voltage. Furthermore, optical receivers are designed to have a wide dynamic range so that they can operate even when receiving strong light. In other words, if strong light is received, the gain control voltage will be lower.
ＡＰＤ １を動作させるために最低限必要々バイアスミ
圧を得るために、抵抗器７．可変抵抗器８゜ダイオード
６．９のクラ７１回路により、 ＤＣ／ＤＣ変換回路へ
の入力端子Ｃ電位が下がりすぎ々いようにクランプされ
、ある程度ＡＰＤバイアス電圧も下がり過ぎないように
なっていた。In order to obtain the minimum necessary bias pressure to operate APD 1, resistor 7. The Cura 71 circuit of variable resistor 8° diode 6.9 clamps the input terminal C potential to the DC/DC conversion circuit to prevent it from dropping too much, and also prevents the APD bias voltage from dropping too much.
」二連した従来のＡＰＤバイアス電圧制御回路は、受光
素子ＡＰＤＩからの信号はできるだけ大きり、シかも雑
音はできるだけ小さくするような最適電流増倍率が得ら
れるバイアス電圧を供給している。The conventional dual APD bias voltage control circuit supplies a bias voltage that provides an optimal current multiplication factor that maximizes the signal from the light receiving element APDI and minimizes noise.
第４図に示すとおり、この最適電流増倍率は最小受光感
度を得るときに決定され、ＡＰＤＩ＜イアスミ圧は２図
中の線１のようになる。最適電流増倍率を得るだめの利
得制御信号は、第３図のｂ端子に入力されＤＣ／ＤＣ変
換回路３によって必要なバイアス電圧をＡＰＤＩに与え
ている。As shown in FIG. 4, this optimum current multiplication factor is determined when obtaining the minimum light-receiving sensitivity, and APDI<Iasumi pressure is as shown by line 1 in FIG. 2. A gain control signal for obtaining the optimum current multiplication factor is input to the b terminal in FIG. 3, and the DC/DC conversion circuit 3 applies a necessary bias voltage to the APDI.
さらに、光受信器は、ダイナミックレンジを大きくする
ために、ＡＰＤＩＯ増倍係数だけでなく２等化増幅器２
の利得も同時に変化させるように々っている。つ寸り、
光パワーが強いときも正常に動作させるためにＡＰＤ
１のバイアス電圧及び等化増幅器２の利得は下げるよう
になっている。このときｂ点に入力される利得制御電圧
は低く々りすぎ、 ＡＰＤＩが必要な応答速度を得るだ
めのバイアス電圧が、 ＤＣ／ＤＣ変換回路３から得ら
れなく々ってしまうため、第３図に示す従来のバイアス
電圧制御回路では、抵抗器７、可変抵抗器８．ダイオー
ド６．９のクランプ回路によって、利得制御電圧が下が
りすぎても。Furthermore, in order to increase the dynamic range, the optical receiver uses not only the APDIO multiplication coefficient but also the 2 equalizing amplifier 2.
It is designed to change the gain of both at the same time. One size,
APD for normal operation even when the optical power is strong
The bias voltage of the amplifier 1 and the gain of the equalizing amplifier 2 are lowered. At this time, the gain control voltage input to point b is too low, and the bias voltage needed to obtain the necessary response speed of APDI cannot be obtained from the DC/DC conversion circuit 3. In the conventional bias voltage control circuit shown in FIG. 1, resistor 7, variable resistor 8. Even if the gain control voltage drops too much due to the diode 6.9 clamp circuit.
ＡＰＤ １が必要な応答速度を得るためのバイアス電圧
が下がらないようになっている。The bias voltage required for APD 1 to obtain the necessary response speed is not reduced.
しかし、光入力パワーが強くなると、 ＡＰＤＩの光
電流も増大して来る。このとき、 ＤＣ／ＤＣ変換回路
３の出力点ｄの出力インピーダンスは充分には小さくな
いため、 ＡＰＤＩの光電流によって起こる電圧降下
が、光入力パワーの弱いときのように無視でき々く々る
。つまりクランプ回路によってＤＣ／ＤＣ変換回路３の
入力端子Ｃは一定以下に下がらないようにしていても、
出力インピーダンスが無視できないためにＡＰＤ １の
充電流増大によりｄ点の電位が下がりＡＰＤ １が必要
な応答速度を得るためのバイアス電圧が下がってしまい
動作しなく々る。However, as the optical input power increases, the photocurrent of APDI also increases. At this time, since the output impedance of the output point d of the DC/DC conversion circuit 3 is not small enough, the voltage drop caused by the photocurrent of APDI becomes negligible and dries up, just like when the optical input power is weak. In other words, even if the clamp circuit prevents the input terminal C of the DC/DC conversion circuit 3 from dropping below a certain level,
Since the output impedance cannot be ignored, the potential at point d decreases due to the increase in the charging current of APD 1, and the bias voltage required for APD 1 to obtain the necessary response speed decreases, causing it to no longer operate.
結局、光受信器の最大受光レベルは、主にＡＰＤバイア
ス電圧発生回路の出力インピーダンスによって決定され
てしまうという欠点を有する。As a result, the maximum light receiving level of the optical receiver is mainly determined by the output impedance of the APD bias voltage generation circuit.
第４図を用いて、光受信パワーとＡＰＤバイアス電圧と
の関係を示す。線１はＡＰＤＩの最小受光レベルで最適
電流増倍率を得るＡＰＤバイアス電圧と光入力パワーと
の関係である。ＡＰＤバイアス電圧９はＡＰＤ １が必
要な応答速度を得るための電圧である。第３図に示す回
路図で、抵抗器７．可変抵抗器８．ダイオード６．９で
構成しているクランプ回路がない場合の最大受光レベル
は、第４図の６の位置になる。このクランプ回路によっ
て、 ＤＣ／ＤＣ変換回路入力が一定電圧から下がら
ないようにしているため、 ＡＰＤバイアス電圧は第
４図の線２の電圧を維持するが。The relationship between optical reception power and APD bias voltage is shown using FIG. Line 1 is the relationship between the APD bias voltage and the optical input power to obtain the optimum current multiplication factor at the minimum light reception level of the APDI. APD bias voltage 9 is a voltage for APD 1 to obtain a necessary response speed. In the circuit diagram shown in FIG. Variable resistor8. The maximum light reception level in the absence of the clamp circuit constituted by the diode 6.9 is at position 6 in FIG. This clamp circuit prevents the DC/DC conversion circuit input from dropping from a constant voltage, so the APD bias voltage maintains the voltage on line 2 in Figure 4.
ＤＣ／ＤＣ変換回路３の出力インピーダンスが無視でき
ないことにより、ＡＰＤ電流増大（光入力パワー増大）
により、ＡＰＤバイアス電圧が線３のように降下してし
まい、最大受光レベルが６の位置になってしまう欠点を
有する。Since the output impedance of the DC/DC conversion circuit 3 cannot be ignored, the APD current increases (optical input power increases)
This has the drawback that the APD bias voltage drops as shown by line 3, and the maximum light reception level is at position 6.
点線５はＤＣ／ＤＣ変換回路３の出力インピーダンスが
０のときである。A dotted line 5 indicates when the output impedance of the DC/DC conversion circuit 3 is zero.
本発明によれば、受光素子と、該受光素子の電気信号を
受ける増幅器と、前記受光素子にバイアス電圧を与える
ＤＣ／ＤＣ変換回路と、前記増幅器の利得制御電圧を入
力し、前記ＤＣ／ＤＣ変換回路を制御する第１のトラン
ジスタとを有するバイアス電圧制御回路において、前記
バイアス電圧の分圧電圧と所定の基準電圧とを比較増幅
する比較増幅器と、該比較増幅器の出力を受け、前記第
１のトランジスタにワイヤードＯＲ接続する第２のトラ
ンジスタとを設け、前記受光素子に印加する前記バイア
ス電圧が常に一定レベル以上になるような負帰還回路を
構成したことを特徴とするバイアス電圧制御回路が得ら
れる。According to the present invention, a light receiving element, an amplifier that receives an electric signal of the light receiving element, a DC/DC conversion circuit that applies a bias voltage to the light receiving element, a gain control voltage of the amplifier is input, and the DC/DC a first transistor for controlling a conversion circuit; a comparison amplifier for comparing and amplifying a divided voltage of the bias voltage with a predetermined reference voltage; A bias voltage control circuit is provided, comprising: a second transistor which is wired OR connected to the transistor, and constitutes a negative feedback circuit such that the bias voltage applied to the light receiving element is always at a certain level or higher. It will be done.
次に１本発明について図面を参照して説明する。第１図
は１本発明の一実施例を示す回路図である。まず２等化
増幅器２と振幅検出回路りとから得た利得制御電圧は、
トランジスタ５を介して、 ＤＣ／ＤＣ変換回路３に
入力される。そしてＤＣ／ＤＣ変換回路３は光受信器の
最小受信感度でＡＰＤ １の最適電流増倍率が得られる
バイアス電圧をＡＰＤＩに印加している。つまシ、受光
素子ＡＰＤＩからの信号はできるだけ大きく。Next, one embodiment of the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention. First, the gain control voltage obtained from the 2 equalization amplifier 2 and the amplitude detection circuit is
It is input to the DC/DC conversion circuit 3 via the transistor 5. The DC/DC conversion circuit 3 applies a bias voltage to the APDI that provides the optimum current multiplication factor of the APD 1 with the minimum reception sensitivity of the optical receiver. The signal from the light receiving element APDI should be as large as possible.
しかも雑音はできるだけ小さくするような一つの負帰還
回路を構成している。このときのＡＰＤバイアス電圧と
光入力パワーとの関係は、第４図の線１のように々る。Furthermore, a single negative feedback circuit is configured to minimize noise. The relationship between the APD bias voltage and optical input power at this time is as shown by line 1 in FIG.
さらに、光受信器は。Additionally, the optical receiver.
ダイナミックレンジを大きくするために、 ＡＰＤＩＯ
増倍係数だけでかく９等化増幅器２の利得も同時に変化
させるようになっている。つｔｂ。To increase the dynamic range, APDIO
Not only the multiplication coefficient but also the gain of the 9-equalizing amplifier 2 is changed at the same time. Tsutb.
光パワーが強いときも正常に動作させるためにＡＰＤバ
イアス電圧及び等化増幅器２の利得は下げるようになっ
ている。このとき、ｂ点に入力される利得制御電圧は低
くなシすぎ、 ＡＰＤＩが必要々応答速度を得るための
バイアス電圧がＤＣ／ＤＣ変換回路３から得られ々く々
って、最大受信感度は、第４図に示される１６の位置に
なってしまう。尚、第４図の１９の位置のＡＰＤバイア
ス電圧は、 ＡＰＤＩが必要な応答速度を維持できる最
低バイアス電圧である。そこで、最大受光感度を向上さ
せるために、 ＡＰＤＩのバイアス電圧を、抵抗器１１
．１２で分圧し２分圧したバイアス電圧を抵抗器１４を
介して、比較増幅器１３に入力し基準電圧ｅと比較増幅
する。このようにして比較増幅した信号は、利得制御電
圧入力のトランジスタ５のエミッタにワイヤードＯＲ接
続するトランジスタ１５を介して、ＤＣ／ＤＣ変換回路
３に入力される。つ−１ｆｉ、ＡＰＤバイアス電圧が一
定電圧（第４図の線２の位置）からＡＰＤ電流増加とＤ
Ｃ／ Ｄ Ｃ変換回路の出力インピーダンスとのため
に降下しようとすると、 ＤＣ／ＤＣ変換回路３の入
力点Ｃの電圧を上げるように負帰還回路を構成し、ＡＰ
Ｄバイアス電圧は降下しないようになる。即ち、光入力
パワーが強くなりＡＰＤ電流が増加するとＤ Ｃ／ Ｄ
Ｃ変換回路３の出力インピーダンスが充分に低くない
ため、 ＡＰＤバイアス電圧は下がろうとするが、ＤＣ
／ＤＣ変換回路３の入力点Ｃを上げて出力点ｄの電圧を
上げる負帰還回路によってＤＣ／ＤＣ変換回路３の出力
インピーダンスの影響を低減し、 ＡＰＤバイアス電圧
は一定に保たれる。第４図の線４の位置までＤＣ／ＤＣ
変換回路の出力インピーダンスの影響を低減でき、最大
受光感度は、１８の位置になり、大幅に改善される。利
得制御電圧入力トランジスタ５と、ＡＰＤバイアス電圧
を分圧した分圧電圧と基準電圧とを比較増幅した負帰還
信号を入力するトランジスタ１５とは、互いのエミッタ
をワイヤードＯＲ接続してＤＣ／ＤＣ変換回路３に入力
しているため、 ＡＰＤバイアス電圧と光入力パワーと
の関係は、第４図太線のように々す、大き々ダイナミッ
クレンジを得ることができる。In order to operate normally even when the optical power is strong, the APD bias voltage and the gain of the equalizing amplifier 2 are lowered. At this time, the gain control voltage input to point b is too low, and the bias voltage for APDI to obtain the necessary response speed is obtained from the DC/DC conversion circuit 3. , resulting in position 16 shown in FIG. The APD bias voltage at position 19 in FIG. 4 is the lowest bias voltage at which the APDI can maintain the required response speed. Therefore, in order to improve the maximum light receiving sensitivity, the bias voltage of APDI is changed by resistor 11.
．． The bias voltage divided by 12 and divided by 2 is inputted to the comparison amplifier 13 via the resistor 14, and is compared and amplified with the reference voltage e. The signal thus compared and amplified is input to the DC/DC conversion circuit 3 via the transistor 15 which is wired OR connected to the emitter of the transistor 5 for inputting the gain control voltage. -1fi, the APD bias voltage changes from a constant voltage (position of line 2 in Figure 4) to an increase in APD current and D
If the output impedance of the C/DC converter circuit 3 attempts to drop due to the output impedance, a negative feedback circuit is configured to increase the voltage at the input point C of the DC/DC converter circuit 3, and the AP
The D bias voltage will not drop. That is, when the optical input power becomes stronger and the APD current increases, D C/D
Since the output impedance of the C conversion circuit 3 is not low enough, the APD bias voltage tries to decrease, but the DC
The influence of the output impedance of the DC/DC conversion circuit 3 is reduced by a negative feedback circuit that raises the input point C of the DC/DC conversion circuit 3 and the voltage at the output point d, and the APD bias voltage is kept constant. DC/DC to the position of line 4 in Figure 4
The influence of the output impedance of the conversion circuit can be reduced, and the maximum light receiving sensitivity is at position 18, which is significantly improved. The gain control voltage input transistor 5 and the transistor 15 which inputs a negative feedback signal obtained by comparing and amplifying a divided voltage obtained by dividing the APD bias voltage and a reference voltage perform DC/DC conversion by connecting their emitters with a wired OR. Since it is input to the circuit 3, the relationship between the APD bias voltage and the optical input power is as shown by the thick line in FIG. 4, and a large dynamic range can be obtained.
第２図はＤ Ｃ／Ｄ Ｃ変換回路出力電圧を分圧して負
帰還回路を構成した回路図である。FIG. 2 is a circuit diagram in which a negative feedback circuit is constructed by dividing the output voltage of the DC/DC conversion circuit.
以上説明したように１本発明はＡＰＤの電気信号を入力
として接続される増幅器の出力信号振幅、つまり、利得
制御電圧を入力するトランジスタと、 ＡＰＤへの印加
電圧を分圧する抵抗器と分圧されたＡＰＤ印加電圧を抵
抗器を介して入力し基準電圧と比較するための比較増幅
器および該増幅器出力を入力するとトランジスタをエミ
ッタどうしのワイヤードＯＲ接続し、さらにＤＣ／ＤＣ
変換器の制御入力にも接続することにより、光受信器の
ダイナミックレンジは大きくなり、特にＤＣ／ＤＣ変換
器の出力インピーダンスの影響を低減することにより最
大受光感度が大幅に向上する効果がある。As explained above, one aspect of the present invention is to divide the amplitude of the output signal of an amplifier connected with the electrical signal of the APD as input, that is, to divide the voltage between the transistor that inputs the gain control voltage and the resistor that divides the voltage applied to the APD. A comparator amplifier is used to input the APD applied voltage via a resistor and compare it with a reference voltage, and when the output of the amplifier is input, the emitters of the transistors are wired OR connected, and further DC/DC
By also connecting to the control input of the converter, the dynamic range of the optical receiver is increased, and in particular, by reducing the influence of the output impedance of the DC/DC converter, the maximum light receiving sensitivity is greatly improved.
第１図は本発明のバイアス電圧制御回路の実施例を示す
回路図、第２図はＩ）Ｃ７０Ｃ変換回路出力電圧を分圧
帰還した構成の一実施例を示す回路図、第３図は従来技
術によるバイアス電圧制御回路、第４図はＡＰＤバイア
ス電圧と光入力パワーの関係を示した図である。
１・・・アバランシェホトダイオード（ＡＰＤ）。
２・・・等化増幅器、３・・・ＤＣ／ＤＣ変換回路、４
・・・抵抗器、５・・・トランジスタ、６・・・ダイオ
ード。
７・・・抵抗器、８・・・可変抵抗器、９・・・ダイオ
ード。
１０・・・コンデンサ、 １１．１２・・・抵抗器、
１３・・・比較増幅器、１４・・・抵抗器、１５・・・
トランジスタ。
Ｄ・・・出力信号振幅検出回路、ａ・・・電圧電源端子
。
ｂ・・・利得制御電圧入力点、Ｃ・・・ＤＣ／ＤＣ変換
回路入力点、ｄ・・・Ｄ Ｃ／ Ｄ Ｃ変換回路出力点
、ｅ・・・基準電圧入力端子、線１・・・最小受光感度
でＡＰＤが最適電流増倍率が得られるときの光入力パワ
ーとＡＰＤバイアス電圧の関係、線２・・・従来および
本発明の回路図でＡＰＤバイアス電圧を一定に保とうと
するレベル、線３・・・従来の回路図でのＡＰＤバイア
ス電圧降下レベル、線４・・・本発明の回路図でのＡＰ
Ｄバイアス電圧降下レベル、線５・・・従来および本発
明の回路図でＡＰＤバイアス電圧を一定に保とうとし、
かつＤＣ／ＤＣ変換回路の出力インピーダンスがゼロの
ときのレベル、１６・・・利得制御回路のみの場合の最
大受光感度、１７・・・従来の回路での最大受光感度。
１８・・・本発明の回路での最大受光感度、１９・・・
ＡＰＤが必要々応答速度を得るためのＡＰＤバイ第１図
第２図Fig. 1 is a circuit diagram showing an embodiment of the bias voltage control circuit of the present invention, Fig. 2 is a circuit diagram showing an embodiment of a configuration in which I) C70C conversion circuit output voltage is divided and fed back, and Fig. 3 is a conventional circuit diagram. Bias voltage control circuit according to technology, FIG. 4 is a diagram showing the relationship between APD bias voltage and optical input power. 1... Avalanche photodiode (APD). 2... Equalization amplifier, 3... DC/DC conversion circuit, 4
...Resistor, 5...Transistor, 6...Diode. 7...Resistor, 8...Variable resistor, 9...Diode. 10... Capacitor, 11.12... Resistor,
13... Comparison amplifier, 14... Resistor, 15...
transistor. D...Output signal amplitude detection circuit, a...Voltage power supply terminal. b...gain control voltage input point, C...DC/DC conversion circuit input point, d...DC/DC conversion circuit output point, e...reference voltage input terminal, line 1... The relationship between the optical input power and the APD bias voltage when the APD can obtain the optimum current multiplication factor with the minimum light receiving sensitivity, line 2...The level at which the APD bias voltage is kept constant in the conventional and inventive circuit diagrams, line 3... APD bias voltage drop level in the conventional circuit diagram, line 4... AP in the circuit diagram of the present invention
D bias voltage drop level, line 5... In the conventional and inventive circuit diagrams, the APD bias voltage is kept constant,
and the level when the output impedance of the DC/DC conversion circuit is zero, 16... the maximum light receiving sensitivity in the case of only the gain control circuit, 17... the maximum light receiving sensitivity in the conventional circuit. 18... Maximum light receiving sensitivity in the circuit of the present invention, 19...
APD bias figure 1 figure 2 to obtain the required response speed of APD
Claims (1)
と、前記受光素子にバイアス電圧を与えるＤＣ／ＤＣ変
換回路と、前記増幅器の利得制御電圧を入力し、前記Ｄ
Ｃ／ＤＣ変換回路を制御する第１のトランジスタとを有
するバイアス電圧制御回路において、前記バイアス電圧
の分圧電圧と所定の基準電圧とを比較増幅する比較増幅
器と、該比較増幅器の出力を受け、前記第１のトランジ
スタにワイヤードＯＲ接続する第２のトランジスタとを
設け、前記受光素子に印加する前記バイアス電圧が常に
一定レベル以上になるような負帰還回路を構成したこと
を特徴とするバイアス電圧制御回路。1. A light-receiving element, an amplifier that receives an electric signal from the light-receiving element, a DC/DC conversion circuit that applies a bias voltage to the light-receiving element, and a gain control voltage of the amplifier is input, and the D
a first transistor for controlling a C/DC conversion circuit; a comparison amplifier for comparing and amplifying a divided voltage of the bias voltage with a predetermined reference voltage; and receiving an output of the comparison amplifier; Bias voltage control characterized in that a second transistor connected to the first transistor in a wired OR connection is provided, and a negative feedback circuit is configured such that the bias voltage applied to the light receiving element is always at a certain level or higher. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61157192A JPS6313534A (en) | 1986-07-05 | 1986-07-05 | Bias voltage control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61157192A JPS6313534A (en) | 1986-07-05 | 1986-07-05 | Bias voltage control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6313534A true JPS6313534A (en) | 1988-01-20 |
Family
ID=15644211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61157192A Pending JPS6313534A (en) | 1986-07-05 | 1986-07-05 | Bias voltage control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6313534A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01260918A (en) * | 1988-04-11 | 1989-10-18 | Nec Corp | Optical reception circuit |
| JPH04108230A (en) * | 1990-08-29 | 1992-04-09 | Nec Corp | Optical reception circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5711548A (en) * | 1980-06-25 | 1982-01-21 | Fujitsu Ltd | Optical receiving circuit |
-
1986
- 1986-07-05 JP JP61157192A patent/JPS6313534A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5711548A (en) * | 1980-06-25 | 1982-01-21 | Fujitsu Ltd | Optical receiving circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01260918A (en) * | 1988-04-11 | 1989-10-18 | Nec Corp | Optical reception circuit |
| JPH04108230A (en) * | 1990-08-29 | 1992-04-09 | Nec Corp | Optical reception circuit |
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