JPS63133569A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63133569A JPS63133569A JP28110386A JP28110386A JPS63133569A JP S63133569 A JPS63133569 A JP S63133569A JP 28110386 A JP28110386 A JP 28110386A JP 28110386 A JP28110386 A JP 28110386A JP S63133569 A JPS63133569 A JP S63133569A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- guard ring
- polycrystalline silicon
- epitaxial layer
- schottky diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 16
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 abstract description 7
- 229910021340 platinum monosilicide Inorganic materials 0.000 abstract description 7
- 230000010354 integration Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 239000000126 substance Substances 0.000 abstract description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にショットキーダイオー
ドを含む半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device including a Schottky diode.
従来、この種のショットキーダイオードを含む半導体装
置では、このダイオードと他の内部素子とを接続する配
線が、一般に、アルミニウム等の金属層からなっていた
。Conventionally, in semiconductor devices including this type of Schottky diode, wiring connecting the diode and other internal elements has generally been made of a metal layer such as aluminum.
上述した従来の半導体装置は、ショットキーダイオード
を接続する配線、例えばアノード側の配線が、内部素子
との間の接続に用いられる配線用金属層と同じなので、
接続のための専用配線領域を必要とし、これが余分な面
積を占めて、集積度向上の妨げになるという欠点がある
。In the conventional semiconductor device described above, the wiring connecting the Schottky diode, for example, the wiring on the anode side, is the same as the wiring metal layer used for connection with internal elements.
A disadvantage is that a dedicated wiring area is required for connection, which occupies extra area and impedes an increase in the degree of integration.
本発明の半導体装置は、−導電型の半導体層表面に形成
したショットキー接合と該ショットキー接合に接しかつ
周囲を囲む反対導電型のガードリングとを備えたショッ
トキーダイオードを含む半導体装置において、少くとも
前記ガードリングの上に反対導電型の不純物を含有し前
記ガードリング形成用の拡散源を兼ねる多結晶半導体層
からなるアノード電極を設けて成る。A semiconductor device of the present invention includes a Schottky diode including a Schottky junction formed on the surface of a semiconductor layer of a conductivity type and a guard ring of an opposite conductivity type that is in contact with and surrounds the Schottky junction, An anode electrode made of a polycrystalline semiconductor layer containing impurities of opposite conductivity type and serving as a diffusion source for forming the guard ring is provided at least on the guard ring.
この実施例は、素子分離用の絶縁層５ａによって仕切ら
れたｎ−型のエピタキシャル層３の所定の位置表面に接
するｐ型不純物を含有する多結晶シリコン層１を設け、
多結晶シリコン層１に接するエピタキシャル層３表面に
ｐ型のガードリング２を設け、ガードリンク２によって
囲まれたエピタキシャル層３表面にＰｔＳｉ層４からな
るショットキー電極を設け、多結晶シリコン層１は、シ
ョットキー電極とガードリング２を介して連なり、アノ
ード電極と他の内部素子とを接続している。In this embodiment, a polycrystalline silicon layer 1 containing a p-type impurity is provided in contact with the surface of an n-type epitaxial layer 3 at a predetermined position separated by an insulating layer 5a for element isolation.
A p-type guard ring 2 is provided on the surface of the epitaxial layer 3 in contact with the polycrystalline silicon layer 1, a Schottky electrode made of a PtSi layer 4 is provided on the surface of the epitaxial layer 3 surrounded by the guard link 2, and the polycrystalline silicon layer 1 is , are connected to the Schottky electrode via the guard ring 2, and connect the anode electrode and other internal elements.
又、この実施例を製造するには、先ず、絶縁層５ａによ
って仕切られた比抵抗１Ω・ｌのｎ−型のエピタキシャ
ル層３の表面に所定のパターンの絶縁層５ｂを形成した
後に、減圧化学気相成長（ＬＰＣＶＤ）法、５Ｘ１０”
個／ｃｓ＋２．６０ｋＶの条件のホウ素原子のイオン注
入及びホトリソグラフィーによって膜厚が３５０人で層
抵抗ρＳが１００Ω、／日程度の所定のパターンの多結
晶シリコン層１を形成する。次に、Ｎ２雰囲気で１００
０℃、１０分間の熱拡散を行い、多結晶シリコン層１に
接するエピタキシャル層３表面に深さ０．２５μｍのガ
ードリンク２を形成する。In order to manufacture this embodiment, first, an insulating layer 5b having a predetermined pattern is formed on the surface of an n-type epitaxial layer 3 with a specific resistance of 1 Ω·l partitioned by an insulating layer 5a, and then a low pressure chemical treatment is performed. Chemical vapor deposition (LPCVD) method, 5X10”
A polycrystalline silicon layer 1 having a predetermined pattern with a film thickness of 350 Ω/cs and a layer resistance ρS of about 100 Ω/day is formed by ion implantation of boron atoms and photolithography under the conditions of 2.60 kV/cs+2.60 kV. Next, 100% in N2 atmosphere.
Thermal diffusion is performed at 0° C. for 10 minutes to form a guard link 2 with a depth of 0.25 μm on the surface of the epitaxial layer 3 in contact with the polycrystalline silicon layer 1.
次に、ガードリンク１に囲まれたエピタキシャル層３表
面にｐｔを３うＯ入の厚さに被着し、Ｎ２雰囲気で５０
０℃、１５分間のシンターを行いＰｔＳ ｉ層４を形成
する。なお、白金の被着及びシンタ一時には多結晶シリ
コン層１は、その表面を酸化膜で被覆されているため、
多結晶シリコン層１の表面にはＰｔＳ ｉ層は形成され
ない。Next, PT was deposited on the surface of the epitaxial layer 3 surrounded by the guard link 1 to a thickness of 3 O, and
Sintering is performed at 0° C. for 15 minutes to form a PtSi layer 4. Note that during platinum deposition and sintering, the surface of the polycrystalline silicon layer 1 is covered with an oxide film, so
No PtSi layer is formed on the surface of polycrystalline silicon layer 1.
このようにショットキーダイオードはｎ−エピタキシャ
ル層３とＰｔＳ ｉ層４上の接合によって形成される。A Schottky diode is thus formed by a junction on the n-epitaxial layer 3 and the PtSi layer 4.
又、近来のバイポーラトランジスタは、自己整合技術の
採用により、その電極引き出し部分に多結晶シリコン層
を使用しているが、これ等のトランジスタがｎｐｎ型の
場合、ベース引き出し電極はホウ素原子を含む多結晶シ
リコン層であり、一方、ショットキーダイオードのアノ
ード側は、はとんどの場合′ベースに接続して使用され
る。そこで、トランジスタのベース電極とショットキー
ダイオードのアノード側は、ホウ素原子を含む−続きの
多結晶シリコン層によって接続することができる。In addition, recent bipolar transistors use a polycrystalline silicon layer for the electrode extension part by adopting self-alignment technology, but when these transistors are npn type, the base extraction electrode is made of a polycrystalline silicon layer containing boron atoms. The anode side of the Schottky diode, on the other hand, is most often used connected to the base. The base electrode of the transistor and the anode side of the Schottky diode can then be connected by a subsequent polycrystalline silicon layer containing boron atoms.
従って、ショットキーダイオードのガードリングは、通
常、耐圧の向上を目的として形成されるがこ・本発明の
構造では、耐圧の向上と共にショットキーダイオードの
アノードとしての役割を担っている。Therefore, the guard ring of the Schottky diode is normally formed for the purpose of improving the withstand voltage, but in the structure of the present invention, it not only improves the withstand voltage but also plays the role of an anode of the Schottky diode.
更に又、アノード電極となる多結晶シリコン層のホウ素
原子の含有率を下げて（例えばイオン注入条件５×１０
′４個／Ｃ１ｌ ２．６０ｋＶ、層抵抗５にΩ／口）形
成した多結晶シリコン層を抵抗体として、バイポーラＲ
ＡＭのショットキー負荷セルを構成するという使用方法
もある。Furthermore, the content of boron atoms in the polycrystalline silicon layer that will become the anode electrode is lowered (for example, the ion implantation conditions are 5×10
'4 pieces/C1l 2.60kV, layer resistance 5Ω/mouth) The formed polycrystalline silicon layer is used as a resistor, and bipolar R
Another use is to configure an AM Schottky load cell.
以上説明したように本発明は、ショットキーダイオード
のアノード側の電極及びそれに連なる配線として、ガー
ドリングに接続した多結晶シリコン層を使用することに
より、他の内部素子と接続する為の専用配線を新たに形
成する必要がなく、従って面積効率が良くなり集積度を
向上させることができるという効果がある。As explained above, the present invention uses a polycrystalline silicon layer connected to a guard ring as the anode side electrode of a Schottky diode and the wiring connected thereto, thereby creating a dedicated wiring for connecting to other internal elements. There is no need to newly form one, and therefore the area efficiency is improved and the degree of integration can be improved.
特に、本発明によってバイポーラＲ，Ａ Ｍのショット
キーダイオードの抵抗体及び抵抗体とトランジスタのベ
ースのそれぞれを接続するためのコンタクト領域も不要
となるため、一層集積度を向上させることができるとい
う効果もある。In particular, the present invention eliminates the need for the resistor of the bipolar R and AM Schottky diodes and the contact regions for connecting the resistor and the base of the transistor, thereby further improving the degree of integration. There is also.
第１図は本発明の一実施例の断面図である。
１・・・多結晶シリコン層、２・・・ガードリング、３
・・・エピタキシャル層、４・・・ＰｔＳｉ層、５ａ。
５ｂ、５ｃ、 ５ｄ−絶縁層。FIG. 1 is a sectional view of an embodiment of the present invention. 1... Polycrystalline silicon layer, 2... Guard ring, 3
...Epitaxial layer, 4...PtSi layer, 5a. 5b, 5c, 5d - insulating layer.
Claims (1)
と該ショットキー接合に接しかつ周囲を囲む反対導電型
のガードリングとを備えたショットキーダイオードを含
む半導体装置において、少くとも前記ガードリングの上
に反対導電型の不純物を含有し前記ガードリング形成用
の拡散源を兼ねる多結晶半導体層からなるアノード電極
を設けたことを特徴とする半導体装置。In a semiconductor device including a Schottky diode comprising a Schottky junction formed on the surface of a semiconductor layer of one conductivity type and a guard ring of an opposite conductivity type in contact with and surrounding the Schottky junction, at least 1. A semiconductor device comprising an anode electrode made of a polycrystalline semiconductor layer containing impurities of opposite conductivity type and serving as a diffusion source for forming the guard ring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61281103A JPH0671074B2 (en) | 1986-11-25 | 1986-11-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61281103A JPH0671074B2 (en) | 1986-11-25 | 1986-11-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63133569A true JPS63133569A (en) | 1988-06-06 |
| JPH0671074B2 JPH0671074B2 (en) | 1994-09-07 |
Family
ID=17634389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61281103A Expired - Lifetime JPH0671074B2 (en) | 1986-11-25 | 1986-11-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0671074B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02264475A (en) * | 1989-01-25 | 1990-10-29 | Cree Res Inc | Silicon carbode schottkey diode and its manufacture |
| US6573128B1 (en) | 2000-11-28 | 2003-06-03 | Cree, Inc. | Epitaxial edge termination for silicon carbide Schottky devices and methods of fabricating silicon carbide devices incorporating same |
| US7026650B2 (en) | 2003-01-15 | 2006-04-11 | Cree, Inc. | Multiple floating guard ring edge termination for silicon carbide devices |
| US9515135B2 (en) | 2003-01-15 | 2016-12-06 | Cree, Inc. | Edge termination structures for silicon carbide devices |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS586313A (en) * | 1981-07-01 | 1983-01-13 | Matsushita Electric Ind Co Ltd | Combustion apparatus for liquid fuel |
-
1986
- 1986-11-25 JP JP61281103A patent/JPH0671074B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS586313A (en) * | 1981-07-01 | 1983-01-13 | Matsushita Electric Ind Co Ltd | Combustion apparatus for liquid fuel |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02264475A (en) * | 1989-01-25 | 1990-10-29 | Cree Res Inc | Silicon carbode schottkey diode and its manufacture |
| US6573128B1 (en) | 2000-11-28 | 2003-06-03 | Cree, Inc. | Epitaxial edge termination for silicon carbide Schottky devices and methods of fabricating silicon carbide devices incorporating same |
| US6673662B2 (en) | 2000-11-28 | 2004-01-06 | Cree, Inc. | Epitaxial edge termination for silicon carbide Schottky devices and methods of fabricating silicon carbide devices incorporating same |
| US7026650B2 (en) | 2003-01-15 | 2006-04-11 | Cree, Inc. | Multiple floating guard ring edge termination for silicon carbide devices |
| US7419877B2 (en) | 2003-01-15 | 2008-09-02 | Cree, Inc. | Methods of fabricating silicon carbide devices including multiple floating guard ring edge termination |
| US7842549B2 (en) | 2003-01-15 | 2010-11-30 | Cree, Inc. | Methods of fabricating silicon carbide devices incorporating multiple floating guard ring edge terminations |
| US8124480B2 (en) | 2003-01-15 | 2012-02-28 | Cree, Inc. | Methods of fabricating silicon carbide devices incorporating multiple floating guard ring edge terminations |
| US9515135B2 (en) | 2003-01-15 | 2016-12-06 | Cree, Inc. | Edge termination structures for silicon carbide devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0671074B2 (en) | 1994-09-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH09199707A (en) | High withstand voltage semiconductor device | |
| JPH05145076A (en) | Vertical type current semiconductor device utilizing wafer-bonding and manufacture thereof | |
| JPH0673376B2 (en) | Bipolar semiconductor device | |
| JPS6322070B2 (en) | ||
| JP2605030B2 (en) | Quadrature bipolar transistor | |
| JPS63133569A (en) | Semiconductor device | |
| US3454846A (en) | High frequency transistor having a base region substrate | |
| JP3099917B2 (en) | Field effect transistor | |
| US3316128A (en) | Semiconductor device | |
| JPH06236989A (en) | Inverse n well cathode schottky transistor and manufacture thereof | |
| JPH0254662B2 (en) | ||
| JP2668528B2 (en) | Method for manufacturing semiconductor device | |
| US3959810A (en) | Method for manufacturing a semiconductor device and the same | |
| JPH0555553A (en) | Semiconductor integrated circuit | |
| JPS6346990B2 (en) | ||
| JPS58107645A (en) | Manufacture of semiconductor device | |
| JPH0318738B2 (en) | ||
| JPH0437581B2 (en) | ||
| JPS5968963A (en) | Semiconductor device and manufacture thereof | |
| JPS6347962A (en) | Semiconductor device | |
| JPH0376023B2 (en) | ||
| JP2002009249A (en) | Semiconductor device and its manufacturing method | |
| JPS6230364A (en) | Manufacture of mis semiconductor device | |
| JPS62139355A (en) | Semiconductor device | |
| JPH0371670A (en) | Semiconductor integrated circuit |