JPS63130933U - - Google Patents

Info

Publication number
JPS63130933U
JPS63130933U JP2049787U JP2049787U JPS63130933U JP S63130933 U JPS63130933 U JP S63130933U JP 2049787 U JP2049787 U JP 2049787U JP 2049787 U JP2049787 U JP 2049787U JP S63130933 U JPS63130933 U JP S63130933U
Authority
JP
Japan
Prior art keywords
count
output
counts
counter
preset data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2049787U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2049787U priority Critical patent/JPS63130933U/ja
Publication of JPS63130933U publication Critical patent/JPS63130933U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す回路ブロツク
図、第2図は同要部回路図をそれぞれ示す。 6…アツプダウンカウンタ、7…データ比較回
路、USW…アツプスイツチ、DSW…ダウンス
イツチ、5…第1カウンタ、4…プリセツタブル
カウンタ。
FIG. 1 is a circuit block diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram of the main parts thereof. 6... Up-down counter, 7... Data comparison circuit, USW... Up switch, DSW... Down switch, 5... First counter, 4... Presettable counter.

Claims (1)

【実用新案登録請求の範囲】 記録モード及び再生モードに応じて異なるプリ
セツトデータを発生するプリセツトデータ発生回
路と、 所定周期で発生する基準信号によりプリセツト
データをプリセツトしクロツク信号を計数してカ
ウントアツプ出力を発するプリセツタブルカウン
タと、 該カウントアツプ出力を受けて前記クロツク信
号を計数するカウンターと、 操作出力に応じて前記クロツクパルスをカウン
トアツプ又はカウントダウンするアツプダウンカ
ウンタと、 前記カウンタと前記アツプダウンカウンタの計
数値が一致したとき一致出力を発するデータ比較
回路とを、 それぞれ配して成るトラツキング制御回路。
[Claim for Utility Model Registration] A preset data generation circuit that generates different preset data depending on the recording mode and playback mode, and a reference signal that is generated at a predetermined period to preset the preset data and count the clock signals. a presettable counter that generates a count-up output; a counter that receives the count-up output and counts the clock signal; an up-down counter that counts up or counts down the clock pulse according to the operation output; A tracking control circuit consisting of a data comparison circuit that outputs a match output when the count values of down counters match.
JP2049787U 1987-02-13 1987-02-13 Pending JPS63130933U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2049787U JPS63130933U (en) 1987-02-13 1987-02-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2049787U JPS63130933U (en) 1987-02-13 1987-02-13

Publications (1)

Publication Number Publication Date
JPS63130933U true JPS63130933U (en) 1988-08-26

Family

ID=30816065

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2049787U Pending JPS63130933U (en) 1987-02-13 1987-02-13

Country Status (1)

Country Link
JP (1) JPS63130933U (en)

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