JPS63126260A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPS63126260A JPS63126260A JP27224886A JP27224886A JPS63126260A JP S63126260 A JPS63126260 A JP S63126260A JP 27224886 A JP27224886 A JP 27224886A JP 27224886 A JP27224886 A JP 27224886A JP S63126260 A JPS63126260 A JP S63126260A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- layer
- silicon wafer
- type silicon
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 81
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 49
- 229910052710 silicon Inorganic materials 0.000 abstract description 49
- 239000010703 silicon Substances 0.000 abstract description 49
- 239000002184 metal Substances 0.000 abstract description 29
- 229910052751 metal Inorganic materials 0.000 abstract description 29
- 235000012431 wafers Nutrition 0.000 abstract 6
- 230000010354 integration Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 67
- 238000005530 etching Methods 0.000 description 20
- 238000009792 diffusion process Methods 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 12
- 239000012535 impurity Substances 0.000 description 11
- 238000002844 melting Methods 0.000 description 10
- 230000008018 melting Effects 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 238000001947 vapour-phase growth Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005566 electron beam evaporation Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 3
- 238000009499 grossing Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 241001385733 Aesculus indica Species 0.000 description 1
- 241000257465 Echinoidea Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910020968 MoSi2 Inorganic materials 0.000 description 1
- 229910008814 WSi2 Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001017 electron-beam sputter deposition Methods 0.000 description 1
- -1 etc. Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 102200021395 rs3739168 Human genes 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910001258 titanium gold Inorganic materials 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、素子を形成する半導体基板を２段に構成した
半導体集積回路の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit in which semiconductor substrates forming elements are structured in two stages.
モノリシック半導体集積回路は、単一の半導体基板上に
複数の素子が形成されるので、各素子間を電気的に分離
絶縁する必要がある。Since a monolithic semiconductor integrated circuit has a plurality of elements formed on a single semiconductor substrate, it is necessary to electrically isolate and insulate each element.
この分離絶縁を実現するために、従来より、各素子領域
をｐｎ接合で分離し、基板に逆バイアスを印加すること
によりこの各素子領域を浮かせて絶縁するという方法が
あった。In order to achieve this separation and insulation, there has conventionally been a method of separating each element region by a pn junction and applying a reverse bias to the substrate to float and insulate each element region.
また、エツチングや多結晶成長等の手段を用いて多結晶
中に酸化膜等の絶縁物を介した素子領域を埋め込み形成
することにより、各素子を分離絶縁する方法も開発され
ている。Also, a method has been developed for isolating and insulating each element by embedding an element region in polycrystal with an insulator such as an oxide film interposed therebetween using means such as etching or polycrystalline growth.
ところが、ｐｎ接合に逆バイアスを印加する方法の場合
には、ｐｎ接合を設けるために素子形成層が厚くなり、
選択拡散等により各素子領域間に分離層を形成すると、
この分離層の幅が広くなり過ぎる。このため、各素子領
域間の間隙が広くなり、素子の高密度化が図れないとい
う欠点が生じていた。また、このような方法による半導
体集積回路は、各素子領域がそれぞれｐｎ接合によって
分離されているため、このｐｎ接合の障壁容量や漏れ電
流が周波数特性や耐電圧等の電気的緒特性に悪影響を及
ぼすという欠点も生じていた。However, in the case of the method of applying a reverse bias to the pn junction, the element formation layer becomes thicker in order to provide the pn junction.
When a separation layer is formed between each element region by selective diffusion, etc.
This separation layer becomes too wide. For this reason, the gap between each element region becomes wide, resulting in a disadvantage that higher density of elements cannot be achieved. In addition, in semiconductor integrated circuits manufactured by this method, each element region is separated by a pn junction, so the barrier capacitance and leakage current of this pn junction have an adverse effect on electrical characteristics such as frequency characteristics and withstand voltage. It also had the disadvantage of having a negative impact.
また、多結晶中に素子領域を埋め込む方法では、ｐｎ接
合がないので電気的緒特性への悪影響を防止でき、各素
子領域間の間隙も狭めることができるが、なおかつ分離
のための多結晶部分のスペースに無駄があり、特に受動
素子（抵抗等）が大きな面積を要するため、素子の高密
度化の障害になるという欠点があり、このため、チップ
面積が太き（なることから歩留まり低下の原因にもなっ
ていた。In addition, in the method of embedding the element region in polycrystal, since there is no pn junction, it is possible to prevent an adverse effect on the electrical characteristics, and the gap between each element region can be narrowed. This has the disadvantage of wasting space, and in particular, passive elements (resistors, etc.) require a large area, which is an obstacle to increasing the density of elements. It was also the cause.
本発明に係る半導体集積回路の製造方法は、上記問題点
を解決するために、基部半導体の各所定領域に受動素子
をそれぞれ形成する工程と、この基部半導体の受動素子
形成面上に上部半導体を接着する工程と、接着した上部
半導体の各所定領域に能動素子及び必要に応じて受動素
子をそれぞれ形成する工程と、上部半導体の各素子領域
間の間隙を除去し、各素子領域を互いに分離絶縁する工
程とを有することを特徴としている。In order to solve the above problems, the method for manufacturing a semiconductor integrated circuit according to the present invention includes a step of forming passive elements in each predetermined region of a base semiconductor, and forming an upper semiconductor on the passive element forming surface of the base semiconductor. A step of bonding, a step of forming an active element and, if necessary, a passive device in each predetermined region of the bonded upper semiconductor, and a step of removing gaps between each element region of the upper semiconductor to separate and insulate each element region from each other. It is characterized by having a step of.
基部半導体に形成される受動素子は抵抗等である。抵抗
等の受動素子は、半導体上で大きな面積を占めることに
なるが、基部半導体には受動素子のみを設けるので、後
の工程で上段に形成される能動素子等との接続に便利な
ように比較的自由に各素子を配置することができる。こ
れらの受動素子は、基部半導体上での不純物の選択拡散
等の従来からの半導体集積回路の製造工程により形成さ
れ、必要に応じて絶縁膜の形成及び高融点材料による電
極形成によって配線が行われる。The passive element formed in the base semiconductor is a resistor or the like. Passive elements such as resistors occupy a large area on the semiconductor, but since only passive elements are provided on the base semiconductor, they can be easily connected to active elements formed on the upper stage in later steps. Each element can be arranged relatively freely. These passive elements are formed using conventional semiconductor integrated circuit manufacturing processes such as selective diffusion of impurities on a base semiconductor, and wiring is performed by forming an insulating film and electrodes using a high-melting point material as necessary. .
接着は、基部半導体及び上部半導体の接着面にそれぞれ
形成した金属層又は絶縁層を高温で加圧することにより
又はその他の確実な接着手段により行う。基部半導体及
び上部半導体は、必要ある場合は、いずれか又は双方の
接着面に予め絶縁層を形成しておく。Adhesion is performed by pressurizing metal layers or insulating layers formed on the bonding surfaces of the base semiconductor and the upper semiconductor at high temperature, or by other reliable bonding means. If necessary, an insulating layer is previously formed on the bonding surface of either or both of the base semiconductor and the upper semiconductor.
上部半導体に形成される能動素子はトランジスタやダイ
オード等であり、必要に応じて形成される受動素子は抵
抗等である。これらの素子は、上部半導体上での不純物
拡散又はイオン注入、エピタキシャル層の形成、フォト
エツチング技術、選択エツチング技術、絶縁膜の形成及
び電極形成等の従来からの半導体集積回路の製造工程に
よって形成される。この際、各素子領域はｐｎ接合によ
って分離する必要がないので、半導体の厚さは各素子を
形成するために必要な最小限でよい。Active elements formed in the upper semiconductor are transistors, diodes, etc., and passive elements formed as needed are resistors, etc. These elements are formed by conventional semiconductor integrated circuit manufacturing processes such as impurity diffusion or ion implantation on the upper semiconductor, formation of an epitaxial layer, photoetching technology, selective etching technology, formation of an insulating film, and formation of electrodes. Ru. At this time, since each element region does not need to be separated by a pn junction, the thickness of the semiconductor may be the minimum required to form each element.
上部半導体の各素子領域間の除去は、フォトリングラフ
ィ技術を利用した選択エツチング等によって行う。この
半導体の除去は、上部半導体の絶縁層若しくは基部半導
体と上部半導体との間の接着層又は基部半導体の絶縁層
に達するまで行い、上部半導体の各素子領域を電気的に
確実に分離絶縁する。この半導体の除去工程は、一般的
には素子の形成工程の途上で行い、その後に絶縁膜の形
成、電極形成等が行われる。Removal between each element region of the upper semiconductor is performed by selective etching using photolithography technology. This removal of the semiconductor is performed until reaching the insulating layer of the upper semiconductor, the adhesive layer between the base semiconductor and the upper semiconductor, or the insulating layer of the base semiconductor, thereby reliably electrically separating and insulating each element region of the upper semiconductor. This semiconductor removal process is generally performed during the element formation process, followed by the formation of an insulating film, electrode formation, etc.
〔実施例１〕
本発明の一実施例を第１図乃至第５図に基づいて説明す
れば、以下の通りである。[Embodiment 1] An embodiment of the present invention will be described below based on FIGS. 1 to 5.
本実施例は、基部半導体として結晶面が（１００）のｎ
型シリコンウェハ１を用い、また、上部半導体として結
晶面が（１００）のｐ型シリコンウェハ２を用い、さら
に、これらｎ型シリコンウェハ１とｐ型シリコンウェハ
２とを接着する接着層としてＴｉ金属層３及びｐｔ金属
層４を用いた場合を示す。In this example, the crystal plane is (100) n as the base semiconductor.
Furthermore, a p-type silicon wafer 2 with a (100) crystal plane is used as the upper semiconductor, and a Ti metal is used as an adhesive layer to bond the n-type silicon wafer 1 and the p-type silicon wafer 2 together. A case is shown in which layer 3 and pt metal layer 4 are used.
まず、第２図に示すように、ｎ型シリコンウェハ１は、
上面の所定箇所に受動素子としての抵抗を形成後、上面
全面に、絶縁層５を形成し、さらに、Ｔｉ金属層３及び
ｐｔ金属Ｎ４を重ねて形成する。ｐ型シリコンウェハ２
は、下面全面に絶縁層５を形成した後に、Ｔｉ金属層３
及びＰｔ金属層４を重ねて形成する。ｎ型シリコンウェ
ハ１の上に形成する抵抗は、まずｐ型不純物を選択拡散
して抵抗層６を形成し、その上面全面を電極窓を残して
抵抗絶縁膜７で覆い、その上面に所定パターンの抵抗電
極膜８・・・を形成することにより構成される。ｐ型不
純物の選択拡散は、ｎ型シリコンウェハ１の上面全面を
熱酸化又は低温気相成長等によりＳｉｎｇ又はＳｉＮ等
の膜で覆い、フォトエツチング技術、エツチング技術等
により所定箇所に窓を開口し拡散マスクを形成した上で
、ｐ型の不純物を熱拡散等でｎ型シリコンウェハ１の表
層に拡散するものである。この際、後の工程で受ける熱
処理温度等を考慮して拡散条件を定め、最終的に所望の
抵抗値が得られるようにしておく。First, as shown in FIG. 2, an n-type silicon wafer 1 is
After forming a resistor as a passive element at a predetermined location on the upper surface, an insulating layer 5 is formed on the entire upper surface, and a Ti metal layer 3 and a PT metal N4 are further formed in layers. p-type silicon wafer 2
After forming an insulating layer 5 on the entire bottom surface, a Ti metal layer 3 is formed.
and a Pt metal layer 4 are formed in an overlapping manner. To form a resistor on an n-type silicon wafer 1, first, a p-type impurity is selectively diffused to form a resistive layer 6, the entire upper surface of the resistive layer 6 is covered with a resistive insulating film 7 leaving an electrode window, and a predetermined pattern is formed on the upper surface. The resistive electrode film 8 is constructed by forming the resistive electrode film 8 . Selective diffusion of p-type impurities is achieved by covering the entire upper surface of the n-type silicon wafer 1 with a film of Sing or SiN by thermal oxidation or low-temperature vapor phase growth, and opening windows at predetermined locations using photoetching technology, etching technology, etc. After forming a diffusion mask, p-type impurities are diffused into the surface layer of n-type silicon wafer 1 by thermal diffusion or the like. At this time, the diffusion conditions are determined in consideration of the heat treatment temperature, etc. to be applied in a later step, so that the desired resistance value can be finally obtained.
抵抗絶縁膜７は、選択拡散の際の酸化膜等を除去した上
で改めて低温気相成長等で再度酸化膜を形成し、フォト
エ・ノチング技術、エツチング技術等によって所定箇所
に電極窓を開口することにより形成される。抵抗電極膜
８は、低圧ＣＶＤ（Ｃｈｅ−ｍｉｃａｌ Ｖａｐｏｕｒ
Ｄｅｐｏｓｉｔｉｏｎ ）法、スパッタ法、電子ビー
ム蒸着法等によりＭ ｏ ｓ Ｗ ％ Ｗ Ｓ ｉｚ−
、Ｍ 。For the resistive insulating film 7, after removing the oxide film etc. during selective diffusion, an oxide film is formed again by low-temperature vapor phase growth, etc., and electrode windows are opened at predetermined locations by photo-notching technology, etching technology, etc. It is formed by The resistive electrode film 8 is formed by low pressure CVD (Chemical Vapor
Mos W % W S iz- by deposition method, sputtering method, electron beam evaporation method, etc.
,M.
Ｓｉ、、’ｌ’１ｓｉｚ等の高融点の金属膜をｎ型シリ
コンウェハ１上面全面に形成後、フォトエツチング技術
、選択エツチング技術等によって所定のパターンにエツ
チングすることによって形成される。It is formed by forming a metal film with a high melting point such as Si, . .
抵抗電極膜８の形成にこのような高融点材料を用いたの
は、後の熱処理による溶融を防止するためである。この
抵抗層６の抵抗は、両端のコンタクト孔に接続した抵抗
電極膜８・・・によって引き出される。絶縁層５は、５
ｉＯｚ、ＳｘＮ若しくはＡｌ２Ｏ３又はこれらの多層膜
よりｌなり、熱酸化法、低温気相成長法又はスパッタ法
等により形成される。Ｔｉ金属層３及びＰｔ金属層４は
、連続スパッタ法又は電子ビーム連続蒸着法により形成
する。Ｔｉ金属層３は、絶縁層５の酸化膜等に良（馴染
み、Ｔｉ金属Ｎ３とＰｔ金属層４も真空槽内で連続的に
形成されるので、これらの金属層３・４はｎ型シリコン
ウェハ１及びｎ型シリコンウェハ２に強固に接着される
。以上の工程が本発明の構成要素である「基部半導体の
各所定領域に受動素子をそれぞれ形成する工程」に対応
する。The reason why such a high melting point material is used to form the resistive electrode film 8 is to prevent melting during subsequent heat treatment. The resistance of this resistance layer 6 is drawn out by resistance electrode films 8 connected to the contact holes at both ends. The insulating layer 5 is 5
It is made of iOz, SxN, Al2O3, or a multilayer film thereof, and is formed by a thermal oxidation method, a low-temperature vapor phase growth method, a sputtering method, or the like. The Ti metal layer 3 and the Pt metal layer 4 are formed by continuous sputtering or continuous electron beam evaporation. The Ti metal layer 3 is compatible with the oxide film of the insulating layer 5, etc., and since the Ti metal N3 and Pt metal layer 4 are also formed continuously in the vacuum chamber, these metal layers 3 and 4 are made of n-type silicon. It is firmly bonded to the wafer 1 and the n-type silicon wafer 2. The above steps correspond to the "step of forming passive elements in each predetermined region of the base semiconductor" which is a component of the present invention.
次に、このｎ型シリコンウェハ１とｎ型シリコンウェハ
２とは、第３図に示すように、互いのＰｔ金属層４・４
を重ね合わせて、所定の温度と圧力を加えることにより
接着する。通常圧力を加えた金属層が強固に接着を開始
するのは、その金属の融点の４０％〜５０％の温度範囲
である。そして、Ｐｔの場合はこの接着開始温度が８８
０を程度であることから、ここでは８９０℃まで加熱し
て圧力を加える。この場合、Ｔｉとｐｔとは金属反応を
起こしにくいので、Ｔｉ金属層３・３及び接着して一体
化したＰｔ金属層４は安定した状態を保っている。以上
の工程が本発明の構成要素である「基部半導体の受動素
子形成面上に上部半導体を接着する工程」に対応する。Next, as shown in FIG. 3, the n-type silicon wafer 1 and the n-type silicon wafer 2
are placed on top of each other and bonded by applying a predetermined temperature and pressure. Normally, a metal layer to which pressure is applied starts to firmly adhere in a temperature range of 40% to 50% of the melting point of the metal. In the case of Pt, this adhesion starting temperature is 88
Since 0 is a degree, here, the temperature is heated to 890° C. and pressure is applied. In this case, since Ti and pt hardly cause a metal reaction, the Ti metal layers 3, 3 and the Pt metal layer 4, which are bonded and integrated, maintain a stable state. The above steps correspond to the "step of bonding the upper semiconductor onto the passive element forming surface of the base semiconductor" which is a component of the present invention.
上記のようにしてｎ型シリコンウェハ１とｎ型シリコン
ウェハ２とが接着すると、第４図に示すように、ｎ型シ
リコンウェハ２の上面全面を平滑エツチングし、この平
滑されたｎ型シリコンウェハ２の所定位置に能動素子と
してのトランジスタ等を形成する。平滑エツチングを行
う際には、ｎ型シリコンウェハ１の下面全面に保護層を
形成する。保護層は、平滑エツチングの際のエツチング
液からｎ型シリコンウェハ１を保護するためのものであ
り、ＴｉＡｕ、ＣｒＡｕ等の金属２重膜からなる。平滑
エツチングは、取扱いの都合上剛性を持たせるために厚
くスライスされたｎ型シリコンウェハ２を素子形成のた
めの必要最小限の厚さまで削り込む作業である。エツチ
ング液は、ｎ型シリコンウェハ２の（１００）面に対し
て優先エツチングができるＫＯＨ又はＮ ａ ＯＨの水
溶液を使用する。なお、この時、必要に応じてポリシン
グ等を行ってもよい。ｎ型シリコンウェハ１の下面の保
護層は、平滑エツチング終了後に除去する。When the n-type silicon wafer 1 and the n-type silicon wafer 2 are bonded together as described above, the entire upper surface of the n-type silicon wafer 2 is smoothed and etched as shown in FIG. A transistor or the like as an active element is formed at a predetermined position of 2. When smoothing etching is performed, a protective layer is formed on the entire lower surface of the n-type silicon wafer 1. The protective layer is for protecting the n-type silicon wafer 1 from an etching solution during smoothing etching, and is made of a double metal film of TiAu, CrAu, or the like. Smooth etching is an operation in which the n-type silicon wafer 2, which has been sliced thickly in order to provide rigidity for convenience of handling, is ground down to the minimum thickness necessary for forming elements. As the etching solution, a KOH or NaOH aqueous solution that can preferentially etch the (100) plane of the n-type silicon wafer 2 is used. Note that at this time, polishing or the like may be performed as necessary. The protective layer on the lower surface of the n-type silicon wafer 1 is removed after smoothing etching is completed.
上面を平滑にされたｎ型シリコンウェハ２にトランジス
タを形成するには、まず所定位置にｎ型不純物の選択拡
散によりベース層９・９を形成し、このベース層９・９
内にさらにｐ型不純物の選択拡散によりエミツタ層１０
・１０をそれぞれ形成することにより行う。なお、この
トランジスタの形成の際の処理温度はベース層９形成の
時の１０００℃程度の温度が最高となるが、ＴｉＰｔ合
金系が溶解する可能性のある温度は１３００℃程度とな
るので、接着されたＰｔ金属層４が剥がれるようなこと
はなく安定している。また、抵抗層６は、最初の形成時
において、前述したようにこれらの処理温度を受けるこ
とを見込んだ処理をしているため、このときに所望の抵
抗値が得られる。In order to form a transistor on the n-type silicon wafer 2 whose upper surface has been smoothed, base layers 9 and 9 are first formed at predetermined positions by selectively diffusing n-type impurities.
The emitter layer 10 is further formed by selectively diffusing p-type impurities into the
・Perform by forming 10, respectively. Note that the highest processing temperature for forming this transistor is about 1000°C when forming the base layer 9, but since the temperature at which the TiPt alloy system may melt is about 1300°C, the adhesive The coated Pt metal layer 4 does not peel off and is stable. In addition, since the resistance layer 6 is subjected to processing in anticipation of being subjected to these processing temperatures as described above when it is first formed, a desired resistance value can be obtained at this time.
以上の工程が本発明の構成要素である「接着した上部半
導体の各所定領域に能動素子及び必要に応じて受動素子
を形成する工程」の一部に対応する。The above steps correspond to a part of the "step of forming an active element and, if necessary, a passive element in each predetermined region of the bonded upper semiconductor" which is a component of the present invention.
このようにしてｐ型シリコンウェハ２にトランジスタが
形成されると、第５図に示すように、各トランジスタ領
域間のｐ型シリコンウェハ２を除去して、それぞれ島状
のトランジスタ領域１１・１１を形成する。ｐ型シリコ
ンウェハ２の除去はフッ硝酸をエツチング液として、絶
縁層５の除去はフッ酸をエツチング液として、Ｔｉ金属
層３の除去は硫酸をエツチング液として、ｐｔ金属層４
の除去は王水をエツチング液として使用しフォトエツチ
ング技術を利用した選択エツチング等により行う。以上
の工程が本発明の構成要素である「上部半導体の各素子
領域間の間隙を除去し、上部半導体の各素子領域を互い
に分離絶縁する工程」に対応する。Once the transistors are formed on the p-type silicon wafer 2 in this way, as shown in FIG. Form. The p-type silicon wafer 2 was removed using hydrofluoric acid as an etching solution, the insulating layer 5 was removed using hydrofluoric acid as an etching solution, and the Ti metal layer 3 was removed using sulfuric acid as an etching solution.
The removal is carried out by selective etching using photo-etching technology using aqua regia as an etching solution. The above steps correspond to the "step of removing the gaps between the respective element regions of the upper semiconductor and isolating and insulating the respective element regions of the upper semiconductor from each other" which is a component of the present invention.
そして最後に、第１図に示すように、ｎ型シリコンウェ
ハｌに形成した絶縁層５の露出部分及び各トランジスタ
領域１１・１１の上面全面に絶縁膜１２を形成し、この
絶縁膜１２及びｎ型シリコンウェハ１に形成した絶縁層
５の必要箇所に電極窓を開口して、所定パターンの電極
膜１３を形成することにより半導体集積回路を完成する
。絶縁膜１２は、ＳｉＯ□又はＳｉＮ等からなり、熱酸
化法又は低温気相成長法により形成する。電極窓は、フ
ォトエツチング技術、選択エツチング技術等により絶縁
膜１２及び絶縁層５の一部を除去することにより開口す
る。電極膜１３は、／ｌ、 ＭＯｌＷ、ＭｏＳｉ２、Ｗ
Ｓｉ２等の導電体からなり、電子ビーム蒸着法、スパッ
タ法又は低圧プラズマＣＶＤ法等により絶縁膜１２及び
電極窓の上にこの導電体の膜を形成後、フォトエツチン
グ技術を利用して選択エツチングによりこの導電体の膜
を所定パターンにエツチングすることによって形成され
る。以上の工程が本発明の構成要素である「接着した上
部半導体の各所定領域に能動素子及び必要に応じて受動
素子を形成する工程」の一部に対応する。Finally, as shown in FIG. A semiconductor integrated circuit is completed by opening electrode windows at required locations in the insulating layer 5 formed on the mold silicon wafer 1 and forming the electrode film 13 in a predetermined pattern. The insulating film 12 is made of SiO□, SiN, or the like, and is formed by a thermal oxidation method or a low-temperature vapor phase growth method. The electrode window is opened by removing a portion of the insulating film 12 and the insulating layer 5 using a photoetching technique, a selective etching technique, or the like. The electrode film 13 is /l, MOLW, MoSi2, W
A film of this conductor is formed on the insulating film 12 and the electrode window by electron beam evaporation, sputtering, or low-pressure plasma CVD, and then selectively etched using photoetching technology. It is formed by etching this conductor film into a predetermined pattern. The above steps correspond to a part of the "step of forming an active element and, if necessary, a passive element in each predetermined region of the bonded upper semiconductor" which is a component of the present invention.
なお、本実施例では、ｎ型シリコンウェハ１とｐ型シリ
コンウェハ２との接着のためにＴｉ金属層３とＰＬ金属
層４との多重膜を用いたが、ＣｒとＣｕ、、ＣｒとＰｔ
若しくはＴｉとＮｉ等の多重膜、Ｔ ｉＳ １ ％ Ｍ
ｏ Ｓ Ｉ ＳＷ Ｓ Ｉ ＳＣｒ Ｃｏ等の単−合
金膜等を用いることもできる。In this example, a multilayer film of Ti metal layer 3 and PL metal layer 4 was used for bonding n-type silicon wafer 1 and p-type silicon wafer 2, but Cr and Cu, Cr and Pt
Or a multilayer film of Ti and Ni, etc., TiS 1% M
A single alloy film such as o SI SW SI SCr Co or the like may also be used.
〔実施例２〕
本発明の他の実施例を第６図乃至第８図に基づいて説明
すれば、以下の通りである。[Embodiment 2] Another embodiment of the present invention will be described below with reference to FIGS. 6 to 8.
本実施例は、基部半導体として結晶面が（１１１）のｎ
型シリコンウェハ１′を用い、また、上部半導体として
結晶面が（１００）のｐ型シリコンウェハ２を用い、さ
らに、これらｎ型シリコンウェハ１′とｐ型シリコンウ
ェハ２とを接着する接着層として絶縁層５′を用いた場
合を示す。In this example, the crystal plane is (111) n as the base semiconductor.
A p-type silicon wafer 1' is used, and a p-type silicon wafer 2 with a (100) crystal plane is used as the upper semiconductor, and an adhesive layer for bonding these n-type silicon wafer 1' and p-type silicon wafer 2 is used. A case where an insulating layer 5' is used is shown.
まず、第６図に示すように、ｎ型シリコンウェハ１′は
、上面の所定箇所に受動素子としての抵抗を形成し、上
面全面に絶縁層５′を形成する。First, as shown in FIG. 6, an n-type silicon wafer 1' has resistors as passive elements formed at predetermined locations on the upper surface, and an insulating layer 5' formed over the entire upper surface.
ｐ型シリコンウェハ２は、下面全面に、ｎ”ｔｌ込層１
４を形成し、さらに絶縁層５′を形成する。The p-type silicon wafer 2 has an n''tl layer 1 on the entire bottom surface.
4 is formed, and an insulating layer 5' is further formed.
ｎ型シリコンウェハ１′の上面に形成する抵抗は、まず
ｐ型不純物を選択拡散して抵抗層６を形成し、その上面
全面を電極窓を残して抵抗絶縁膜７で覆い、その上面に
所定パターンの抵抗電極膜８・・・を形成することによ
り構成される。この際、後の工程で受ける熱処理温度等
を考慮して拡散条件を定め、最終的に所望の抵抗値が得
られるようにしておく。抵抗電極Ｊｌ！８は、低圧ＣＶ
Ｄ法、スパッタ法、電子ビーム蒸着法等によりＭＯｌＷ
、ＷＳｉ２、Ｍｏ５ｉｚ、Ｔｉ５ｉｚ等の高融点材料の
金属膜を、ｎ型シリコンウェハ１′上面全面に形成後、
フォトエツチング技術、選択エツチング技術により所定
のパターンにエツチングすることによって形成される。To form a resistor on the upper surface of the n-type silicon wafer 1', first, p-type impurities are selectively diffused to form a resistive layer 6, and the entire upper surface is covered with a resistive insulating film 7 leaving an electrode window. It is constructed by forming a resistive electrode film 8 in a pattern. At this time, the diffusion conditions are determined in consideration of the heat treatment temperature, etc. to be applied in a later step, so that the desired resistance value can be finally obtained. Resistance electrode Jl! 8 is low pressure CV
MOLW by D method, sputtering method, electron beam evaporation method, etc.
After forming a metal film of a high melting point material such as , WSi2, Mo5iz, Ti5iz, etc. on the entire upper surface of the n-type silicon wafer 1',
It is formed by etching into a predetermined pattern using photo-etching technology or selective etching technology.
この抵抗層６の抵抗は、両端のコンタクト孔に接続した
抵抗電極膜８・・・によって引き出される。ｎ＋埋込層
１４は、ｐ型シリコンウェハ２の下面全面にｎ型不純物
を拡散することにより形成される。絶縁層５′は、Ｓｔ
Ｏ□よりなり、熱酸化法、低温気相成長法等により形成
される。この絶縁層５′には、形成時に同時にＰ２０Ｓ
及びＢ２Ｏ３をドープする。ノンドープのＳｉｎ。The resistance of this resistance layer 6 is drawn out by resistance electrode films 8 connected to the contact holes at both ends. The n+ buried layer 14 is formed by diffusing n-type impurities over the entire lower surface of the p-type silicon wafer 2. The insulating layer 5' is St
It is made of O□ and is formed by thermal oxidation method, low temperature vapor phase growth method, etc. This insulating layer 5' is made of P20S at the same time as it is formed.
and doping with B2O3. Non-doped Sin.
膜の融点は１７００°Ｃ程度であるが、ＰｚＯｓが１０
％ドープされると融点は１０００℃程度となり、これに
加えてＢ２０１等がドープされると融点はさらに低下す
る。従って、絶縁層５′には、少なくとも表面層が１１
００℃程度で溶解するようにＰ２Ｏ，及びＢｚ ０３を
ドープしておく。以上の工程が本発明の構成要素である
「基部半導体の各所定領域に受動素子をそれぞれ形成す
る工程」に対応する。The melting point of the film is about 1700°C, but when PzOs is 10
% doping, the melting point will be about 1000° C., and if B201 or the like is additionally doped, the melting point will further decrease. Therefore, the insulating layer 5' has at least a surface layer of 11
P2O and Bz 03 are doped so as to melt at about 00°C. The above steps correspond to the "step of forming passive elements in each predetermined region of the base semiconductor" which is a component of the present invention.
次に、このｎ型シリコンウェハ１′とｐ型シリコンウェ
ハ２とを、第７図に示すように、互いの絶縁層５′ ・
５′を重ね合わせて、所定の温度と圧力を加えることに
より接着する。この際、絶縁層５′ ・５′には圧力を
加えるので、５ｉ０２が溶解する１１００℃より低い１
０００℃以下の温度で接着を行う。以上の工程が本発明
の構成要素である「基部半導体の受動素子形成面上に上
部半導体を接着する工程」に対応する。Next, as shown in FIG.
5' are overlapped and bonded by applying a predetermined temperature and pressure. At this time, since pressure is applied to the insulating layers 5' and 5', the temperature is lower than 1100°C at which 5i02 melts.
Adhesion is carried out at a temperature of 000°C or less. The above steps correspond to the "step of bonding the upper semiconductor onto the passive element forming surface of the base semiconductor" which is a component of the present invention.
上記のようにしてｎ型シリコンウェハ１′とｐ型シリコ
ンウェハ２とが接着すると、同じく第７図に示すように
、実施例１と同じ手順でｐ型シリコンウェハ２の上面全
面を平滑エツチングし、この平滑されたｐ型シリコンウ
ェハ２の所定値’ｔに能動素子としてのトランジスタ等
を形成する。上面を平滑されたｐ型シリコンウェハ２に
トランジスタを形成するには、まず所定位置にｎ型不純
物の選択拡散によりベースＮ９・９を形成し、このベー
ス層９・９内にさらにｐ型不純物の選択拡散によりエミ
ツタ層１０・１０をそれぞれ形成することにより行う。After the n-type silicon wafer 1' and the p-type silicon wafer 2 are bonded together as described above, the entire top surface of the p-type silicon wafer 2 is etched to smooth it in the same manner as in Example 1, as shown in FIG. , transistors and the like as active elements are formed on the smoothed p-type silicon wafer 2 at a predetermined value 't. To form a transistor on a p-type silicon wafer 2 whose top surface has been smoothed, a base N9.9 is first formed at a predetermined position by selective diffusion of n-type impurities, and then a p-type impurity is further added to the base layer 9.9. This is done by forming the emitter layers 10, 10, respectively, by selective diffusion.
なお、このトランジスタの形成の際の処理温度はベース
層９形成の時の１０００°Ｃ程度の温度が最高となるが
、５ｉｎ２からなる絶縁層５′の溶解温度は１１００℃
程度となるので、接着された一体化した絶縁層５′が剥
がれるようなことはなく安定している。また、抵抗層６
も、これらの温度処理が行われることを計算に入れて拡
散条件が設定されているので、これらの工程終了後に所
定の抵抗値を呈するようになっている。以上の工程が本
発明の構成要素である［接着した上部半導体の各所定領
域に能動素子及び必要に応じて受動素子を形成する工程
」に対応する。Note that the highest processing temperature during the formation of this transistor is about 1000°C when forming the base layer 9, but the melting temperature of the insulating layer 5' consisting of 5in2 is 1100°C.
Since the bonded and integrated insulating layer 5' is not peeled off, it is stable. In addition, the resistance layer 6
However, since the diffusion conditions are set taking into consideration that these temperature treatments will be carried out, a predetermined resistance value is exhibited after these steps are completed. The above steps correspond to the component of the present invention, which is the step of forming an active element and, if necessary, a passive element in each predetermined region of the bonded upper semiconductor.
このようにしてｐ型シリコンウェハ２にトランジスタが
形成されると、第８図に示すように、各トランジスタ領
域間のｐ型シリコンウェハ２をｎ＋埋込Ｊｉ１４まで除
去して、それぞれ島状のトランジスタ領域１１・１１を
形成するとともに、絶縁層５′の露出部分及びこの各ト
ランジスタ領域１１・１１の上面全面に絶縁膜１２を形
成し、この絶縁膜１２及び絶縁層５′の必要箇所に電極
窓を開口して、所定パターンの電極膜１３を形成するこ
とにより半導体集積回路を完成する。以上の工程が本発
明の構成要素である「上部半導体の各素子領域間の間隙
を除去し、上部半導体の各素子領域を互いに分離絶縁す
る工程」に対応する。When transistors are formed on the p-type silicon wafer 2 in this way, as shown in FIG. At the same time as forming the regions 11, 11, an insulating film 12 is formed on the exposed portion of the insulating layer 5' and the entire upper surface of each transistor region 11, 11, and electrode windows are formed at necessary locations on the insulating film 12 and the insulating layer 5'. A semiconductor integrated circuit is completed by opening the electrode film 13 in a predetermined pattern. The above steps correspond to the "step of removing the gaps between the element regions of the upper semiconductor and isolating the element regions of the upper semiconductor from each other" which is a component of the present invention.
なお、実施例１及び実施例２では、ｎ型シリコンウニハ
ト１′に形成する抵抗に抵抗電極膜８を形成する場合を
示したが、設計上不要な場合もあり必ずしも形成しなけ
ればならないものではない。また、実施例２では、トラ
ンジスタの特性向上のためｐ型シリコンウェハ２の下面
にｎ＋埋込層１４を設けた場合を示しているが、実施例
１のｐ型シリコンウェハ２にも同様のｎ１埋込層を設け
ることができる。さらに、実施例１及び実施例２では、
基部半導体及び上部半導体としてシリコンウェハを用い
た場合を示したが、これに限らず例えばＧａＡｓ又はｒ
ｎＰ等のＩＩＩ−Ｖ族半導体、その他の半導体を使用す
ることもできる。また、実施例１及び実施例２では、バ
イポーラＩＣについて説明したが、Ｃ−ＭＯＳ−ＩＣ等
のようなユニポーラＩＣ，その他のデバイスへの実施も
同様に可能である。In addition, in Examples 1 and 2, a case was shown in which a resistive electrode film 8 was formed on the resistor formed on the n-type silicon urchin 1', but it may not be necessary due to the design and may not necessarily be formed. isn't it. Further, in Example 2, a case is shown in which an n+ buried layer 14 is provided on the lower surface of the p-type silicon wafer 2 in order to improve the characteristics of the transistor, but the p-type silicon wafer 2 of Example 1 also has a similar n+ buried layer 14. A buried layer can be provided. Furthermore, in Example 1 and Example 2,
Although the case where a silicon wafer is used as the base semiconductor and the upper semiconductor is shown, the present invention is not limited to this, and for example, GaAs or r
Group III-V semiconductors such as nP and other semiconductors can also be used. Further, in the first and second embodiments, a bipolar IC has been described, but it is also possible to implement the present invention in a unipolar IC such as a C-MOS-IC or other devices.
本発明に係る半導体集積回路の製造方法は、以上のよう
に、基部半導体の各所定領域に受動素子をそれぞれ形成
する工程と、この基部半導体の受動素子形成面上に上部
半導体を接着する工程と、接着した上部半導体の各所定
領域に能動素子及び必要に応じて受動素子をそれぞれ形
成する工程と、上部半導体の各素子領域間の間隙を除去
し、各素子領域を互いに分離絶縁する工程とを有する構
成である。As described above, the method for manufacturing a semiconductor integrated circuit according to the present invention includes the steps of forming passive elements in each predetermined region of the base semiconductor, and bonding the upper semiconductor onto the passive element forming surface of the base semiconductor. , forming an active element and, if necessary, a passive element in each predetermined region of the bonded upper semiconductor; and a step of removing gaps between each element region of the upper semiconductor and isolating and insulating each element region from each other. This is a configuration that has
これにより、上部半導体の各素子領域は、間隙の半導体
が除去されて分離絶縁されるのでｐｎ接合を設ける必要
がなくなり、各素子領域間の間隔を狭めるとともに、電
気的緒特性に対する悪影Ｃを受けることもな（なる。As a result, each element region of the upper semiconductor is separated and insulated by removing the semiconductor in the gap, so there is no need to provide a pn junction, which reduces the distance between each element region and reduces the negative effect C on electrical characteristics. I won't even receive it (naru).
また、特に大きな面積を要する受動素子をできるだけ基
部半導体に形成し、上部半導体には主に能動素子を形成
するので、大幅な素子の高密度化が可能となり、しかも
、チップ面積が小さくなるため半導体集積回路の歩留ま
りの向上を図ることができるばかりでな（、受動素子の
位置や形状の制限が緩和され設計が容易になるという効
果を奏する。In addition, passive elements that require a particularly large area are formed in the base semiconductor as much as possible, and active elements are mainly formed in the upper semiconductor, making it possible to significantly increase the density of elements. This not only improves the yield of integrated circuits, but also eases restrictions on the position and shape of passive elements, making design easier.
第１図乃至第５図は本発明の一実施例を示すものであっ
て、第１図は半導体集積回路の縦断面部分正面図、第２
図乃至第５図は半導体集積回路の製造過程を示す縦断面
部分正面図、第６図乃至第８図は本発明の他の実施例を
示すものであり、第６図は半導体集積回路の縦断面部分
正面図、第７図及び第８図は半導体集積回路の製造過程
を示す縦断面部分正面図である。
ｌ・１′はｎ型シリコンウェハ（基部半導体）、２はｎ
型シリコンウェハ（上部半導体）、３はＴｉ金属層、４
はｐｔ金属層、５′は絶縁層、６は抵抗層、１１はトラ
ンジスタ領域である。
特許出願人 シャープ 株式会社第１図
′＄２図
第３図
第４図1 to 5 show one embodiment of the present invention, in which FIG. 1 is a vertical cross-sectional partial front view of a semiconductor integrated circuit, and FIG.
5 to 5 are vertical cross-sectional partial front views showing the manufacturing process of a semiconductor integrated circuit, FIGS. 6 to 8 show other embodiments of the present invention, and FIG. 6 is a longitudinal cross-sectional view of the semiconductor integrated circuit. 7 and 8 are vertical cross-sectional partial front views showing the manufacturing process of a semiconductor integrated circuit. l・1' is n-type silicon wafer (base semiconductor), 2 is n
type silicon wafer (upper semiconductor), 3 is Ti metal layer, 4
is a PT metal layer, 5' is an insulating layer, 6 is a resistance layer, and 11 is a transistor region. Patent applicant Sharp Co., Ltd. Figure 1'$2 Figure 3 Figure 4
Claims (1)
する工程と、この基部半導体の受動素子形成面上に上部
半導体を接着する工程と、接着した上部半導体の各所定
領域に能動素子及び必要に応じて受動素子をそれぞれ形
成する工程と、上部半導体の各素子領域間の間隙を除去
し、各素子領域を互いに分離絶縁する工程とを有するこ
とを特徴とする半導体集積回路の製造方法。1. A process of forming passive elements in each predetermined region of the base semiconductor, a process of bonding an upper semiconductor on the passive element forming surface of the base semiconductor, and a step of forming an active element and as necessary in each predetermined region of the bonded upper semiconductor. 1. A method of manufacturing a semiconductor integrated circuit, comprising the steps of forming passive elements accordingly, and removing gaps between each element region of an upper semiconductor to isolate and insulate each element region from each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27224886A JPS63126260A (en) | 1986-11-14 | 1986-11-14 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27224886A JPS63126260A (en) | 1986-11-14 | 1986-11-14 | Manufacture of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63126260A true JPS63126260A (en) | 1988-05-30 |
Family
ID=17511197
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27224886A Pending JPS63126260A (en) | 1986-11-14 | 1986-11-14 | Manufacture of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63126260A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8471377B2 (en) | 2010-08-09 | 2013-06-25 | Mitsubishi Electric Corporation | Semiconductor device and semiconductor circuit substrate |
-
1986
- 1986-11-14 JP JP27224886A patent/JPS63126260A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8471377B2 (en) | 2010-08-09 | 2013-06-25 | Mitsubishi Electric Corporation | Semiconductor device and semiconductor circuit substrate |
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