JPS63125681A - Thin film forming device - Google Patents
Thin film forming deviceInfo
- Publication number
- JPS63125681A JPS63125681A JP26910686A JP26910686A JPS63125681A JP S63125681 A JPS63125681 A JP S63125681A JP 26910686 A JP26910686 A JP 26910686A JP 26910686 A JP26910686 A JP 26910686A JP S63125681 A JPS63125681 A JP S63125681A
- Authority
- JP
- Japan
- Prior art keywords
- heat treatment
- chamber
- treatment chamber
- thin film
- reaction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 26
- 238000010438 heat treatment Methods 0.000 claims abstract description 50
- 239000004065 semiconductor Substances 0.000 claims abstract description 49
- 238000006243 chemical reaction Methods 0.000 claims abstract description 46
- 239000010408 film Substances 0.000 claims abstract description 28
- 229910021332 silicide Inorganic materials 0.000 claims description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 238000002844 melting Methods 0.000 claims description 5
- 230000008018 melting Effects 0.000 claims description 4
- 239000012808 vapor phase Substances 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 abstract description 52
- 230000015572 biosynthetic process Effects 0.000 abstract description 10
- 238000001947 vapour-phase growth Methods 0.000 description 20
- 239000007789 gas Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 17
- 238000010586 diagram Methods 0.000 description 8
- 239000010453 quartz Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000000428 dust Substances 0.000 description 5
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 5
- 239000011261 inert gas Substances 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012495 reaction gas Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- 229910008814 WSi2 Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Landscapes
- Chemical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置の製造工程で利用される気相成長法
により薄膜を形成する薄膜形成装置に係り、特にゲート
電極等の配線材料に用いられる高融点金属のシリサイド
膜を形成する薄膜形成装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a thin film forming apparatus for forming thin films by a vapor phase growth method used in the manufacturing process of semiconductor devices, and particularly relates to a thin film forming apparatus for forming thin films by a vapor phase growth method used in the manufacturing process of semiconductor devices. The present invention relates to a thin film forming apparatus for forming a silicide film of a melting point metal.
従来の技術
近年、半導体デバイスの高集積化に伴ない高速応答性が
強く要求さＪするようになり、ゲート電極や配線材料に
抵抗の低い材＃１の開発が進められている。とれ１で主
に用いられてきたゲート電極は多結晶シリコン（Ｐｏｌ
ｙＳｉ ）にリン（Ｐ）等をドープしたものであった。BACKGROUND OF THE INVENTION In recent years, as semiconductor devices have become highly integrated, there has been a strong demand for high-speed response, and the development of material #1 with low resistance for gate electrodes and wiring materials is underway. The gate electrode that has been mainly used in Tore 1 is polycrystalline silicon (Pol).
ySi) doped with phosphorus (P) or the like.
リンをドープした多結晶シリコン（以下、Ｐ −ｄｏｐ
ｅｄ Ｐｏ１ｙ Ｓｉ と記す。）は４０００〜５０
００人の薄厚で２０〜３０Ω７４コのシ−ト抵抗を有し
ている。シート抵抗を下げる方法の一つは、高融点金属
、或いは該金属のシリサイドを用いることで、タングス
テンシリサイド（ＷＳ ｉ ） 。Polycrystalline silicon doped with phosphorus (hereinafter referred to as P-dop)
It is written as edPolySi. ) is 4000-50
It has a sheet resistance of 20 to 30Ω74 with a thin thickness of 0.00Ω. One way to lower the sheet resistance is to use a high melting point metal or a silicide of the metal, such as tungsten silicide (WS i ).
モリブデンシリサイド（ＭｏＳｉ）をゲート電極に採用
するとＰ−ｄｏｐｅｄ Ｐｏ１ｙ Ｓｔに比較してシー
ト抵抗を約１桁低くできる。実際の半導体デバイスにお
いては、下地との密着性、安定性等の面からシリサイド
膜と多結晶シリコン膜の２層構造（ポリサイド構造）に
するのが一般に行なわれている。When molybdenum silicide (MoSi) is used for the gate electrode, the sheet resistance can be lowered by about one order of magnitude compared to P-doped PolySt. In actual semiconductor devices, a two-layer structure (polycide structure) of a silicide film and a polycrystalline silicon film is generally used from the viewpoint of adhesion with the underlying layer and stability.
次に、ゲート電極材料にＷ Ｓ １２を用いたプロセス
について説明する。第３図にＷ Ｓ １２のゲート形成
法の一例を示す。初めにＰｏ１ｙ Ｓ’ｉ膜を気相成長
法により堆積させる。第４図に一般に使用されている気
相成長装置の概略図を示す。石英チューブでできた反応
管１の中に石英ボート２に多数枚並べた半導体ウェハ３
を投入して０．１〜ＩＴｏｒｒの減圧下でモノシランガ
ス（Ｓ １Ｈ４）をガス導入口４から流しながら、反応
管１の周囲に設けた抵抗加熱ヒータ５で６００〜６５０
℃に加熱して成長させる。Next, a process using W S 12 as the gate electrode material will be described. FIG. 3 shows an example of a method for forming the gate of W S 12. First, a Po1yS'i film is deposited by vapor phase growth. FIG. 4 shows a schematic diagram of a commonly used vapor phase growth apparatus. A large number of semiconductor wafers 3 are arranged in a quartz boat 2 in a reaction tube 1 made of a quartz tube.
While flowing monosilane gas (S1H4) from the gas inlet 4 under a reduced pressure of 0.1 to ITorr, the resistance heater 5 installed around the reaction tube 1 was used to heat the reaction tube to 600 to 650
Grow by heating to ℃.
次に拡散炉（上記の気相成長装置と類似した反応管を有
する）に半導体ウェハを移してホスフィン（ＰＨ３）と
酸素（ｏ２）を常圧下で流しながら約１０００℃で処理
する。これによりＰ −ｄｏｐｅｄＰｏｌｙ Ｓｔ
が形成される。しかしながら同時にＰ −ｄｏｐｅｄ
Ｐｏ１ｙ Ｓｔ膜表面酸化されるため、この後フッ酸等
のエツチング液により表面の酸化膜を除去する工程が必
要となる。表面の酸化膜をエツチング除去したのち、Ｐ
−ｄｏｐｅｄ Ｐｏ１ｙ Ｓｉ上にＷＳ ｘ ２ （
もしくはＷ）を形成する。Next, the semiconductor wafer is transferred to a diffusion furnace (having a reaction tube similar to the above-mentioned vapor phase growth apparatus) and treated at about 1000° C. while flowing phosphine (PH3) and oxygen (O2) under normal pressure. This allows P-dopedPoly St
is formed. However, at the same time P-doped
Since the surface of the PolySt film is oxidized, a subsequent step is required to remove the oxide film on the surface using an etching solution such as hydrofluoric acid. After removing the oxide film on the surface by etching, P
-WS x 2 (
Or form W).
高融点金属を半導体ウェハ上に形成する方法には、スパ
ッタ、蒸着、気相成長法などがあるが、気相成長法はス
パッタ、蒸着法に比べてステップカバレージおよび純度
等の点で優れている。この気相成長法によるＷＳ １２
（あるいはＷ）の形成には、特開昭５９−１７９７７
５号公報に示されるような気相成長装置が使用されてい
る。第５図にその装置の概略図を示す。Methods for forming high-melting point metals on semiconductor wafers include sputtering, vapor deposition, and vapor phase growth, but vapor phase growth is superior to sputtering and vapor deposition in terms of step coverage and purity. . WS 12 produced by this vapor phase growth method
(or W), JP-A-59-17977
A vapor phase growth apparatus as shown in Publication No. 5 is used. FIG. 5 shows a schematic diagram of the device.
ＷＳ １２は六フッ化タングステン（ＷＦ６）とＳ Ｉ
Ｈ４の化学反応により形成される。WS 12 is made of tungsten hexafluoride (WF6) and S I
Formed by a chemical reaction of H4.
ＷＦ ｅ ＋ ２ Ｓ Ｉ Ｈ４ＷＳ １２ ＋６ＨＦ
＋Ｈ２第２図において、半導体ウェハ６は多面体を形
成している試料台７に載置され、ＷＦ６及びＳ ｚ Ｈ
４ガスがキャリアガスとともにガス供給管８を通して導
入され、ＷＳ １２膜が生成されるものである。WF e + 2 SI H4WS 12 +6HF
+H2 In FIG. 2, the semiconductor wafer 6 is placed on a sample stage 7 forming a polyhedron, and WF6 and S z H
4 gas is introduced through the gas supply pipe 8 together with the carrier gas, and a WS 12 film is produced.
上記の如く薄膜を堆積した後、低抵抗化（あるいはシリ
サイド化）のだめに熱処理をほどこす。After depositing the thin film as described above, heat treatment is performed to lower the resistance (or to make it into a silicide).
通常、熱処理は拡散炉と同様チューブ状の石英管内に半
導体ウェハを置き、不活性ガス雰囲気下１０００℃付近
で３０分程度行なわれる。Usually, the heat treatment is performed by placing the semiconductor wafer in a tubular quartz tube similar to a diffusion furnace, and performing the heat treatment at around 1000° C. in an inert gas atmosphere for about 30 minutes.
発明が解決しようとする問題点
以トの説明の如く、シリサイドのゲート電極形成は、工
程が複錐であり、また各工程間を移送させる際半導体ウ
ェハへのダストの付着あるいは薄膜表面の酸化等が問題
になっている。さらにＰ −ｄｏｐｅｄ Ｐｏ１ｙ Ｓ
ｉ膜の形成においては拡散炉如おけるＰのドープがＰｏ
１ｙ Ｓｔ の粒径の増大を招き、後工程でのＷＳ
ｉ 形成に悪影響を及ぼすことが示唆されている。そ
こで、これらの問題を解決する一つの手段として、Ｐｏ
１ｙ Ｓｉ の堆積と同時にＰをドープするＰ −ｄ
ｏｐｅｄ Ｐｏ１ｙ Ｓｉの気相成長６ ・＼ 。Problems to be Solved by the Invention As explained below, the process of forming a silicide gate electrode is a multi-cone process, and when the wafer is transferred between processes, dust may adhere to the semiconductor wafer, oxidation of the thin film surface, etc. has become a problem. Furthermore, P-doped Po1y S
In the formation of the i-film, P doping in a diffusion furnace is
This leads to an increase in the particle size of 1ySt, and WS in the subsequent process
i has been suggested to have a negative effect on formation. Therefore, as a means to solve these problems, Po
1y P-d doped with P simultaneously with Si deposition
Vapor phase growth of oped PolySi 6 ・＼.
が提唱されている。また、シリサイド膜の低抵抗化を図
る熱処理においても、従来抵抗加熱により比較的長時間
貸なっていた方法から赤外線ランプを加熱源とする高速
熱処理（ラピッド・サーマル・アニール）も行なわれて
いる。has been proposed. Furthermore, in heat treatment to lower the resistance of silicide films, the conventional method of resistive heating, which lasted for a relatively long time, has been replaced by rapid thermal annealing, which uses an infrared lamp as a heat source.
しかしながら、上記の各工程を別々の装置で行なう限り
、ダスト付着あるいは膜表面の酸化は避けることのでき
ない問題である。このような問題を解消するには、外気
にふれさせずに１台の装置でシリサイド膜形成を連続的
に行なうのが最も効果的な方法である。しかし、この方
法を実現するには気相成長及び熱処理を行なう各処理室
間の被処理体すなわち半導体ウェハの移送手段をどうす
るか５丑だ各処理室で使用するガスの他の室への流出あ
るいはダストの舞い上りをどのようにして防止するかが
問題である。However, as long as each of the above steps is performed using separate apparatuses, dust adhesion and oxidation of the film surface are unavoidable problems. To solve this problem, the most effective method is to continuously form a silicide film using one device without exposing it to the outside air. However, in order to realize this method, it is necessary to decide how to transport the object to be processed, that is, the semiconductor wafer, between the processing chambers where vapor phase growth and heat treatment are performed. Another problem is how to prevent dust from flying up.
本発明は上記問題点に鑑み、品質の優れたシリサイド膜
を効率よく形成する薄膜形成装置を提供するものである
。In view of the above problems, the present invention provides a thin film forming apparatus that can efficiently form a silicide film of excellent quality.
問題点を解決するだめの手段
７〜−
上記問題点を解決するために本発明の薄膜形成装置は、
多結晶シリコン及び高融点金属（あるいは高融点金属の
シリサイド）膜の気相成長を行彦う反応室と熱処理室と
を具備し、各室を半導体ウェハを移送する搬送手段を備
えた中間室で接続するとともに、好ましくは中間室の圧
力を他の室の圧力より低く構成したものである。Means for Solving the Problems 7-- In order to solve the above problems, the thin film forming apparatus of the present invention includes:
Equipped with a reaction chamber and a heat treatment chamber for vapor phase growth of polycrystalline silicon and refractory metal (or refractory metal silicide) films, each chamber is connected by an intermediate chamber equipped with a transport means for transporting semiconductor wafers. At the same time, preferably the pressure in the intermediate chamber is lower than the pressure in the other chambers.
作 用
本発明は上記したように反応室及び熱処理室を半導体ウ
ェハの搬送手段を備えた中間室により連結することでシ
リサイド膜を大気にふれることなく形成でき、しかも、
中間室の圧力を反応室及び熱処理室の圧力を低くするこ
とにより、反応室及び熱処理室への不要なガスの流れ込
み及びダストの混入を防止でき、品質の優れたシリサイ
ド膜を形成できるものである。さらに中間室に接したゲ
ートバルブを反応室あるいは熱処理室側の壁面に密着さ
せる構成にすることにより中間室の圧力を低げた場合、
気密性が増し効果は犬なるものになる０
実施例
以下本発明の一実施例の薄膜形成装置について、図面を
参照しながら説明する。Function: As described above, the present invention connects the reaction chamber and the heat treatment chamber through an intermediate chamber equipped with a means for transporting a semiconductor wafer, thereby making it possible to form a silicide film without exposing it to the atmosphere.
By lowering the pressure in the intermediate chamber and the pressure in the reaction chamber and heat treatment chamber, it is possible to prevent unnecessary gas from flowing into the reaction chamber and heat treatment chamber and the incorporation of dust, and it is possible to form a silicide film of excellent quality. . Furthermore, if the pressure in the intermediate chamber is lowered by configuring the gate valve in contact with the intermediate chamber to be in close contact with the wall on the reaction chamber or heat treatment chamber side,
The airtightness is increased and the effect becomes even more impressive.Example Hereinafter, a thin film forming apparatus according to an example of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の薄膜形成装置の概略図であ
り、第２図は同薄膜形成装置の断面概略図を示すもので
ある。FIG. 1 is a schematic diagram of a thin film forming apparatus according to an embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view of the same thin film forming apparatus.
熱処理室９は反応室１０−１及び１ｏ−２と中間室１１
−１及び１１−２とを介して連結されており、前記熱処
理室９の内部には半導体ウェハを載置する石英製テーブ
ル１２が設けている。前記テーブル１２の外径は半導体
ウェハの外径より小さくなっており、上下に移動できる
ようにしている。熱処理室９の土壁は石英板１３で構成
され、その上方には加熱用の赤外線ランプ１４が設けで
ある。熱処理室９の中間室に接しない側壁の一方にはゲ
ートバルブ１５−１があり、ゲートバルブ１５−１の対
面する位置に設けた搬送用のアーム１６−３により前記
ゲー！・バルブ１５−１を通過して半導体ウェハの出し
入れを行なう。さらに熱処理室９の外部前方には半導体
ウェハを収納する９ １、−
２個のカセット１７−１．１７−２と２個のカセットの
間を半導体ウェハをウェハ載置台１８を経由して搬送す
る搬送ベルト１９がある。一方のカセット１７−１から
搬送された薄膜形成前の半導体ウェハはウェハ載置台１
８に−ｌ置かれ、アーム１６−３により熱処理室９に投
入するように構成している。２つの中間室１１−１．１
１−２は内部にそれぞれウェハ搬送用のアーム１６−１
、１６−２を備えており、反応室１０−１及び１０−
２と熱処理室９とに接する側壁にはそれぞれゲートバル
ブ１５−２，１１５−３及び１５−４ 、１５−６が設
けてあり、ゲートバルブ１５−２〜１５−６はシリンダ
（図示せず）により反応室１０−１．１０−２あるいは
熱処理室９の側壁に密着開閉するよう構成さノ１ている
。２つの反応室１０−１ 、１０−２には反応ガスを供
給するガス供給口２０−１．２０−２と真空ポンプ２１
−１に接続して反応済のガスを排出するガス排気１］２
２−１．２２−２が設けてあり、内部には加熱用のヒー
タ（図示せず）を具備したサセプタ２３−１．２３−２
を設けである。前１ｏ ぺ−２
記サセプタ２３−１．２３−２の中央には半導体ウェハ
の搬送をアームにより可能にするための突き上げピン２
４−１，２４−２が備えである。なお、を有し、熱処理
室９には減圧操作ならびに常圧復帰を行なうため真空ポ
ンプ２１−２に連結したガス排気口２６及びガス供給口
２７を有している。The heat treatment chamber 9 includes reaction chambers 10-1 and 1o-2 and an intermediate chamber 11.
-1 and 11-2, and a quartz table 12 on which a semiconductor wafer is placed is provided inside the heat treatment chamber 9. The outer diameter of the table 12 is smaller than the outer diameter of the semiconductor wafer, so that it can be moved up and down. The earthen wall of the heat treatment chamber 9 is made of a quartz plate 13, and an infrared lamp 14 for heating is provided above it. There is a gate valve 15-1 on one side wall of the heat treatment chamber 9 that is not in contact with the intermediate chamber, and a transfer arm 16-3 provided at a position facing the gate valve 15-1 is used to transport the gas! - Semiconductor wafers are taken in and out through the valve 15-1. Furthermore, at the outside front of the heat treatment chamber 9, there are two cassettes 17-1 and 17-2 for storing semiconductor wafers, and the semiconductor wafers are transported via a wafer mounting table 18 between the two cassettes 17-1 and 17-2. There is a conveyor belt 19. The semiconductor wafer before thin film formation transferred from one cassette 17-1 is placed on the wafer mounting table 1.
8, and is configured to be introduced into the heat treatment chamber 9 by an arm 16-3. Two intermediate chambers 11-1.1
1-2 is an arm 16-1 for wafer transfer inside.
, 16-2, reaction chambers 10-1 and 10-
2 and the heat treatment chamber 9 are provided with gate valves 15-2, 115-3, 15-4, and 15-6, respectively, and the gate valves 15-2 to 15-6 are connected to cylinders (not shown). It is configured to open and close in close contact with the side wall of the reaction chamber 10-1, 10-2 or the heat treatment chamber 9. The two reaction chambers 10-1 and 10-2 are provided with gas supply ports 20-1 and 20-2 for supplying reaction gas and a vacuum pump 21.
-1 to exhaust the reacted gas 1]2
2-1.22-2 is provided, and a susceptor 23-1.23-2 is provided with a heater (not shown) for heating inside.
This is provided. Front 1 o Page 2 In the center of the susceptor 23-1, 23-2, there is a push-up pin 2 to enable the arm to transport the semiconductor wafer.
4-1 and 24-2 are preparations. The heat treatment chamber 9 has a gas exhaust port 26 and a gas supply port 27 connected to a vacuum pump 21-2 for performing depressurization operations and return to normal pressure.
なお、前記アームはそれぞれ腕を２本有しその先端は石
英でできたＵ字形をしており、半導体ウェハの裏面周囲
を支持するように構成しである。Each of the arms has two arms, the tips of which are U-shaped and made of quartz, and are configured to support the periphery of the back surface of the semiconductor wafer.
以上のように構成された薄膜形成装置について、以下そ
の動作を説明する。The operation of the thin film forming apparatus configured as described above will be described below.
捷ず、半導体ウニはカセット１７−１から搬送ベルト１
９によりウエノ・載置台１８の位置に移送され、ゲート
バルブ１５−１を開放にしだ後、アーム１６−３の移動
及びウエノ・載置台１８とテーブル１２の一ヒ下動によ
り半導体ウエノ・を熱処理室９に搬送する。この間、反
応室１０−１．１０−２は不活性ガスをガス供給０２０
−１．２０−２から流１１ ・−１
しながらガス排気口２２−１．２２−２より真空排気し
、気相成長を行なうときと略等しい圧力に調整するとと
もに、中間室１１−１．１１−２がガス排気口２５−１
，２５−２より真空引きを行なっている。次にゲートパ
ルプ１６−３を閉じた後熱処理室９内の圧力をガス排気
口２６より真空引きして所定圧力にした後、ゲートパル
プ１６−２及び１５−３を開け、アーム１６−１により
半導体ウェハを反応室１ｏ−１のサセプタ２３−１上に
移送する。この時テーブル１２さらにはサセプタ２３−
１の突き上げビン２４−１を上下動させるのは言うまで
もない。ゲートパルプ１５−２ 。The semiconductor sea urchin is transferred from the cassette 17-1 to the conveyor belt 1 without being separated.
9, the semiconductor wafer is transferred to the position of the wafer mounting table 18, and after opening the gate valve 15-1, the semiconductor wafer is heat-treated by moving the arm 16-3 and lowering the wafer mount 18 and table 12. Transfer to room 9. During this time, the reaction chambers 10-1 and 10-2 are supplied with inert gas 020.
-1.20-2 is evacuated from the gas exhaust port 22-1.22-2 while the flow 11.-1 is being applied, and the pressure is adjusted to approximately the same as when performing vapor phase growth, and the intermediate chamber 11-1. 11-2 is the gas exhaust port 25-1
, 25-2. Next, after closing the gate pulp 16-3, the pressure inside the heat treatment chamber 9 is evacuated from the gas exhaust port 26 to a predetermined pressure, and then the gate pulps 16-2 and 15-3 are opened, and the arm 16-1 The semiconductor wafer is transferred onto the susceptor 23-1 of the reaction chamber 1o-1. At this time, the table 12 and the susceptor 23-
Needless to say, the push-up bottle 24-1 of No. 1 is moved up and down. Gate Pulp 15-2.
１６−３を閉じだ後、熱処理室９は次の半導体ウェハを
外部から搬送するためガス供給口２７より不活性ガスを
流して常圧復帰し、一方反応室１ト１ではＰ−ｄｏｐｅ
ｄ Ｐｏ１ｙ Ｓｉの気相成長を行なう。After closing 16-3, the heat treatment chamber 9 returns to normal pressure by flowing inert gas from the gas supply port 27 in order to transfer the next semiconductor wafer from the outside, while in the reaction chamber 1 to 1, P-dope
d PolySi is vapor-phase grown.
Ｐ−ｄｏｐｅｄ Ｐｏ１ｙ Ｓｉの気相成長は反応ガス
にジシラン（Ｓ ｌ ２ Ｈｅ ）及びホスフィン（Ｐ
Ｈ３）をヘリウム（Ｈｅ）ガスで希釈したものをガス供
給口２０−１より供給しながら６５０℃、 ５ Ｔｏｒ
ｒで反応させ行なう。反応終了後、不活性ガスを流し反
応室１０−１から反応ガスを排出した後、ゲートパルプ
１５−２ 、１５−３を開けて、次にＰ−ｄｏｐｅｄＰ
ｏｌｙ Ｓｉ の形成のため熱処理室９に搬送された
半導体ウェハと交換する。このときには熱処理室９は減
圧状態になっている。次に、ゲートパルプ１５−４ 、
１５−５を開は前記と異なる反応室１０−２にＰ−ｄｏ
ｐｅｄ Ｐｏ１ｙ Ｓｉを形成した半導体ウェハをアー
ム１６−２により搬送し、ゲートパルプ１５−４ 、１
５−５を閉じだ後でＷＳ １２の気相成長を行う。ＷＳ
１２は反応ガスに六フッ化タングステン（ＷＦ ）
とモノシラン（Ｓ Ｉ Ｈ４） ヲヘリウム（Ｈｅ）で
希釈した混合ガスを使用し、４００℃。The vapor phase growth of P-doped PolySi uses disilane (S l 2 He ) and phosphine (P
H3) diluted with helium (He) gas at 650°C and 5 Tor while supplying it from the gas supply port 20-1.
Carry out the reaction with r. After the reaction is complete, inert gas is flown in and the reaction gas is discharged from the reaction chamber 10-1, the gate pulps 15-2 and 15-3 are opened, and then the P-doped P
The semiconductor wafer is replaced with the semiconductor wafer transported to the heat treatment chamber 9 for the formation of olySi. At this time, the heat treatment chamber 9 is in a reduced pressure state. Next, Gate Pulp 15-4,
15-5 opens P-do to reaction chamber 10-2 different from the above.
The semiconductor wafer on which the ped PolySi has been formed is transported by the arm 16-2, and gate pulps 15-4, 1
After closing 5-5, vapor phase growth of WS 12 is performed. WS
12 is tungsten hexafluoride (WF) as the reaction gas
and monosilane (S I H4) at 400°C using a mixed gas diluted with helium (He).
５ Ｔｏｒｒで気相成長させた。その後、まずＰ−４ｏ
ｐｅｄＰｏｌｙ Ｓｉの反応室１０〜１側のゲートパル
プ１５−２ 、１５−３を開は新しく外部より搬送した
半導体ウェハと、ＷＳ １２の形成を行なっている間に
反応室１０−１でＰ−ｄｏｐｅｄ Ｐｏ１ｙ Ｓｔを形
成した半導体ウェハとを交換しゲートパルプ１５−２゜
１５−３を閉じた後、ＷＳｉ２を気相成長する反応室１
ｏ−２側のゲートパルプ１６−４ 、１５−５を開き、
Ｗ Ｓ １２を形成した半導体ウエノ・を熱処理室９に
搬送するとともに、それと交換に今Ｐ−４ｏｐｅ ｄＰ
ｏｌｙ Ｓｔ を形成した半導体ウェハを反応室１ｏ
−２に搬送する。ＷＳ １２の気相成長を終了した半導
体ウェハは熱処理室９で真空中で赤外線ランプ１４によ
り１０００℃に加熱され、シリサイド膜の形成が終了す
る。この後、熱処理室９は常圧復帰を行ない、ゲートパ
ルプ１５−１を開け、外部のウェハ載置台１８にある処
理前の半導体ウェハと交換される。ウェハ載置台に移送
された処理済の半導体ウェハは搬送ベルト１９で処理済
の半導体ウェハを収納するカセッ）１７−２に送られる
。Vapor phase growth was performed at 5 Torr. After that, first P-4o
The gate pulps 15-2 and 15-3 on the reaction chamber 10-1 side of pedPoly Si are connected to a semiconductor wafer newly transferred from the outside and P-doped in the reaction chamber 10-1 while forming the WS 12. After replacing the semiconductor wafer on which PolySt was formed and closing the gate pulps 15-2 and 15-3, the reaction chamber 1 in which WSi2 is grown in vapor phase
Open the gate pulps 16-4 and 15-5 on the o-2 side,
The semiconductor wafer formed with W S 12 is transported to the heat treatment chamber 9, and in exchange, P-4ope dP is
The semiconductor wafer on which oly St was formed was placed in reaction chamber 1o.
-2. The semiconductor wafer on which the vapor phase growth of WS 12 has been completed is heated to 1000° C. in vacuum in a heat treatment chamber 9 by an infrared lamp 14, and the formation of the silicide film is completed. Thereafter, the heat treatment chamber 9 is returned to normal pressure, the gate pulp 15-1 is opened, and the unprocessed semiconductor wafer placed on the external wafer mounting table 18 is replaced. The processed semiconductor wafer transferred to the wafer mounting table is sent by a conveyor belt 19 to a cassette 17-2 for storing processed semiconductor wafers.
以上の動作を繰り返すことによりシリサイド膜形成を連
続的に行なうことができる。By repeating the above operations, silicide film formation can be performed continuously.
以上説明した動作において、２つの中間室１１−１．１
１−２は常にガス排気口２６−１゜２５−２より真空引
きを行ない反応室及び熱処理室の圧力より低くした。In the operation described above, the two intermediate chambers 11-1.1
1-2 was always evacuated from the gas exhaust ports 26-1 and 25-2 to make the pressure lower than that of the reaction chamber and heat treatment chamber.
１４へ一／
なお本発明の実施例においては半導体ウェハの搬送に、
腕の先端をＵ字形にしたアームの移動とウェハ載置台、
テーブル、及びサセプタの突き上げビンの上下動により
実行したが、例えば、半導体ウェハの表面周囲を吸着し
て保持して搬送する方法など、これに限定されるもので
はない。Go to 14/ Note that in the embodiment of the present invention, when transporting a semiconductor wafer,
Movement of the arm with a U-shaped end, wafer mounting table,
Although this was carried out by vertically moving the table and the push-up bin of the susceptor, the present invention is not limited to this method, for example, a method of suctioning and holding the periphery of the surface of the semiconductor wafer and transporting the semiconductor wafer.
また、本実施例においては熱処理室を中心にして、その
両側に２つの反応室を配置して、半導体ウェハを一旦熱
処理室を通過させて搬送しだが、２つの反応室と熱処理
室を直列に配置して、一方向のみ半導体ウェハを搬送し
ていく方法も可能である。In addition, in this example, two reaction chambers are arranged on both sides of the heat treatment chamber, and the semiconductor wafer is transported once passing through the heat treatment chamber, but the two reaction chambers and the heat treatment chamber are connected in series. It is also possible to arrange the semiconductor wafer in one direction and transport the semiconductor wafer in only one direction.
また、本実施例では、シリサイド膜の形成について説明
したが１つの反応室と２つの熱処理室を組み合わせ、Ｐ
ｏ１ｙ Ｓｔ の気相成長−Ｐのドープ−熱処理の工
程、すなわちＰｏ１ｙ ＳｉからのＰ−ｄｏｐｅｄ Ｐ
ｏ１ｙ Ｓｔの形成等にも利用できる。In addition, in this example, the formation of a silicide film was explained, but it is also possible to combine one reaction chamber and two heat treatment chambers.
Vapor phase growth of o1y St - doping of P - heat treatment process, i.e. P-doped P from Po1y Si
It can also be used for forming o1y St.
発明の効果
以上のように本発明は、反応室及び熱処理室を半導体ウ
ェハの搬送手段を備えた中間室により連１５’・−
続することにより、シリサイド膜等の薄膜形成を大気に
ふれずに連続的に形成することができ、まだダスト等の
ない高品質の薄膜が効率よく形成できる。さらに、中間
室の圧力を反応室あるいは熱処理室の圧力より低くする
とともに、さらに中間室に接したゲートバルブを反応室
あるいは熱処理室側の壁面に密着させる構成とすること
により、反応室あるいは熱処理室の気密性が向上する。Effects of the Invention As described above, the present invention enables the formation of thin films such as silicide films without being exposed to the atmosphere by connecting a reaction chamber and a heat treatment chamber through an intermediate chamber equipped with a means for transporting a semiconductor wafer. It can be formed continuously, and a high quality thin film that is free of dust etc. can be efficiently formed. Furthermore, by making the pressure in the intermediate chamber lower than the pressure in the reaction chamber or heat treatment chamber, and by making the gate valve in contact with the intermediate chamber tightly contact the wall on the reaction chamber or heat treatment chamber side, the pressure in the reaction chamber or heat treatment chamber can be lowered. Improves airtightness.
第１図は本発明の一実施例の薄膜形成装置の概略図、第
２図は同薄膜形成装置の断面概略図、第３図は従来のＷ
Ｓ １２のゲート形成法の一例を示す工程図、第４図は
従来のＰｏ１ｙ Ｓｉ膜等の形成に使用される気相成長
装置の断面概略図、第５図は従来のＷ Ｓ １２膜等の
形成に使用される気相成長装置の断面概略図である。
９熱処理室、１０−１．１０−２反応室、１１−１．１
１−２中間室、１５−１゜１５−２．１５−３．１５−
４ゲートバルブ、
１６−１ 、１６−２アーム（搬送手段）。
猷 １ へ
Ｃ″′ ぐ４
第３図
δＧ 気月戚長
ＰＩ−ブ （↓乞貫（）
ｆＩ豚イビＩｌ曽丁、、キ・ノｄ岬
第４図
、５
第５図Fig. 1 is a schematic diagram of a thin film forming apparatus according to an embodiment of the present invention, Fig. 2 is a cross-sectional schematic diagram of the same thin film forming apparatus, and Fig. 3 is a conventional W
FIG. 4 is a cross-sectional schematic diagram of a vapor phase growth apparatus used for forming a conventional PolySi film, etc., and FIG. 5 is a process diagram showing an example of a method for forming a gate of S12. It is a cross-sectional schematic diagram of a vapor phase growth apparatus used for formation. 9 heat treatment chamber, 10-1.10-2 reaction chamber, 11-1.1
1-2 intermediate chamber, 15-1゜15-2.15-3.15-
4 gate valve, 16-1, 16-2 arms (transport means).猷 1 to C″′ gu 4 Fig. 3 δG Kigetsu Kicho PI-bu (↓Kaikan() fI pig ibis Il So Ding, Ki Nod Misaki Fig. 4, 5 Fig. 5
Claims (4)
も一つの反応室と、半導体ウェハを保持し加熱できる構
成にした少なくとも一つの熱処理室と、前記反応室と熱
処理室との間をゲートバルブを介して連結させる中間室
とからなり、前記中間室の内部に、反応室あるいは熱処
理室との間で半導体ウェハを移送する搬送手段を設けた
ことを特徴とする薄膜形成装置。(1) At least one reaction chamber for forming a vapor-phase grown film on a semiconductor wafer, at least one heat treatment chamber configured to hold and heat the semiconductor wafer, and a gate valve between the reaction chamber and the heat treatment chamber. What is claimed is: 1. A thin film forming apparatus comprising: an intermediate chamber connected to the intermediate chamber via a reaction chamber or a heat treatment chamber;
力より低くしたことを特徴とする特許請求の範囲第１項
記載の薄膜形成装置。(2) The thin film forming apparatus according to claim 1, wherein the pressure in the intermediate chamber is lower than the pressure in the adjacent reaction chamber and heat treatment chamber.
着させることを特徴とする特許請求の範囲第２項記載の
薄膜形成装置。(3) The thin film forming apparatus according to claim 2, wherein the gate valve is brought into close contact with the wall surface on the side of the reaction chamber and the heat treatment chamber.
ン膜、もしくは不純物をドープした多結晶シリコン膜を
気相成長し、他の反応室で高融点金属膜、もしくは高融
点金属のシリサイド膜を形成することを特徴とする特許
請求の範囲第１項〜第３項の何れかに記載の薄膜形成装
置。(4) It has two reaction chambers, in which a polycrystalline silicon film or a polycrystalline silicon film doped with impurities is grown in vapor phase in one reaction chamber, and a high melting point metal film or a high melting point metal film is grown in the other reaction chamber. A thin film forming apparatus according to any one of claims 1 to 3, characterized in that the thin film forming apparatus forms a silicide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26910686A JPS63125681A (en) | 1986-11-12 | 1986-11-12 | Thin film forming device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26910686A JPS63125681A (en) | 1986-11-12 | 1986-11-12 | Thin film forming device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63125681A true JPS63125681A (en) | 1988-05-28 |
Family
ID=17467752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26910686A Pending JPS63125681A (en) | 1986-11-12 | 1986-11-12 | Thin film forming device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63125681A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0239527A (en) * | 1988-07-29 | 1990-02-08 | Tokyo Electron Ltd | Metallic silicide film forming method |
| JPH02133923A (en) * | 1988-11-14 | 1990-05-23 | Tokyo Electron Ltd | Manufacture of semiconductor device |
| JPH02187021A (en) * | 1989-01-13 | 1990-07-23 | Sharp Corp | Manufacture of semiconductor device |
| JPH02192120A (en) * | 1989-01-19 | 1990-07-27 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPH02303123A (en) * | 1989-05-18 | 1990-12-17 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JPH02303122A (en) * | 1989-05-18 | 1990-12-17 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JPH03133133A (en) * | 1989-10-19 | 1991-06-06 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JP2755369B2 (en) * | 1992-02-25 | 1998-05-20 | エージー．アソシェーツ、インコーポレイテッド | Gas phase doping of semiconductor materials under reduced pressure in a radiantly heated cold wall reactor |
| JP2002208754A (en) * | 2001-01-11 | 2002-07-26 | Denso Corp | Method of manufacturing semiconductor laser element |
| US6488984B1 (en) | 1998-10-29 | 2002-12-03 | Applied Materials Inc. | Film deposition method and apparatus |
| US6852626B1 (en) | 1998-10-29 | 2005-02-08 | Applied Materials, Inc. | Film deposition method and apparatus |
| KR20180073519A (en) | 2015-05-19 | 2018-07-02 | 후세진공가부시키가이샤 | Surface protecting method and surface decoration method of adherend |
| JP2020002446A (en) * | 2018-06-29 | 2020-01-09 | 住友金属鉱山株式会社 | Atomic layer deposition apparatus and method of manufacturing coating film formation particle using the same |
-
1986
- 1986-11-12 JP JP26910686A patent/JPS63125681A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0239527A (en) * | 1988-07-29 | 1990-02-08 | Tokyo Electron Ltd | Metallic silicide film forming method |
| JPH02133923A (en) * | 1988-11-14 | 1990-05-23 | Tokyo Electron Ltd | Manufacture of semiconductor device |
| JPH02187021A (en) * | 1989-01-13 | 1990-07-23 | Sharp Corp | Manufacture of semiconductor device |
| JPH02192120A (en) * | 1989-01-19 | 1990-07-27 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPH02303123A (en) * | 1989-05-18 | 1990-12-17 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JPH02303122A (en) * | 1989-05-18 | 1990-12-17 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JPH03133133A (en) * | 1989-10-19 | 1991-06-06 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JP2755369B2 (en) * | 1992-02-25 | 1998-05-20 | エージー．アソシェーツ、インコーポレイテッド | Gas phase doping of semiconductor materials under reduced pressure in a radiantly heated cold wall reactor |
| US6488984B1 (en) | 1998-10-29 | 2002-12-03 | Applied Materials Inc. | Film deposition method and apparatus |
| WO2004102649A1 (en) * | 1998-10-29 | 2004-11-25 | Yuichi Wada | Film forming method and apparatus |
| US6852626B1 (en) | 1998-10-29 | 2005-02-08 | Applied Materials, Inc. | Film deposition method and apparatus |
| JP2002208754A (en) * | 2001-01-11 | 2002-07-26 | Denso Corp | Method of manufacturing semiconductor laser element |
| KR20180073519A (en) | 2015-05-19 | 2018-07-02 | 후세진공가부시키가이샤 | Surface protecting method and surface decoration method of adherend |
| JP2020002446A (en) * | 2018-06-29 | 2020-01-09 | 住友金属鉱山株式会社 | Atomic layer deposition apparatus and method of manufacturing coating film formation particle using the same |
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