JPS63121965U - - Google Patents
Info
- Publication number
- JPS63121965U JPS63121965U JP1341987U JP1341987U JPS63121965U JP S63121965 U JPS63121965 U JP S63121965U JP 1341987 U JP1341987 U JP 1341987U JP 1341987 U JP1341987 U JP 1341987U JP S63121965 U JPS63121965 U JP S63121965U
- Authority
- JP
- Japan
- Prior art keywords
- mark
- mark detection
- main scanning
- scanning direction
- detection section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 16
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 1
Landscapes
- Image Input (AREA)
- Facsimile Scanning Arrangements (AREA)
Description
第1図は本考案によるマーク検出回路の一実施
例を示すブロツク構成図である。
6……読取画信号、7……画信号同期クロツク
、8……マーク検出区間信号、9……マーク検出
信号、10……マーク検出回路リセツト信号、1
1……リードオンリーメモリ、12……カウンタ
、13……カウンタ、14……インバータ回路、
15……アンド回路。
第2図は本考案における原稿走査面を示した図
である。
1……読取主走査方向、2……読取副走査方向
、3……読取走査範囲、4……マーク検出区間(
主走査方向)、5……原稿読取区間(主走査方向
)、a……マーク。
第3図は本考案によるマーク検出回路の入力信
号を示した図である。
7……画信号同期クロツク、6……読取画信号
、8……マーク検出区間信号、19……マーク検
出区間画信号、20……原稿読取区間画信号、2
1……主走査1ライン周期。
第4図は本考案によるマーク検出回路のリード
オンリメモリの書込内容とマークとの比較とを表
示した図である。
22……主走査方向、23……副走査方向、2
4……マーク、25……マーク検出区間。
第5図は本考案以前に考案された飛越走査スキ
ヤナの飛越マークの検出方法を説明するための図
である。
51……読取主走査方向、52……読取副走査
方向、53……読取走査範囲、54……マーク検
出区間(主走査方向)、55……原稿読取区間(
主走査方向)、56……飛越マーク、57……原
稿読取区間(副走査方向)、58……原稿読飛ば
し区間(副走査方向)、59……飛越マーク検出
時の主走査1ラインの画信号、60……飛越マー
ク未検出時の主走査1ラインの画信号、61……
飛越マーク信号、62……画信号。
FIG. 1 is a block diagram showing an embodiment of a mark detection circuit according to the present invention. 6... Read image signal, 7... Image signal synchronization clock, 8... Mark detection interval signal, 9... Mark detection signal, 10... Mark detection circuit reset signal, 1
1...Read-only memory, 12...Counter, 13...Counter, 14...Inverter circuit,
15...AND circuit. FIG. 2 is a diagram showing a document scanning surface according to the present invention. 1...Reading main scanning direction, 2...Reading sub-scanning direction, 3...Reading scanning range, 4...Mark detection section (
main scanning direction), 5... document reading section (main scanning direction), a... mark. FIG. 3 is a diagram showing input signals of the mark detection circuit according to the present invention. 7... Image signal synchronization clock, 6... Reading image signal, 8... Mark detection section signal, 19... Mark detection section picture signal, 20... Original reading section picture signal, 2
1...Main scanning 1 line period. FIG. 4 is a diagram showing a comparison between the contents written in the read-only memory of the mark detection circuit according to the present invention and the marks. 22...Main scanning direction, 23...Sub scanning direction, 2
4... Mark, 25... Mark detection section. FIG. 5 is a diagram for explaining a method of detecting interlaced marks in an interlaced scanner devised before the present invention. 51...Reading main scanning direction, 52...Reading sub-scanning direction, 53...Reading scanning range, 54...Mark detection section (main scanning direction), 55...Document reading section (
(main scanning direction), 56... skipped mark, 57... document reading section (sub-scanning direction), 58... document skipping section (sub-scanning direction), 59... image of 1 line in main scanning when detecting skipped mark Signal, 60... Image signal of 1 line of main scanning when skipped mark is not detected, 61...
Jump mark signal, 62...Picture signal.
Claims (1)
出区間とし、マーク検出区間中のマークを副走査
動作中に検出する機能を有するスキヤナ装置にお
いて、読み取られた一主走査線のうちマーク検出
区間中のマークの幅を測定し、それとマーク検出
回路中に蓄積されていたマークの形状データとを
比較し、複数ライン連続して読み取られたマーク
の総ビツト数がマークの副走査方向の長さ以内で
適正な数である事を検出する事により、マークの
検出、未検出を判断する事を特徴とするスキヤナ
のマーク検出回路。 A certain section of the main scanning line in the scanning screen is defined as a mark detection section, and in a scanner device that has a function of detecting marks within the mark detection section during sub-scanning operation, the mark detection section of one main scanning line that has been read is used. Measure the width of the mark, compare it with the mark shape data stored in the mark detection circuit, and determine whether the total number of bits of the mark read in multiple lines consecutively is within the length of the mark in the sub-scanning direction. A scanner mark detection circuit is characterized in that it determines whether a mark is detected or not by detecting a proper number of marks.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1341987U JPS63121965U (en) | 1987-01-31 | 1987-01-31 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1341987U JPS63121965U (en) | 1987-01-31 | 1987-01-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63121965U true JPS63121965U (en) | 1988-08-08 |
Family
ID=30802464
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1341987U Pending JPS63121965U (en) | 1987-01-31 | 1987-01-31 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63121965U (en) |
-
1987
- 1987-01-31 JP JP1341987U patent/JPS63121965U/ja active Pending
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