JPS63119581A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS63119581A JPS63119581A JP61265371A JP26537186A JPS63119581A JP S63119581 A JPS63119581 A JP S63119581A JP 61265371 A JP61265371 A JP 61265371A JP 26537186 A JP26537186 A JP 26537186A JP S63119581 A JPS63119581 A JP S63119581A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- field oxide
- tunnel
- erasing
- writing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 230000005641 tunneling Effects 0.000 claims abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract 1
- 230000006378 damage Effects 0.000 description 7
- 238000000605 extraction Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
トンネル酸化膜部がフィールド酸化膜のエツジ邪に掛か
らないようにした電気的書込み消去可能なメモリセル。[Detailed Description of the Invention] [Summary] An electrically programmable and erasable memory cell in which a tunnel oxide film portion does not overlap the edge of a field oxide film.
本発明は半導体記憶装置のメモリセル、特に電気的に書
込み消去可能なＦＲＯＭ （ＥＥＰＲＯＭ）のメモリセ
ルに関する。The present invention relates to a memory cell of a semiconductor memory device, and particularly to an electrically programmable and erasable FROM (EEPROM) memory cell.
ＥＥＦＲＯＭのメモリセルには第４図、第５図に示す構
造のものがある。Ｑｌは記憶用のトランジスタ部、Ｑ３
はその書込み／消去部、Ｑ２は選択用トランジスタであ
る。ロー線（ワード線）Ｘ２を選択する（Ｈレベルにす
る）とトランジスタＱ２はオンになり、トランジスタＱ
１はコラム線（ビット線）Ｙに接続され、フローティン
グゲートＦＣがＨ（電子抽出）であればＱ＋オン、従っ
てＹ。Some EEFROM memory cells have structures shown in FIGS. 4 and 5. Ql is a memory transistor section, Q3
is its write/erase section, and Q2 is a selection transistor. When low line (word line) X2 is selected (set to H level), transistor Q2 is turned on, and transistor Q
1 is connected to the column line (bit line) Y, and if the floating gate FC is H (electron extraction), Q+ is on, so Y.
Ｑ２．Ｑｌ、グランドの経路で電流が流れる。フローテ
ィングゲー）ＦＧがＬ（電子注入）であればＱｌはオフ
であり、上記電流は流れない。これにより記憶情報のＨ
／Ｌ （電子抽出／注入）を読取ることができる。Q2. Current flows through the path between Ql and ground. If floating gate) FG is L (electron injection), Ql is off and the above current does not flow. As a result, H
/L (electronic extraction/injection) can be read.
書込み／消去は次のようにして行なう。即ち、ロー線Ｘ
２を選択してＱ２をオンにし、またロー線Ｘ１をＨ１従
ってコントロールゲートをＨにし、容量結合でフローテ
ィングゲートＦＣもＨにし、そしてコラム線ＹはＬにす
ると、フローティングゲー）ＦＣの書込み／消去部Ｑ３
においてＱｌのドレインＤ１からＦＣへ、これらの間の
絶縁膜を通して電子が注入される（消去）。即ち０３部
分の絶縁膜は極めて薄（、ある程度以上の電界が加わる
と電子のトンネリングが可能である。これに対してロー
線Ｘ＋をし、従ってＣＧをし、容量結合でＦＣもＬとし
、コラム線ＹをＨにすると、ＦＧから電子が０３部分の
絶縁膜をトンネリングしてＱ＋のドレインＤ１へ抽出さ
れる（書込み）。Writing/erasing is performed as follows. That is, the low wire
2 is selected and Q2 is turned on, and the row line Part Q3
Electrons are injected from the drain D1 of Ql to FC through the insulating film between them (erasing). In other words, the insulating film in the 03 part is extremely thin (if an electric field above a certain level is applied, electron tunneling is possible).For this, the low line When the line Y is set to H, electrons from FG tunnel through the insulating film of the 03 portion and are extracted to the drain D1 of Q+ (writing).
トランジスタＱｌ、Ｑ２のソース／ドレインＳ１、Ｓ２
／ＤＩ、Ｄ２が形成される活性領域の周囲は厚い絶縁層
であるフィールド酸化膜Ｆｌとなっている。書込み／消
去部Ｑ３は記憶用トランジスタＱ１のゲート部から離れ
ており、活性領域は図示の如くこれらの部分でＬ字型を
なしている。Source/drain S1, S2 of transistors Ql, Q2
The area around the active region where /DI and D2 are formed is a field oxide film Fl, which is a thick insulating layer. The write/erase portion Q3 is separated from the gate portion of the storage transistor Q1, and the active region is L-shaped in these portions as shown.
書込み／消去部Ｑ３でフィールド酸化膜ＦＩは直線状に
入り込んでくる活性領域の３方を包囲する形になってお
り、フローティングゲートＦＧはこの部分で湾にか−る
橋のようになっており、その下部の薄い絶縁層（トンネ
ル酸化膜Ｔｏ）は両端がフィールド酸化膜ＦＩに接して
いる。In the write/erase section Q3, the field oxide film FI has a shape that surrounds the active region that enters in a straight line on three sides, and the floating gate FG is shaped like a bridge over a bay in this part. , the lower thin insulating layer (tunnel oxide film To) is in contact with the field oxide film FI at both ends.
この構造では、書込み／消去を行なっているとやがてト
ンネル領域が損傷し、書込み／消去不能になる。書込み
／消去部Ｑ３の、定電流により破壊に至るまでの通過電
気量は数〜１０クーロン程度であり、寿命が短く、信頼
性に問題が残る。In this structure, when writing/erasing is performed, the tunnel region is eventually damaged, making writing/erasing impossible. The amount of electricity that passes through the write/erase section Q3 until it is destroyed by a constant current is about several to 10 coulombs, so the service life is short and reliability remains a problem.
書込み／消去不能になったメモリセルを調べてみると、
損傷はトンネル酸化膜とフィールド酸化膜の接触部で生
じているケースが多い。トンネル酸化膜がフィールド酸
化膜の端縁に接していると、この端縁近傍では欠陥が多
く、酸化膜厚の特に薄い部分も発生し、これが書込み／
消去の繰り返しで、端縁近傍で、損傷発生の原因と考え
られる。When examining memory cells that have become unprogrammable/erasable, we find that
In many cases, damage occurs at the contact between the tunnel oxide film and the field oxide film. If the tunnel oxide film is in contact with the edge of the field oxide film, there will be many defects near this edge, and there will also be areas where the oxide film is particularly thin.
Repeated erasing is thought to be the cause of damage near the edges.
本発明はか＼る点を改善し、反復書込み／消去に耐える
、長寿命のＥＥＰＲＯＭメモリセルを提供しようとする
ものである。The present invention aims to improve these points and provide a long-life EEPROM memory cell that can withstand repeated programming/erasing.
本発明は、一部が薄い絶縁層を介してドレイン領域と対
向し、該薄い絶縁層を通して電子のトンネリングが可能
なフローティングゲー） （ＦＧ）およびその上のコン
トロールゲート（ＣＧ）を有する記憶用トランジスタ（
Ｑ１）と選択用トランジスタ（Ｑ２）とを直列に接続し
てなるメモリセルを備える半導体記憶装置において、電
子がトンネリングする該薄い絶縁層（Ｔｏ）は、ソース
、ドレイン領域が形成される活性層の周囲のフィールド
酸化膜（ＦＩ）から離れて形成されたことを特徴とする
ものである。The present invention relates to a memory transistor having a floating gate (FG), a part of which faces a drain region through a thin insulating layer, and allows electron tunneling through the thin insulating layer, and a control gate (CG) thereon. (
In a semiconductor memory device including a memory cell formed by connecting a selection transistor (Q2) and a selection transistor (Q2) in series, the thin insulating layer (To) through which electrons tunnel is located in the active layer where the source and drain regions are formed. It is characterized by being formed away from the surrounding field oxide film (FI).
このメモリセルでは、トンネル電流を流して書込み／消
去を行なうトンネル酸化膜部分がフィールド酸化膜の端
縁に接しておらず、このため損傷を生じ易いフィールド
酸化膜端縁近傍をトンネル電流が流れることはないので
、定電流により破壊に至るまでの通過電荷量が２０ク一
ロン以上となり、寿命が長くなり、信頼性が向上する利
点が得られる。In this memory cell, the tunnel oxide film part where tunnel current flows to perform writing/erasing is not in contact with the edge of the field oxide film, so the tunnel current flows near the edge of the field oxide film, where damage is likely to occur. Since there is no current, the amount of charge that passes through until destruction due to constant current is 20 corons or more, which provides the advantage of a longer life and improved reliability.
第１図に本発明の実施例を示す。第４図と同じ部分には
同じ符号が付しである。両者を比較すれば明らかなよう
に第１図は第４図とぼり同様であるが、書込み／消去部
Ｑ３ではフローティングゲ−）ＦＣは、フィールド酸化
膜ＦＩ内に直線状に入り込む活性領域の中央部を同方向
に延び、その下部のトンネル酸化膜は該活性領域内にあ
り、フィールド酸化膜Ｆｌとは接していない。このため
トンネル領域がフィールド酸化膜ＦＩの端縁を含まず、
繰り返し書込み／消去に耐え得る。この構造によれば定
電流による破壊に至るまでの通過電荷量は２０ク一ロン
以上になり、寿命が長く、信頼性が向上する。FIG. 1 shows an embodiment of the present invention. The same parts as in FIG. 4 are given the same reference numerals. As is clear from comparing the two, FIG. 1 is the same as FIG. The lower tunnel oxide film is within the active region and is not in contact with the field oxide film Fl. Therefore, the tunnel region does not include the edge of the field oxide film FI,
Can withstand repeated writing/erasing. With this structure, the amount of charge that passes through until destruction due to constant current is 20 corons or more, resulting in a long life and improved reliability.
第２図は記憶用トランジスタ０１部に書込み／消去部Ｑ
３を組込んだ例を示し、第３図は第２図Ａ−Ａ’線の断
面図である。これらの図に示されるようにフローティン
グゲートＦＣは中央部で凹んでおり、この凹んだ部分の
下部絶縁層は薄く、電子のトンネル電流が可能である。Figure 2 shows the write/erase section Q in the memory transistor 01 section.
3 is a sectional view taken along the line AA' in FIG. 2. As shown in these figures, the floating gate FC is recessed in the center, and the lower insulating layer in this recessed portion is thin, allowing electron tunneling current to occur.
この凹んだ部分の基板にｎ＋拡散領域りを形成し、電子
注入／抽出を容易にする。このトンネル領域のトンネル
酸化膜もフィールド酸化膜と接しておらず、前記の問題
は生じない。An n+ diffusion region is formed in the substrate in this recessed area to facilitate electron injection/extraction. The tunnel oxide film in this tunnel region is also not in contact with the field oxide film, so the above-mentioned problem does not occur.
第２図のトンネル領域等を形成するには、例えば次の如
くすればよい。即ち選択酸化によりフィールド酸化膜Ｆ
Ｉを形成し、次にトンネル領域に窓を持つマスクを通し
てイオン注入してｎ＋領領域を作る。次に軽く熱酸化し
て全面にトンネル酸化膜を作り、次にトンネル領域以外
を選択酸化してゲート絶縁膜とする。その後はＱｌのフ
ローティングゲートＦＧおよびＱ２のゲート形成、これ
らをマスクにしてのソース、ドレイン用イオン打込み、
ＣＶＤ法による絶縁層（第５図のＬＩ）形成、コントロ
ールゲートＣＧ形成などを行なえばよい。To form the tunnel region shown in FIG. 2, for example, the following steps may be performed. That is, the field oxide film F is formed by selective oxidation.
I is formed, and then ions are implanted through a mask having a window in the tunnel region to form an n+ region. Next, a tunnel oxide film is formed on the entire surface by light thermal oxidation, and then the area other than the tunnel region is selectively oxidized to form a gate insulating film. After that, the floating gate FG of Ql and the gate of Q2 are formed, and ion implantation for the source and drain is performed using these as masks.
Formation of an insulating layer (LI in FIG. 5), control gate CG, etc. may be performed by the CVD method.
以上説明したように本発明では、トンネル電流を流して
書込み／消去を行なうトンネル酸化膜部分がフィールド
酸化膜の端縁に接しておらず、このため損傷を生じ易い
フィールド酸化膜端縁近傍をトンネル電流が流れること
はないので、定電流により破壊に至るまでの通過電荷量
が２０ク一ロン以上となり、寿命が長くなり、信頼性が
向上する利点が得られる。As explained above, in the present invention, the tunnel oxide film portion in which writing/erasing is performed by flowing a tunnel current is not in contact with the edge of the field oxide film, and therefore, the tunnel oxide film near the edge of the field oxide film, where damage is likely to occur, is Since no current flows, the amount of charge that passes until destruction occurs due to constant current is 20 courier or more, which provides the advantage of longer life and improved reliability.
第１図および第２図は本発明の実施例を示す説明図、
第３図は第２図のＡ−Ａ’線断面図、
第４図は従来例の概略平面図、
第５図（ａ）および（ｂ）は第４図の等価回路図および
一部の断面図である。
第１図でＱｌは記憶用トランジスタ、ＳＬ、ＤＩはその
ソース、ドレイン領域、Ｑ２は選択用トランジスタ、Ｓ
２．Ｄ２はそのソース、ドレイン領域、ＦＣはフローテ
ィングゲート、ＣＧはコントロールゲート、Ｔｏは薄い
絶縁層、ＦＩはフィールド酸化膜である。1 and 2 are explanatory diagrams showing an embodiment of the present invention, FIG. 3 is a sectional view taken along the line AA' in FIG. 2, FIG. 4 is a schematic plan view of a conventional example, and FIG. ) and (b) are an equivalent circuit diagram and a partial sectional view of FIG. 4. In Figure 1, Ql is a storage transistor, SL and DI are its source and drain regions, Q2 is a selection transistor, and S
2. D2 is the source and drain region, FC is the floating gate, CG is the control gate, To is the thin insulating layer, and FI is the field oxide film.
Claims (1)
薄い絶縁層を通して電子のトンネリングが可能なフロー
ティングゲート（ＦＧ）およびその上のコントロールゲ
ート（ＣＧ）を有する記憶用トランジスタ（Ｑ＿１）と
選択用トランジスタ（Ｑ＿２）とを直列に接続してなる
メモリセルを備える半導体記憶装置において、 電子がトンネリングする該薄い絶縁層（ＴＯ）は、ソー
ス、ドレイン領域が形成される活性層の周囲のフィール
ド酸化膜（ＦＩ）から離れて形成されたことを特徴とす
る半導体記憶装置。[Claims] A memory device having a floating gate (FG), a part of which faces a drain region through a thin insulating layer, and which allows electron tunneling through the thin insulating layer, and a control gate (CG) above the floating gate. In a semiconductor memory device including a memory cell formed by connecting a transistor (Q_1) and a selection transistor (Q_2) in series, the thin insulating layer (TO) through which electrons tunnel is an active layer where source and drain regions are formed. A semiconductor memory device characterized in that the layer is formed away from a surrounding field oxide film (FI).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61265371A JPS63119581A (en) | 1986-11-07 | 1986-11-07 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61265371A JPS63119581A (en) | 1986-11-07 | 1986-11-07 | Semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63119581A true JPS63119581A (en) | 1988-05-24 |
Family
ID=17416251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61265371A Pending JPS63119581A (en) | 1986-11-07 | 1986-11-07 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63119581A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4749419B2 (en) * | 2004-05-27 | 2011-08-17 | ザ・ボーイング・カンパニー | Vacuum cup |
| JP2012218099A (en) * | 2011-04-06 | 2012-11-12 | Smc Corp | Suction apparatus equipped with ejector |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60186069A (en) * | 1983-12-09 | 1985-09-21 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | Semiconductor device |
| JPS61208865A (en) * | 1985-03-13 | 1986-09-17 | Mitsubishi Electric Corp | Semiconductor memory |
-
1986
- 1986-11-07 JP JP61265371A patent/JPS63119581A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60186069A (en) * | 1983-12-09 | 1985-09-21 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | Semiconductor device |
| JPS61208865A (en) * | 1985-03-13 | 1986-09-17 | Mitsubishi Electric Corp | Semiconductor memory |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4749419B2 (en) * | 2004-05-27 | 2011-08-17 | ザ・ボーイング・カンパニー | Vacuum cup |
| JP2012218099A (en) * | 2011-04-06 | 2012-11-12 | Smc Corp | Suction apparatus equipped with ejector |
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