JPS63117176U - - Google Patents

Info

Publication number
JPS63117176U
JPS63117176U JP796787U JP796787U JPS63117176U JP S63117176 U JPS63117176 U JP S63117176U JP 796787 U JP796787 U JP 796787U JP 796787 U JP796787 U JP 796787U JP S63117176 U JPS63117176 U JP S63117176U
Authority
JP
Japan
Prior art keywords
circuit
multiplexing
recording
output
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP796787U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP796787U priority Critical patent/JPS63117176U/ja
Publication of JPS63117176U publication Critical patent/JPS63117176U/ja
Pending legal-status Critical Current

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  • Television Signal Processing For Recording (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す記録側回路ブ
ロツク図、第2図は再生側のデコーダ回路の回路
ブロツク図をそれぞれ顕わす。 3……最大値検出回路、4……最小値検出回路
、5……多重回路。
FIG. 1 shows a recording side circuit block diagram showing one embodiment of the present invention, and FIG. 2 shows a circuit block diagram of a reproducing side decoder circuit. 3...Maximum value detection circuit, 4...Minimum value detection circuit, 5...Multiple circuit.

Claims (1)

【実用新案登録請求の範囲】 アナログ映像情報を記録する映像記録装置に於
て、 映像信号の1画面中の最大レベルと最小レベル
を検出するレベル検出回路と、 該レベル検出回路の出力を映像信号のブランキ
ング期間に多重する多重回路と、 該多重回路の出力を記録媒体に記録する記録手
段とを、 それぞれ配して成る変域情報多重記録回路。
[Claim for Utility Model Registration] In a video recording device that records analog video information, a level detection circuit that detects the maximum level and minimum level in one screen of a video signal, and the output of the level detection circuit is used as a video signal. A range information multiplexing recording circuit comprising: a multiplexing circuit that performs multiplexing during a blanking period; and a recording means that records the output of the multiplexing circuit on a recording medium.
JP796787U 1987-01-22 1987-01-22 Pending JPS63117176U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP796787U JPS63117176U (en) 1987-01-22 1987-01-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP796787U JPS63117176U (en) 1987-01-22 1987-01-22

Publications (1)

Publication Number Publication Date
JPS63117176U true JPS63117176U (en) 1988-07-28

Family

ID=30791914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP796787U Pending JPS63117176U (en) 1987-01-22 1987-01-22

Country Status (1)

Country Link
JP (1) JPS63117176U (en)

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