JPS6310911A - Control circuit for electronic tuner - Google Patents
Control circuit for electronic tunerInfo
- Publication number
- JPS6310911A JPS6310911A JP61155831A JP15583186A JPS6310911A JP S6310911 A JPS6310911 A JP S6310911A JP 61155831 A JP61155831 A JP 61155831A JP 15583186 A JP15583186 A JP 15583186A JP S6310911 A JPS6310911 A JP S6310911A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- pll
- lpf
- terminal
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 19
- 238000010586 diagram Methods 0.000 description 5
- 230000010363 phase shift Effects 0.000 description 4
- 238000007599 discharging Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電子同調チューナ用制御回路、特にＰＬＬ（フ
ェーズ ロックド ループ）出力端のローパスフィルタ
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control circuit for an electronically tuned tuner, and particularly to a low-pass filter at the output end of a PLL (phase locked loop).
この種のローパスフィルタ（ＬＰＦ）は第４図に示すよ
うに１−ランジスタＱ ＋ 、キャパシタＣ１抵抗Ｒａ
、Ｒｂ、Ｒｄからなる、アクティブ素子Ｑ１を含む積分
回路である。入力はＰＬＬ ＩＣの出力で、制御信号
ｃｓによりスイッチｓ１がオン、Ｓ２がオフになると該
出力は■（レベル（５Ｖ）になり、ＬＰＦの出力電圧Ｔ
Ｖは減少を開始する。This type of low-pass filter (LPF) is composed of 1-transistor Q + , capacitor C1, resistor Ra as shown in FIG.
, Rb, and Rd, and includes an active element Q1. The input is the output of the PLL IC, and when switch s1 is turned on and switch S2 is turned off by the control signal cs, the output becomes ■ (level (5V)), and the LPF output voltage T
V starts decreasing.
制御信号Ｏ８によりスイッチｓ２がオン、Ｓｔがオフに
なるとＰＬＬ ＩＣの出力はＬレベル（０■）になり
、ＬＰＦの出力電圧ＴＶは増加を始める。これらはラジ
オ受信機の局部発振器の出方周波数が所望放送局受信時
のそれ（基準周波数）よりずれている場合で、一致する
とＳｔ、Ｓ２は共にオフとなり（Ｓｌ、Ｓ２はＨレベル
、Ｌレベル、およびハイインピーダンス状態を出力する
スリースチートスインチ）、ＬＰＦへの入力はない（ハ
イインピーダンス状態）。出力電圧ＴＶ（チューニング
電圧）は、抵抗Ｒ＋、キャパシタＣ１、バリキャップダ
イオードＶＤを含むチューナ部の入力となり、ＶＤの容
量値を変え、ひいては局発周波数を変化させ、上記一致
を実現させる。When the switch s2 is turned on and St is turned off by the control signal O8, the output of the PLL IC becomes L level (0■), and the output voltage TV of the LPF starts to increase. These are cases where the output frequency of the radio receiver's local oscillator deviates from that when receiving the desired broadcasting station (reference frequency). When they match, both St and S2 are turned off (Sl and S2 are at H level and L level. , and three cheat switches outputting a high-impedance state), there is no input to the LPF (high-impedance state). The output voltage TV (tuning voltage) becomes an input to a tuner section including a resistor R+, a capacitor C1, and a varicap diode VD, and changes the capacitance value of VD, thereby changing the local frequency to achieve the above coincidence.
このＬＰＦ部はＰＬＬ ＩＣには組込まれておらず、
外付は部品である。その理由の１つは、チューナ部のバ
リキャップ（可変容量）ダイオードＶＤに印加する電圧
は０〜８Ｖで、ＩＣ電源の５Ｖでは不足である、ことで
ある。またキャパシタＣの容量値が大きく、ＩＣ（集積
回路）では構成しにくい事も挙げられる。This LPF section is not incorporated into the PLL IC,
External parts are parts. One of the reasons for this is that the voltage applied to the varicap (variable capacitance) diode VD of the tuner section is 0 to 8 V, and the 5 V of the IC power supply is insufficient. Another problem is that the capacitance value of the capacitor C is large, making it difficult to configure with an IC (integrated circuit).
しかしながら、アクティブ素子Ｑ１を含む回路を外付け
とすると、コストアップを招く。However, if the circuit including the active element Q1 is externally attached, the cost will increase.
ＬＰＦとしては、第５図に示すように単純なＲＣ回路を
用いることも考えられる。しかし単純ＲＣ回路では第６
図（ａ）に示すように充放電波形が鈍り、直線性が悪く
なる。具体的には出力電圧ＴＶが低位（ＯＶ近傍）、中
位（５Ｖ近傍）、高位（１０Ｖ近傍）で、選局に対する
応答速度が変化する結果を招（。充放電波形は同図ｔｂ
ｌに示すように直線的にしたいものであり、これは電源
電圧を高くすることにより可能であるが、高い電源電圧
は実際上使用しにくい。It is also conceivable to use a simple RC circuit as shown in FIG. 5 as the LPF. However, in a simple RC circuit, the 6th
As shown in Figure (a), the charge/discharge waveform becomes dull and the linearity deteriorates. Specifically, when the output voltage TV is low (near OV), medium (near 5V), and high (near 10V), the response speed to tuning changes.
It is desired to make the line linear as shown in 1. This is possible by increasing the power supply voltage, but a high power supply voltage is difficult to use in practice.
本発明は、外付は部品となるＬＰＦ部は受動素子のみと
してコスト低減を図り、またキャパシタ充放電特性はリ
ニアにして応答速度の変化がないようにしようとするも
のである。The present invention aims to reduce the cost by making the LPF section, which is an external component, only a passive element, and to make the capacitor charging/discharging characteristics linear so that there is no change in response speed.
Ｃ問題点を解決するための手段〕
第１図に示すように本発明ではＬＰＦは、抵抗Ｒｃ、Ｒ
ｄとキャパシタＣからなる受動素子のみの外付は部品と
する。そしてＰＬＬ ＩＣに定電流源スイッチＩｓ１．
Ｉｓ２ と、ＰＬＬ ＩＣ動作電ａ（５Ｖ）より高い
チューナ部ＶＤ駆動用電源（ＩＯＶ）端子を設け、Ｉｓ
ｌ及びＩｓ２は直列にしてＩＯＶ端子とグランドとの間
に接続し、直列接続点を出力端としてこれにＬＰＦの入
力端を接続する。Means for Solving Problem C] As shown in FIG.
Only the passive elements consisting of d and capacitor C are external components. Then, the constant current source switch Is1.
Is2 and a tuner section VD drive power supply (IOV) terminal higher than the PLL IC operating voltage a (5V) are provided, and Is
l and Is2 are connected in series between the IOV terminal and the ground, and the series connection point is used as an output end and the input end of the LPF is connected to this.
このようにすると前記要求は全て満たすことができる。 In this way, all of the above requirements can be met.
即ち、ＬＰＦは受動素子のみで、コスト低減が可能であ
る。また定電流■ｓｌ 、Ｉｓ２によるコンデンサＣの
充電、放電であるから、出力電圧ＴＶは第６図（ｂｌの
如く直線的になる。またＰＬＬ ＩＣにＩＯＶ端子を
設けたことでＶＤに充分な電圧を供給することができる
。That is, since the LPF is only a passive element, it is possible to reduce the cost. Also, since the capacitor C is charged and discharged by constant currents sl and Is2, the output voltage TV becomes linear as shown in Figure 6 (bl).Also, by providing the IOV terminal on the PLL IC, a sufficient voltage for VD is generated. can be supplied.
第４図の従来回路ではキャパシタＣの充電電流Ｉの最大
値（デユーティ１００％のときの電流）Ｉ ｍａｘはＩ
ｍａｘ＝５Ｖ／Ｒａになる。そこで同じ条件にするには
、電流ｆｌ Ｉ ｓ １ を５ Ｖ ／ Ｒａと同じ値
にすればよい。In the conventional circuit shown in FIG. 4, the maximum value of the charging current I of the capacitor C (current when the duty is 100%) I max is I
max=5V/Ra. Therefore, in order to maintain the same conditions, the current fl I s 1 should be set to the same value as 5 V/Ra.
また出力電圧ＴＶの変化の仕方は、従来と本発明では逆
になるので、ＰＬＬｒＣの論理を下表表 １
またサーチ速度を向上させる（受信中よりサーチ中の応
答速度は大きい方がよい）には、サーチ中の■ｓ１．■
ｓ２の電流値を大にすればよく（これで第６図のＡをＢ
にすることができる）、これはＰＬＬ ＩＣ内で簡単
に処理できる。この点も従来回路より有利である。In addition, the way the output voltage TV changes is opposite between the conventional method and the present invention, so the logic of PLLrC is shown in Table 1 below.Also, to improve the search speed (it is better to have a faster response speed during search than during reception). ■s1. is being searched. ■
All you need to do is increase the current value of s2 (this will change A to B in Figure 6).
), which can be easily handled within the PLL IC. This point is also advantageous over conventional circuits.
第２図、第３図に実施例を示す。第２図はバイポーラト
ランジスタを用いた例でＱ２はｌ１ｎｐ）ランジスタ、
Ｑ３．Ｑ４はｎｐｎトランジスタで、いずれもマルチコ
レクタ型である。制御信号Ｃ８はＯＶまたは５Ｖで、一
方、例えばＱ３の−・−スに加わる側が５■なら他方（
Ｃ４のベースに加わる側）はＯＶである。一方が５■の
ときＣ３はオン、Ｃ４従ってＣ２はオフ、これとは逆に
他方が５ＶならＣ４従ってＣ２がオン、Ｑｚがオフであ
る。Examples are shown in FIGS. 2 and 3. Figure 2 is an example using bipolar transistors, Q2 is a l1np) transistor,
Q3. Q4 is an npn transistor, both of which are multi-collector type. The control signal C8 is OV or 5V.For example, if the side that is applied to the -...- source of Q3 is 5■, the other side (
The side that joins the base of C4) is OV. When one voltage is 5V, C3 is on, C4 and therefore C2 are off, and conversely, when the other voltage is 5V, C4 and therefore C2 are on and Qz is off.
これらのトランジスタはカレントミラーを構成するので
、Ｃ３がオンなら、は＼’Ｃ３＝５Ｖを抵抗Ｒａで割っ
た電流をキャパシタＣ１抵抗Ｒｃ 、、Ｑ ３、グラン
ドの経路で流し、Ｑ−、Ｃ２オンのときはＣ３＝５Ｖを
抵抗Ｒａで割った電流をＩＯＶ、Ｃ２、Ｒｃ、Ｃ、グラ
ンドの経路で流す。これらの電流を大にするには、抵抗
Ｒａを小又は制御電圧ＣＳを大にすればよい。Ｃ４はイ
ンバータであり、これにより上記の如き制御電圧でＣ３
，Ｃ２が互いに逆にオン／オフ、及び同時にオフするよ
うになる。These transistors constitute a current mirror, so when C3 is on, a current equal to \'C3 = 5V divided by resistor Ra flows through the path of capacitor C1, resistor Rc, Q3, and ground, and Q-, C2 is on. In this case, a current obtained by dividing C3=5V by the resistor Ra is passed through the path of IOV, C2, Rc, C, and ground. In order to increase these currents, it is sufficient to reduce the resistance Ra or increase the control voltage CS. C4 is an inverter, which allows C3 to operate at the control voltage as described above.
, C2 are turned on and off oppositely to each other and turned off at the same time.
第３図はＭＯ３Ｉ−ランジスタを使用した場合で、Ｃ５
はｐチャネルＭＯ５）ランジスタ、Ｑａ、にｌ＋はｎチ
ャネルＭＯ３）ランジスタである。Ｃ６のゲートに加わ
る制御電圧Ｃ８がＨレベル（５■）のとき、Ｃ６はオン
、Ｃ７はオフ、従ってＣ５もオフで、キャパシタＣはＣ
，ＲＣ，Ｃ６の経路で放電し、該Ｃ８がＬレベル（Ｏｖ
）のときＣ６オフ、Ｑフォノ、Ｃ５オン、従ってキャパ
シタＣは１０Ｖ、Ｃ５，ＲＣ，Ｃの経路で充電される。Figure 3 shows the case where MO3I-transistor is used, and C5
is a p-channel MO5) transistor, Qa, and l+ is an n-channel MO3) transistor. When the control voltage C8 applied to the gate of C6 is at H level (5■), C6 is on, C7 is off, and therefore C5 is also off, and the capacitor C is
, RC, and C6, and C8 reaches L level (Ov
), C6 is off, Q phono, and C5 is on, so capacitor C is charged at 10V through the path of C5, RC, and C.
Ｒｅ〜Ｒｇは抵抗で、Ｒｅ、Ｒｆは制御電圧ＣＳを分圧
してトランジスタＱ６のゲートに加える。Re to Rg are resistors, and Re and Rf divide the control voltage CS and apply it to the gate of the transistor Q6.
第７図にＰＬＬ ＩＣの周辺を示す。局部発振器ＯＳ
Ｃの出力周波数が分周器１／Ｎで１／Ｈにされ、位相比
較器ＰＣにおいて基準周波数ｆｒと比較される。画周波
数の信号位相が一致していると制御電圧Ｃ８はなく （
第２図で言えばＱｔ、Ｑａ共にオフ）、ＰＬＬ ＩＣ
の出力ＴＶはない（ハイインピーダンス状態）。分周器
出力ｆｉと基準周波数ｆｒのいずれかの位相が進むと制
御電圧Ｃ８のＩｓｌ側又はＩｓ、２側がＨになり、第２
図で言えばＣ３又はＣ４とＣ２がオンになってキャパシ
タＣの放電又は充電が行なわれる。分周器の分周比は選
局したい局に応じて設定される。位相比較器ＰＣは本例
ではデジタル型である。ｆｒ、ｆｉは矩形波である。制
御信号ＣＳは位相ずれに応じたパルス幅（デユーティ）
を持つ矩形波で、位相ずれがなければデユーティ０１位
相ずれが± １８０゜であるとデユーティ１００％、そ
れ以上の位相ずれではデユーティが下ってくるが、これ
に対しては１００％で一定になるようにしている。Figure 7 shows the surroundings of the PLL IC. Local oscillator OS
The output frequency of C is set to 1/H by a frequency divider 1/N, and is compared with a reference frequency fr by a phase comparator PC. If the signal phases of the image frequency match, there is no control voltage C8 (
In Figure 2, both Qt and Qa are off), PLL IC
There is no output TV (high impedance state). When the phase of either the frequency divider output fi or the reference frequency fr advances, the Isl side or the Is,2 side of the control voltage C8 becomes H, and the second
In the figure, C3 or C4 and C2 are turned on, and the capacitor C is discharged or charged. The frequency division ratio of the frequency divider is set according to the desired station. The phase comparator PC is of the digital type in this example. fr and fi are rectangular waves. The control signal CS has a pulse width (duty) according to the phase shift.
If there is no phase shift, the duty is 100%.If the phase shift is ±180°, the duty will be 100%.If the phase shift is greater than that, the duty will decrease, but in contrast, it will remain constant at 100%. That's what I do.
以上説明したように、本発明ではチューナ部の可変容量
ダイオードに制御電圧を与えるローパスフィルタを抵抗
とキャパシタからなる受動素子のみの回路とすることが
でき、またキャパシタの充放電特性をリニアにして応答
速度に変化がないようにすることができ、甚だ有効であ
る。As explained above, in the present invention, the low-pass filter that applies the control voltage to the variable capacitance diode in the tuner section can be made into a circuit consisting only of passive elements consisting of a resistor and a capacitor, and the charging and discharging characteristics of the capacitor can be made linear to respond. It is possible to prevent the speed from changing, which is extremely effective.
第１図は本発明の要部を示す回路図、第２図および第３
図は本発明の実施例を示す回路図、第４図は従来例を示
す回路図、第５図はＲＣＬＰＦの回路図、第６図はその
充放電特性を示すグラフ、第７図はＰＬＬ ｒｃとそ
の周囲を示すブロック図である。
図面で、ＯＳＣは局部発１辰器、１／Ｎは分周器、ＰＣ
は位相比較器、ＬＰＦはローパスフィルタ、Ｉｓｌ、Ｉ
ｓ２は定電流源スイッチである。
出 願 人 富士通テン株式会社
代理人弁理士 青 柳 稔
第１図
第２図 第８国
＋０７
第４図
Ｎ６図Figure 1 is a circuit diagram showing the main parts of the present invention, Figures 2 and 3 are
Figure 4 is a circuit diagram showing an embodiment of the present invention, Figure 4 is a circuit diagram showing a conventional example, Figure 5 is a circuit diagram of RCLPF, Figure 6 is a graph showing its charge/discharge characteristics, Figure 7 is PLL rc. FIG. 2 is a block diagram showing the surrounding area. In the drawing, OSC is a local oscillator, 1/N is a frequency divider, and PC
is a phase comparator, LPF is a low-pass filter, Isl, I
s2 is a constant current source switch. Applicant Fujitsu Ten Ltd. Representative Patent Attorney Minoru Aoyagi Figure 1 Figure 2 Country 8+07 Figure 4 Figure N6
Claims (1)
周波数信号（ｆｒ）との位相差に従ってＨレベル、Ｌレ
ベル、ハイインピーダンス状態の３出力を生じるＰＬＬ
集積回路と、該集積回路の出力を受けて前記発振器の可
変容量ダイオードに対する制御電圧を出力するローパス
フィルタとを備える電子同調チューナ用制御回路におい
て、 該ローパスフィルタ（ＬＰＦ）を抵抗とキャパシタから
なる受動素子のみのフィルタとし、該ＰＬＬ集積回路に
、前記制御電圧（ＴＶ）を供給できる高い電圧の電源端
子を設け、該電源端子とグランド間に第１、第２の定電
流源スイッチ（Ｉｓ＿１、Ｉｓ＿２）を直列にして接続
し、これらのスイッチの直列接続点をＰＬＬ集積回路の
出力端とし、かつこれらのスイッチは前記位相差に従っ
て動作又は不動作状態となるようにしてなることを特徴
とする電子同調チューナ用制御回路。[Claims] A PLL that generates three outputs: H level, L level, and high impedance state according to the phase difference between a frequency-divided output frequency of a local oscillator (fi) and a reference frequency signal (fr).
A control circuit for an electronic tuning tuner comprising an integrated circuit and a low-pass filter that receives an output of the integrated circuit and outputs a control voltage for a variable capacitance diode of the oscillator, wherein the low-pass filter (LPF) is a passive filter consisting of a resistor and a capacitor. A high voltage power supply terminal capable of supplying the control voltage (TV) is provided to the PLL integrated circuit, and first and second constant current source switches (Is_1, Is_2) are connected between the power supply terminal and the ground. ) are connected in series, the series connection point of these switches is the output terminal of a PLL integrated circuit, and these switches are activated or inactivated according to the phase difference. Control circuit for tuned tuner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61155831A JP2524118B2 (en) | 1986-07-02 | 1986-07-02 | Control circuit for electronic tuning tuner |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61155831A JP2524118B2 (en) | 1986-07-02 | 1986-07-02 | Control circuit for electronic tuning tuner |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6310911A true JPS6310911A (en) | 1988-01-18 |
| JP2524118B2 JP2524118B2 (en) | 1996-08-14 |
Family
ID=15614448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61155831A Expired - Lifetime JP2524118B2 (en) | 1986-07-02 | 1986-07-02 | Control circuit for electronic tuning tuner |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2524118B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1990013673A1 (en) | 1989-05-08 | 1990-11-15 | Kawasaki Steel Corporation | Process for manufacturing unidirectional silicon steel sheet excellent in magnetic properties |
| JPH03181225A (en) * | 1989-12-11 | 1991-08-07 | Fuji Photo Film Co Ltd | Externally synchronizing programmable device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5510238A (en) * | 1978-07-07 | 1980-01-24 | Citizen Watch Co Ltd | Rll circuit |
| JPS55133619U (en) * | 1979-03-13 | 1980-09-22 | ||
| JPS5733894A (en) * | 1980-08-08 | 1982-02-24 | Matsushita Electric Ind Co Ltd | Supporting body |
| JPS5814630A (en) * | 1981-07-20 | 1983-01-27 | Nec Corp | Phase locking circuit |
| JPS58134531A (en) * | 1982-02-04 | 1983-08-10 | Oki Electric Ind Co Ltd | Loop filter for pll |
| JPS59188224A (en) * | 1983-04-08 | 1984-10-25 | Matsushita Electric Ind Co Ltd | Electronic channel selecting circuit |
| JPS59177241U (en) * | 1983-05-13 | 1984-11-27 | パイオニア株式会社 | phase comparator |
| JPS6037825A (en) * | 1983-08-10 | 1985-02-27 | Matsushita Electric Ind Co Ltd | Pll low pass filter for frequency synthesizer channel selection |
-
1986
- 1986-07-02 JP JP61155831A patent/JP2524118B2/en not_active Expired - Lifetime
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5510238A (en) * | 1978-07-07 | 1980-01-24 | Citizen Watch Co Ltd | Rll circuit |
| JPS55133619U (en) * | 1979-03-13 | 1980-09-22 | ||
| JPS5733894A (en) * | 1980-08-08 | 1982-02-24 | Matsushita Electric Ind Co Ltd | Supporting body |
| JPS5814630A (en) * | 1981-07-20 | 1983-01-27 | Nec Corp | Phase locking circuit |
| JPS58134531A (en) * | 1982-02-04 | 1983-08-10 | Oki Electric Ind Co Ltd | Loop filter for pll |
| JPS59188224A (en) * | 1983-04-08 | 1984-10-25 | Matsushita Electric Ind Co Ltd | Electronic channel selecting circuit |
| JPS59177241U (en) * | 1983-05-13 | 1984-11-27 | パイオニア株式会社 | phase comparator |
| JPS6037825A (en) * | 1983-08-10 | 1985-02-27 | Matsushita Electric Ind Co Ltd | Pll low pass filter for frequency synthesizer channel selection |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1990013673A1 (en) | 1989-05-08 | 1990-11-15 | Kawasaki Steel Corporation | Process for manufacturing unidirectional silicon steel sheet excellent in magnetic properties |
| JPH03181225A (en) * | 1989-12-11 | 1991-08-07 | Fuji Photo Film Co Ltd | Externally synchronizing programmable device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2524118B2 (en) | 1996-08-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3699301B2 (en) | Integrated circuit | |
| US4713631A (en) | Varactor tuning circuit having plural selectable bias voltages | |
| US6400231B1 (en) | Numerically controlled variable oscillator | |
| US6853257B2 (en) | PLL circuit including a voltage controlled oscillator and a method for controlling a voltage controlled oscillator | |
| US7564318B2 (en) | Switch capacitance and varactor banks applied to voltage controlled oscillator having constant frequency tuning sensitivity | |
| US5534821A (en) | Charge pump circuits for PLL frequency synthesizer | |
| US5757216A (en) | Electronic device using phase synchronous circuit | |
| US6650194B1 (en) | Phase shift control for voltage controlled oscillator | |
| US5548829A (en) | PLL circuit having a low-pass passive filter coupled to a varactor diode | |
| JPS6310911A (en) | Control circuit for electronic tuner | |
| US6590459B2 (en) | Phase lock circuit | |
| US10784875B2 (en) | Loop filter for a phase-locked loop | |
| JP3028929B2 (en) | Voltage controlled oscillator | |
| US3715604A (en) | Integrated circuit frequency divider having low power consumption | |
| JPS6010459B2 (en) | PLL circuit low-pass filter | |
| JPS5816278Y2 (en) | frequency divider | |
| JPH0644192Y2 (en) | FM-AM receiver | |
| JPH0815251B2 (en) | Electronic tuning receiver | |
| JPH07120945B2 (en) | Automatic mode switching PLL circuit | |
| JPS5811082Y2 (en) | frequency divider | |
| JP4277154B2 (en) | Voltage controlled oscillator and synthesizer receiver | |
| JPS61251314A (en) | Electronic tuning type receiver | |
| JP2923198B2 (en) | Phase locked loop | |
| JP2827307B2 (en) | PLL receiver | |
| JPS63194410A (en) | Channel selection device |