JPS6310895B2 - - Google Patents
Info
- Publication number
- JPS6310895B2 JPS6310895B2 JP57075166A JP7516682A JPS6310895B2 JP S6310895 B2 JPS6310895 B2 JP S6310895B2 JP 57075166 A JP57075166 A JP 57075166A JP 7516682 A JP7516682 A JP 7516682A JP S6310895 B2 JPS6310895 B2 JP S6310895B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon
- active region
- void
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 40
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 239000011800 void material Substances 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000012212 insulator Substances 0.000 claims description 9
- 229910021426 porous silicon Inorganic materials 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 239000008151 electrolyte solution Substances 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 36
- 238000002955 isolation Methods 0.000 description 20
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 12
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 229910017604 nitric acid Inorganic materials 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 229910003902 SiCl 4 Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000006557 surface reaction Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
本発明は高集積化、高速化、低消費電力化、高
耐圧化を目的としたデジタルおよびアナログ系の
集積回路に用いられる半導体装置の製造方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device used in digital and analog integrated circuits aimed at higher integration, higher speed, lower power consumption, and higher voltage resistance.
従来、集積回路の素子間の絶縁分離法としては
素子の周辺をSiO2膜で分離するアイソプレーナ
法、およびLOCOS法が実用になつている。一方、
素子の底面を絶縁物で分離する方法としてSOSが
実用になつている。前者については素子間を完全
に熱酸化膜で分離するためには、厚いSiO2膜を
形成する必要があり、それによつて、コレクター
埋込層の再分布が起り、又厚いSiO2膜とSi界面
での応力発生により結晶転位が発生することもあ
る。更に厚いSiO2膜とＰ形の高抵抗基板との界
面に反転層が形成されチヤネルカツト層が必要と
なる。又、選択酸化時のバーズビーク、バーズヘ
ツドの発生により集積回路の微細化、高集積化、
表面の平坦化に対する阻害要因となつている。 Conventionally, the isoplanar method, in which the periphery of the device is isolated by a SiO 2 film, and the LOCOS method have been put into practical use as insulation isolation methods between elements of integrated circuits. on the other hand,
SOS is now in practical use as a method of isolating the bottom surface of an element with an insulator. Regarding the former, in order to completely isolate the elements using a thermal oxide film, it is necessary to form a thick SiO 2 film, which causes redistribution of the buried collector layer, and Crystal dislocations may also occur due to stress generation at the interface. Furthermore, an inversion layer is formed at the interface between the thick SiO 2 film and the P-type high-resistance substrate, and a channel cut layer is required. In addition, the generation of bird's beaks and bird's heads during selective oxidation leads to miniaturization and higher integration of integrated circuits.
This is an impediment to surface flattening.
又、後者のSOS技術についてはシリコンとサフ
アイア界面での結晶転位の発生があり、適用デバ
イスがMOSに限られ、バイポーラに使うことは
困難である。更にSOSのコストが高いことも問題
である。以上のように実用になつている素子間の
絶縁分離法は多くの欠点がある。 In addition, the latter SOS technology causes crystal dislocations to occur at the interface between silicon and sapphire, and the applicable devices are limited to MOS, making it difficult to use for bipolar devices. Another problem is the high cost of SOS. As described above, the isolation method between elements that has come into practical use has many drawbacks.
本発明は通常用いられている酸化物分離のアイ
ソプレーナ法、LOCOS法では実現できなかつた
底面の絶縁化を実現し、素子領域の周囲、底面い
ずれも絶縁物分離され、素子形成領域には結晶転
位が全く無く、かつバイポーラLSI、MOSLSIお
よびBi―MOSLSIの高集積化、高性能化を実現
することを目的としたものである。 The present invention realizes bottom surface insulation that could not be achieved with the commonly used isoplanar method and LOCOS method of oxide separation.Both the periphery and bottom surface of the element region are isolated with insulators, and the element forming region has a crystalline structure. The objective is to achieve high integration and high performance of bipolar LSI, MOSLSI, and Bi-MOSLSI without any dislocations.
前記の目的を達成するため、本発明は半導体基
板上にＮ形高濃度層を形成する工程と、前記高濃
度層上にエピタキシヤルSi層を形成し、ついで前
記Si層上に酸化膜を形成する工程と、ついで前記
酸化膜上にシリコン窒化膜を堆積し、ついでレジ
ストを塗布した後、前記レジストを所望のパタン
化する工程と、前記レジストをマスクとして異方
性エツチングを施して、前記シリコン窒化膜、酸
化膜及びエピタキシヤルSi層をエツチングして、
溝を形成し、前記Ｎ形高濃度層の一部を露出する
工程と、ついで前記溝の内側にシリコン酸化膜及
び窒化膜を形成し、前記Ｎ形高濃度層の一部また
は全部を選択的にエツチングして、素子の活性化
領域直下に空隙を形成する工程と、前記溝及び空
隙をCVD法によつて絶縁物で充填する工程とを
具備することを特徴とする半導体装置の製造方法
を発明の要旨とする。 In order to achieve the above object, the present invention includes a step of forming an N-type high concentration layer on a semiconductor substrate, forming an epitaxial Si layer on the high concentration layer, and then forming an oxide film on the Si layer. Next, depositing a silicon nitride film on the oxide film, applying a resist, and patterning the resist into a desired pattern; and performing anisotropic etching using the resist as a mask to remove the silicon. Etching the nitride film, oxide film and epitaxial Si layer,
A step of forming a groove and exposing a part of the N-type high concentration layer, and then forming a silicon oxide film and a nitride film inside the groove to selectively expose part or all of the N-type high concentration layer. A method for manufacturing a semiconductor device, comprising the steps of etching to form a void directly below an active region of a device, and filling the trench and void with an insulating material by CVD. This is the gist of the invention.
次に本発明の実施例を添附図面について説明す
る。なお実施例は一つの例示であつて、本発明の
精神を逸脱しない範囲内で、種々の変更あるいは
改良を行いうることは云うまでもない。 Next, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the present invention.
第１図は本発明の実施例を示したもので、半導
体のＮ又はＰ形の高抵抗（数Ω−cm以上）基板１
ａ（図ａ参照）にＰ形又はＮ形の高濃度層（表面
濃度〜1019cm-3、接合深さ0.1〜2μｍ）２ａを、Ｐ
形の高濃度層（表面濃度〜1019cm-3、接合深さ0.5
〜1μｍ）３ａを形成する（図ｂ参照）。次にＮ形
のエピタキシヤルSi層（比抵抗0.1〜数Ω−cm、
厚み0.5〜2μｍ）４ａを形成し（図ｃ参照）、その
表面に熱酸化によりSiO2膜５ａを1000Å形成す
る。素子の接合が減圧CVD法によるSiO2に直接
接した場合、接合の電気特性がドリフトしたりリ
ーク電流が大幅に増加することがあり不安定であ
る等実用上問題があり熱酸化SiO2膜を形成した
後、減圧CVD法によるSiO2膜を堆積することが
必要となる。続いてSiO2膜上にCVD法によりシ
リコン窒化膜６ａを1000〜1500Å堆積し、レジス
ト７を塗布した後通常のフオトリソグラフイの工
程で素子周囲を絶縁する分離パターンを形成する
（図ｄ参照）。７ａはレジストを示す。次に４ａの
エピタキシヤルSi層をレジストをマスクとしてリ
アクテイブイオンエツチング法を用いてSiCl4ガ
ス中で圧力8Pa、電力0.16W/cm2で1.5μｍの深さ迄
異方性エツチングを行う（図ｅ参照）。次に表面
に露出したシリコン面を酸化し、1000〜2000Åの
SiO2膜８ａを形成し、続いて通常のCVD法によ
りシリコン窒化膜９ａを1000〜1500Å堆積する
（図ｆ参照）。次にリアクテイブイオンエツチング
法を用いてCF4ガス中で圧力4.5Pa、電力0.16W/
cm2で溝の底面部分のSiO2膜、シリコン窒化膜を
除去する（図ｇ参照）。次に弗化水素酸を含む溶
液を溝から流し、２ａのシリコン層を多孔質シリ
コン層１０ａに変質させる（図ｈ参照）。この際
１ａ，２ａ，４ａの領域の電解液に対する電極電
位差を利用して２ａのみを多孔質化させる。次
に、多孔質シリコン層１０ａと１ａ，４ａとのウ
エツトエツチング又はドライエツチング速度の差
が数桁のオーダ異なることを利用して、多孔質シ
リコン層１０ａのみ除去し、Ｎ形エピタキシヤル
層４ａの底面に空隙１１ａを形成する。多孔質Si
を形成して除去する特徴は多孔質シリコンは厚く
形成することが可能なため空隙の幅を大きくでき
素子底面の寄生容量を低減したり又高耐圧化した
りする場合は後に述べる実施例２より有利となる
（図ｉ参照）。第２図にｉ図の俯瞰図を示した。こ
れにより、断面に垂直方向の両端で素子領域部が
固定されており、素子部が遊離することはない。
次に、空隙を利用して、通常のドープトオキサイ
ド法により４ａの底面から砒素を拡散させ、コレ
クター埋込層１２ａを形成する（図ｊ参照）。コ
レクター埋込層の抵抗を低下させるためにはシリ
サイド化を素子底面の空隙を利用して行うことも
可能である。次に減圧CVD法でSiO2膜１３ａを
堆積し、溝および空隙を充填し、高分子膜又は
PSG膜を塗布しリアクテイブイオンエツチング
法を用いて、CF4ガス中で圧力4.5Pa、電力0.16
Ｗ／cm2でエツチングを行い、表面平坦化を行う
（図ｋ参照）。次に、図ｋに示された断面に垂直方
向の素子周囲の素子間分離はリアクテイブイオン
エツチング法を利用して異方性のエツチングを行
い溝を形成し、図ｋで説明した同じ方法でその溝
を減圧CVD法によるSiO2膜によつて充填し更に
表面平坦化を行う。 FIG. 1 shows an embodiment of the present invention, in which a semiconductor N or P type high resistance (several Ω-cm or more) substrate 1
A (see figure a) is a P-type or N-type high concentration layer (surface concentration ~10 19 cm -3 , junction depth 0.1-2 μm) 2a, P
A highly concentrated layer of the shape (surface concentration ~10 19 cm -3 , junction depth 0.5
~1 μm) to form 3a (see figure b). Next, an N-type epitaxial Si layer (specific resistance 0.1 to several Ω-cm,
A SiO 2 film 5a having a thickness of 1000 Å is formed on its surface by thermal oxidation. If the junction of the device is in direct contact with SiO 2 formed by low-pressure CVD, there are practical problems such as drift in the electrical properties of the junction and a significant increase in leakage current, resulting in instability. After formation, it is necessary to deposit a SiO 2 film by low pressure CVD. Next, a silicon nitride film 6a with a thickness of 1000 to 1500 Å is deposited on the SiO 2 film by the CVD method, and after a resist 7 is applied, an isolation pattern is formed to insulate the periphery of the element using a normal photolithography process (see Figure d). . 7a indicates a resist. Next, using the resist as a mask, the epitaxial Si layer 4a is anisotropically etched to a depth of 1.5 μm in SiCl 4 gas at a pressure of 8 Pa and a power of 0.16 W/cm 2 (Fig. (see e). Next, the silicon surface exposed on the surface is oxidized to form a 1000 to 2000 Å
A SiO 2 film 8a is formed, and then a silicon nitride film 9a is deposited to a thickness of 1000 to 1500 Å by the usual CVD method (see FIG. f). Next, using the reactive ion etching method, we used CF4 gas at a pressure of 4.5Pa and a power of 0.16W/
Remove the SiO 2 film and silicon nitride film at the bottom of the groove with a vacuum of 2 cm 2 (see Figure g). Next, a solution containing hydrofluoric acid is flowed through the groove to transform the silicon layer 2a into a porous silicon layer 10a (see Figure h). At this time, only 2a is made porous using the electrode potential difference with respect to the electrolytic solution in the regions 1a, 2a, and 4a. Next, taking advantage of the fact that the difference in wet etching or dry etching speed between the porous silicon layer 10a and 1a, 4a is several orders of magnitude different, only the porous silicon layer 10a is removed, and the N-type epitaxial layer 4a is removed. A void 11a is formed at the bottom surface of the space. Porous Si
The feature of forming and removing porous silicon is that it can be formed thickly, so the width of the gap can be increased, and when the parasitic capacitance at the bottom of the element is reduced or the breakdown voltage is increased, this method is more advantageous than Example 2, which will be described later. (See Figure i). Figure 2 shows an overhead view of Figure i. As a result, the element region portion is fixed at both ends in the direction perpendicular to the cross section, and the element portion will not come loose.
Next, using the void, arsenic is diffused from the bottom surface of 4a by a normal doped oxide method to form a collector buried layer 12a (see FIG. J). In order to lower the resistance of the collector buried layer, it is also possible to perform silicide using the voids at the bottom of the element. Next, a SiO 2 film 13a is deposited using a low pressure CVD method, filling the grooves and voids, and depositing a polymer film or
PSG film was applied and reactive ion etching was applied, and the pressure was 4.5 Pa and the power was 0.16 in CF4 gas.
Perform etching at W/cm 2 to flatten the surface (see Figure k). Next, the isolation between the elements around the elements in the direction perpendicular to the cross section shown in Figure k is achieved by performing anisotropic etching using the reactive ion etching method to form grooves, and using the same method explained in Figure K. The grooves are filled with a SiO 2 film by low-pressure CVD, and the surface is further flattened.
以上で素子の周囲および底面がSiO2で完全分
離される。従つて、素子底面の寄生容量が低減出
来ると同時に素子間の高耐圧化が可能となる特徴
がある。以後の素子形成工程は通常の方法と同じ
である。バイポーラの素子形成後の断面構造を図
ｌに示した。図中１２ａはコレクター埋込層、１
４ａはベース層、１５ａはエミツタ層、１６ａは
金属配線、１７ａはシリコン熱酸化膜を示す。 With the above steps, the periphery and bottom surface of the element are completely isolated by SiO 2 . Therefore, it is possible to reduce the parasitic capacitance at the bottom of the element, and at the same time, it is possible to increase the breakdown voltage between the elements. The subsequent element forming steps are the same as the usual method. Figure 1 shows the cross-sectional structure of the bipolar device after it has been formed. In the figure, 12a is a collector buried layer, 1
4a is a base layer, 15a is an emitter layer, 16a is a metal wiring, and 17a is a silicon thermal oxide film.
本実施例ではエピタキシヤル層の厚さは0.5〜
2μｍと薄いが、更に厚くなつた場合でも同様の
完全分離構造が得られ高耐圧の素子分離が可能と
なる。 In this example, the thickness of the epitaxial layer is 0.5~
Although it is thin at 2 μm, even if it becomes thicker, a similar complete isolation structure can be obtained and element isolation with high breakdown voltage is possible.
第３図は本発明の実施例２を示したもので、半
導体シリコン基板Ｎ又はＰ形の数Ω−cm以上の高
抵抗基板１（図ａ参照）にＮ形の高濃度層（表面
濃度〜1019cm-3、接合深さ0.1〜2μｍ）２を形成す
る（図ｂ参照）。この高濃度層はエピタキシヤル
層を使わないで高エネルギーイオン注入法でも形
成が可能である。次にＮ形のエピタキシヤル層
（比抵抗0.1〜数Ω−cm、厚み0.5〜2μｍ）３を形
成し（図ｃ参照）、その表面に熱酸化膜４を1000
Å形成する。この熱酸化膜を形成する効果は実施
例１と同じである。続いてSiO2上にCVD法によ
りシリコン窒化膜５を1000〜1500Å堆積し、レジ
スト６を塗布した後通常のフオトリソグラフイの
工程で素子周囲を絶縁する分離パターンを形成す
る（図ｄ参照）。次に３の絶縁分離する領域をレ
ジスト６をマスクとしてリアクテイブイオンエツ
チング法で異方性エツチングを行う（図ｅ参照）。
次に、表面に露出したシリコン面を酸化し、1000
〜2000ÅのSiO2膜７を形成し、続いてCVD法に
よりシリコン窒化膜８を1000〜1500Å堆積する
（図ｆ参照）。次に、リアクテイブイオンエツチン
グ法で溝の底面部分のSiO2膜とシリコン窒化膜
を除去する（図ｇ参照）。次に弗酸、硝酸、酢酸
の体積比を１：３：８に混合し、液温20℃に保ち
ながら超音波を印加しながらエツチングを行い、
続いて１：３：７液で同じ方法でエツチングし、
続いて１：３：６液で２の高濃度層のみをエツチ
ングし、図に示したような、横方向に水平な形状
をもつ空隙９を形成する（図ｈ参照）。使用した
エツチヤントは浅野、住友、村岡、大橋等により
昭和48年４月の半導体・集積回路の生産技術第４
回シンポジウムで報告されており、酢酸容量比を
変えることによりシリコンのエツチレートの比抵
抗依存性を大幅に変化させられる。 Embodiment 2 of the present invention is shown in FIG. 3, in which an N-type high concentration layer (surface concentration ~ 10 19 cm -3 , junction depth 0.1-2 μm) 2 (see Figure b). This high concentration layer can also be formed by high energy ion implantation without using an epitaxial layer. Next, an N-type epitaxial layer (specific resistance 0.1 to several Ω-cm, thickness 0.5 to 2 μm) 3 is formed (see Figure c), and a thermal oxide film 4 is deposited on its surface to a thickness of 1,000 Ω.
Å form. The effect of forming this thermal oxide film is the same as in the first embodiment. Subsequently, a silicon nitride film 5 is deposited to a thickness of 1000 to 1500 Å on the SiO 2 by the CVD method, and after a resist 6 is applied, an isolation pattern for insulating the periphery of the element is formed by a normal photolithography process (see FIG. d). Next, the regions 3 to be insulated and separated are anisotropically etched by reactive ion etching using the resist 6 as a mask (see Figure e).
Next, the exposed silicon surface is oxidized to 1000
A SiO 2 film 7 of ~2000 Å is formed, and then a silicon nitride film 8 of 1000 to 1500 Å is deposited by CVD (see Figure f). Next, the SiO 2 film and silicon nitride film at the bottom of the trench are removed using reactive ion etching (see Figure g). Next, hydrofluoric acid, nitric acid, and acetic acid were mixed in a volume ratio of 1:3:8, and etching was performed while applying ultrasonic waves while keeping the liquid temperature at 20°C.
Next, etch in the same manner with 1:3:7 solution,
Subsequently, only the high concentration layer 2 is etched using a 1:3:6 solution to form voids 9 having a horizontal shape as shown in the figure (see figure h). The etchants used were published in April 1971 by Asano, Sumitomo, Muraoka, Ohashi, etc.
It was reported at the 2017 Symposium that by changing the acetic acid capacity ratio, the dependence of silicon etching rate on resistivity can be significantly changed.
次に空隙と溝を利用して、通常のドープトオキ
サイド法で素子底面にAsを含むCVD SiO2膜堆
積させ熱処理を1000℃で行ないＮ形（砒素）の高
濃度層１０を形成する（図ｉ参照）。又、コレク
ター埋込層となる１０の抵抗を低下させるために
シリサイドを作ることは当然可能となる。即ち高
融点金属を減圧CVD法で素子底面に堆積させ熱
処理することにより可能となる。 Next, using the voids and grooves, a CVD SiO 2 film containing As is deposited on the bottom surface of the device using the usual doped oxide method, and heat treatment is performed at 1000°C to form a highly concentrated N-type (arsenic) layer 10 (Fig. (see i). Furthermore, it is naturally possible to make silicide in order to lower the resistance of the collector buried layer 10. That is, this can be achieved by depositing a high-melting point metal on the bottom surface of the element using a low-pressure CVD method and heat-treating it.
次に、減圧CVD法でSiO2膜１１を堆積し、溝
および空隙を充填し、実施例１と同じ方法で表面
の平坦化を行う（図ｊ参照）。次に第３図のｊに
示された断面に垂直方向の素子間分離は第３図の
ｄからｆ迄説明した同じ方法で溝を形成した後、
第３図のｊで説明した同じ方法により減圧CVD
法のSiO2膜によつて充填し、表面平坦化を行う。 Next, a SiO 2 film 11 is deposited by low pressure CVD to fill the grooves and voids, and the surface is flattened by the same method as in Example 1 (see FIG. J). Next, the isolation between the elements in the direction perpendicular to the cross section shown in FIG.
Reduced pressure CVD using the same method explained in Figure 3 j.
Fill with SiO 2 film according to the method and flatten the surface.
以上で素子の周囲および底面が全てSiO2で分
離され、完全分離構造が得られたことになる。こ
の効果は実施例１と同じである。以後の素子形成
工程は通常の方法と同じである。素子形成後の断
面構造を第３図ｋに示した。図中１２ａはベー
ス、１３ａはソース、１４ａはエミツタ、１５ａ
は金属配線を示す。 With the above steps, the periphery and bottom of the device are all separated by SiO 2 , and a completely isolated structure has been obtained. This effect is the same as in the first embodiment. The subsequent element forming steps are the same as the usual method. The cross-sectional structure after device formation is shown in FIG. 3k. In the figure, 12a is the base, 13a is the source, 14a is the emitter, 15a
indicates metal wiring.
第４図は本発明の実施例３を示したものであ
り、溝を形成するまでの工程は実施例２のａから
ｇまでの工程と同一である。次に弗酸、硝酸、酢
酸の体積混合比が１：３：６のエツチング液の１
種のみを用い、超音波約28KHzを印加しながらエ
ツチングを行ない第４図ａに示したような横方向
に傾きをもつた形状をもつ空隙９を形成する。こ
のような形状をもつことによりCVD SiO2膜で容
易に空隙が充填される特徴があると同時に、熱処
理に伴なうシリコン単結晶島に与える応力効果が
緩和され素子領域部の彎曲がなくなる特徴があ
り、結晶歪の発生がなくなる。次にコレクター埋
込層に相当するＮ形高濃度層１０を実施例２と同
じ方法で溝と空隙を利用して素子の活性領域の底
面から形成する（図ａ参照）。次に減圧CVD法で
SiO2膜１１を堆積し、溝および空隙を充填し実
施例１と同じ方法で表面平坦化を行う（図ｂ参
照）。続いて、試料断面に垂直な方向の素子分離
のための溝を形成し、減圧CVD法でSiO2膜を堆
積し、溝を充填して完全分離工程が完成する。こ
れ以後の素子形成工程は従来法と同じである。素
子形成後の断面図を図ｃに示した。 FIG. 4 shows Example 3 of the present invention, and the steps up to forming the grooves are the same as steps a to g of Example 2. Next, use an etching solution with a volume mixing ratio of hydrofluoric acid, nitric acid, and acetic acid of 1:3:6.
Using only the seeds, etching is performed while applying ultrasonic waves of approximately 28 KHz to form voids 9 having a shape inclined laterally as shown in FIG. 4a. This shape allows the voids to be easily filled with the CVD SiO 2 film, and at the same time, the stress effect on the silicon single crystal islands due to heat treatment is alleviated, eliminating curvature in the device region. This eliminates the occurrence of crystal distortion. Next, an N-type heavily doped layer 10 corresponding to a collector buried layer is formed from the bottom of the active region of the device using the same method as in Example 2, using the grooves and gaps (see Figure a). Next, by low pressure CVD method
A SiO 2 film 11 is deposited to fill the grooves and voids, and the surface is flattened in the same manner as in Example 1 (see Figure b). Next, grooves for element isolation are formed in a direction perpendicular to the cross section of the sample, and a SiO 2 film is deposited by low-pressure CVD to fill the grooves, completing the complete isolation process. The subsequent element forming steps are the same as the conventional method. A cross-sectional view after forming the element is shown in Figure c.
第５図は本発明の実施例４を示したものであ
る。溝を形成する迄の工程は実施例２のａからｇ
迄の工程と同一である。次に空隙を形成する際素
子領域の底面を完全にエツチングしないで、素子
の中央部に半導体基板と素子の活性領域とを連結
するためのシリコン２４を残す。次にコレクター
埋込層に相当する高濃度層１０を実施例２と同じ
方法で溝と空隙を利用して素子領域の底面から形
成する（図ａ参照）。次に熱酸化法で素子領域の
底面に残されたシリコン２４を高圧酸化法で1000
℃で完全に酸化する。次に実施例３と同じ方法で
溝及び空隙を減圧CVD法によるSiO2膜で充填し
表面平坦化を行う（図ｂ参照）。以上の工程で素
子形成領域の周囲および底面の完全分離が完成す
る。実施例３と異なる点は空隙を作る際素子底面
に一部シリコンを残すため、溝と空隙形成で素子
分離が１回の作業で完了する点である。この構造
によつて現われる効果は実施例１と同じである。
これ以後の素子形成工程は従来法と同じである。
素子形成後の断面図を図ｃに示した。 FIG. 5 shows a fourth embodiment of the present invention. The steps up to forming the grooves are from a to g in Example 2.
The process is the same as the previous one. Next, when forming a gap, the bottom surface of the device region is not completely etched, leaving silicon 24 in the center of the device to connect the semiconductor substrate and the active region of the device. Next, a high concentration layer 10 corresponding to a collector buried layer is formed from the bottom surface of the element region using the grooves and voids in the same manner as in Example 2 (see Figure a). Next, the silicon 24 left on the bottom of the element area was removed by thermal oxidation using high-pressure oxidation.
Completely oxidizes at ℃. Next, in the same manner as in Example 3, the grooves and voids are filled with a SiO 2 film by low pressure CVD to flatten the surface (see Figure b). Through the above steps, complete isolation of the periphery and bottom surface of the element formation region is completed. The difference from Embodiment 3 is that when creating a gap, a portion of silicon is left on the bottom surface of the element, so element isolation can be completed in one operation by forming the groove and the gap. The effects produced by this structure are the same as in the first embodiment.
The subsequent element forming steps are the same as the conventional method.
A cross-sectional view after forming the element is shown in Figure c.
第６図は本発明の実施例５を示したものであ
り、横方向に傾きをもつた形状の空隙を形成する
迄の工程は実施例４と同じである。弗酸、硝酸、
酢酸の体積比が１：３：６のエツチング液でエツ
チング液の超音波による撹拌更にエツチング時間
のコントロールにより歩留りよくシリコンを素子
の底面に一部残すことが可能となる（図ａ参照）。
次に実施例３と同一の方法で溝と空隙を減圧
CVD法によりSiO2膜で充填する（図ｂ参照）。試
料断面に垂直方向の分離は実施例４と同じく溝と
空隙形成で１回の作業で完了する。これは素子中
央部にシリコンを残したために可能となるもので
ある。次に通常のイオン注入法でＰチヤネル、Ｎ
チヤネルのCMOSトランジスタを形成する。素
子完成断面図を図ｃに示す。図中１６は金属配
線、１８はＰ形高濃度層（ソース）、１９はＮ形
領域、２０はＰ形高濃度層（ドレイン）、２１は
Ｎ形高濃度層（ソース）、２２はＰ形領域、２３
はＮ形高濃度層（ドレイン）を示す。本実施例に
おいて、接合の側面、底面が絶縁物で接している
ため接合寄生容量が減少する効果があり、更に完
全誘電体分離になつていないため素子領域がフロ
ーテイングにならないので電位変動がなくなる特
徴がある。 Embodiment 5 of the present invention is shown in FIG. 6, and the steps up to forming a void having a shape inclined in the lateral direction are the same as in Embodiment 4. Hydrofluoric acid, nitric acid,
By using an etching solution with an acetic acid volume ratio of 1:3:6, stirring the etching solution using ultrasonic waves, and controlling the etching time, it is possible to leave a portion of the silicon on the bottom surface of the element with a good yield (see Figure a).
Next, the groove and void were depressurized using the same method as in Example 3.
Fill with SiO 2 film by CVD method (see Figure b). Separation in the direction perpendicular to the cross section of the sample is completed in one operation by forming grooves and voids, as in Example 4. This is possible because silicon is left in the center of the element. Next, P channel, N
Form a channel CMOS transistor. A cross-sectional view of the completed device is shown in Figure c. In the figure, 16 is a metal wiring, 18 is a P-type high concentration layer (source), 19 is an N-type region, 20 is a P-type high concentration layer (drain), 21 is an N-type high concentration layer (source), and 22 is a P-type area, 23
indicates an N-type high concentration layer (drain). In this example, the side and bottom surfaces of the junction are in contact with an insulator, which has the effect of reducing the junction parasitic capacitance.Furthermore, since complete dielectric isolation is not achieved, the element area does not float, eliminating potential fluctuations. It has characteristics.
第７図は本発明の実施例６を示した。横方向に
傾きをもつ形状の空隙を形成する迄の工程は実施
例３と同じである（第７図ａ参照）。次に実施例
３で示した同一の方法で溝および空隙を減圧
CVD法によるSiO2膜で充填し、表面平坦化を行
う（図ｂ参照）。次に、試料断面に垂直方向の素
子間分離のための溝を形成し、減圧CVD SiO2膜
を堆積し、溝を充填して完全分離工程が完成す
る。次に通常のイオン注入法でＰチヤネル、Ｎチ
ヤネルのMOSトランジスタを形成する。素子完
成断面図を図ｃに示す。図中１６は金属配線、１
８はＰ形高濃度層（ソース）、１９はＮ形領域、
２０はＰ形高濃度層（ドレイン）、２１はＮ形高
濃度層（ソース）、２２はＰ形領域、２３はＮ形
高濃度層（ドレイン）を示す。この構造により接
合の側面、底面が絶縁物で接しているため接合寄
生容量が低減できる特徴がある。本実施例は実施
例５と比べ素子間に高耐圧が要求される場合には
その効果が現われる。 FIG. 7 shows Example 6 of the present invention. The steps up to forming the void having a shape inclined in the lateral direction are the same as in Example 3 (see FIG. 7a). Next, the grooves and voids were depressurized using the same method as shown in Example 3.
Fill with SiO 2 film by CVD method and flatten the surface (see Figure b). Next, grooves for vertical element isolation are formed in the cross section of the sample, and a low-pressure CVD SiO 2 film is deposited to fill the grooves, completing the complete isolation process. Next, P channel and N channel MOS transistors are formed using a normal ion implantation method. A cross-sectional view of the completed device is shown in Figure c. In the figure, 16 is metal wiring, 1
8 is a P-type high concentration layer (source), 19 is an N-type region,
20 is a P-type high concentration layer (drain), 21 is an N-type high concentration layer (source), 22 is a P-type region, and 23 is an N-type high concentration layer (drain). This structure has the characteristic that the junction parasitic capacitance can be reduced because the side and bottom surfaces of the junction are in contact with an insulator. Compared to the fifth embodiment, this embodiment is more effective when a high breakdown voltage is required between elements.
次に、完全誘電体分離を実現する上で実施例
２、３、４、６において、充填用の絶縁物材料と
しては、熱伝導率が良くて且つ絶縁性の良いもの
が要求される。従つて、実施例７として、溝およ
び空隙を形成した後、減圧CVD法でSiO2膜を
1000Å堆積し、次に13.56MHzを用いたグロー放
電法でNH3を分解し、プラズマ領域以外の部分
からAl（CH3）3を供給し、表面反応によつてAlN
膜を堆積させる。試料基板温度は700℃に保つて
おく。このAlN膜の使用により溝と空隙を充填
し、熱伝導率がSiO2膜のそれに比べ約２桁近く
改善される。 Next, in order to realize complete dielectric isolation, in Examples 2, 3, 4, and 6, the filling insulating material is required to have good thermal conductivity and good insulation. Therefore, as Example 7, after forming grooves and voids, a SiO 2 film was formed by low pressure CVD method.
After depositing 1000 Å, NH 3 is decomposed by a glow discharge method using 13.56 MHz, Al(CH 3 ) 3 is supplied from a part other than the plasma region, and AlN is formed by a surface reaction.
Deposit the film. Keep the sample substrate temperature at 700℃. By using this AlN film, the grooves and voids are filled, and the thermal conductivity is improved by about two orders of magnitude compared to that of the SiO 2 film.
以上説明したように、本発明によれば
(イ) エピタキシヤル層形成後、素子領域の周囲に
溝を、底面に空隙を形成した後、素子の底面か
らコレクタ埋込層を形成するため、Ｎ形高濃度
領域の再拡散が抑制され、エピタキシヤル層を
薄く出来LSIの高性能化がはかれる。 As explained above, according to the present invention, (a) after forming an epitaxial layer, forming a groove around the element region and forming a gap on the bottom surface, a collector buried layer is formed from the bottom surface of the element; This suppresses re-diffusion in the high-concentration region, making the epitaxial layer thinner and improving the performance of the LSI.
(ロ) 素子の周囲、底面の絶縁をSiO2膜の堆積に
より行うため分離の寄生容量が低減できると同
時に単結晶シリコンを酸化する場合の応力発生
はなく、素子が形成される単結晶領域の結晶転
位の発生がなくバイポーラLSI、MOS―LSI、
Bi―MOS LSIに適用され、その高性能化が図
れる。(b) Insulating the periphery and bottom of the device by depositing a SiO 2 film reduces the parasitic capacitance of isolation, and eliminates the stress that occurs when oxidizing single-crystal silicon. Bipolar LSI, MOS-LSI, with no crystal dislocations,
It can be applied to Bi-MOS LSI to improve its performance.
(ハ) 素子の周囲、底面がSiO2膜で分離されるた
めチヤネルカツト拡散が不必要となる。又、コ
レクター埋込マスクが不要である。(c) Since the periphery and bottom of the element are separated by the SiO 2 film, channel cut diffusion becomes unnecessary. Furthermore, a collector embedded mask is not required.
(ニ) 素子周囲の分離幅はドライエツチングで任意
に選択出来るため、その微細化がはかれる。(d) Since the isolation width around the element can be arbitrarily selected by dry etching, it can be miniaturized.
(ホ) 以上の多くのメリツトによつて集積回路の高
集積化、高性能化がはかれる。(e) Many of the above advantages enable higher integration and higher performance of integrated circuits.
等の効果を有するものである。It has the following effects.
なお、現在までに発表されている素子間分離法
で分離島の底面が絶縁物のものとしては
(イ) SOI（Silicon on Insulator）
SOIはSi／SiO2／Si構造からなつている。最
上Si層中にSi転位が108−109個cm-2程度存在す
る。従つて、長チヤネルMOSデバイスにしか
適用できない。 Note that among the device isolation methods that have been announced so far, the bottom surface of the isolation island is an insulator: (a) SOI (Silicon on Insulator) SOI has a Si/SiO 2 /Si structure. There are approximately 10 8 −10 9 Si dislocations cm -2 in the topmost Si layer. Therefore, it can only be applied to long channel MOS devices.
(ロ) SOS（Silicon on Sapphire）
SOSはSi／Al2O3構造である。この構造はヘ
テロエピタキシヤル成長を利用しており、格子
不整合、熱膨張係数の違い、Siと基板Al2O3と
の界面でのAl原子、Si原子の相互拡散等があ
り、Si中の転位が多く発生する。このため、こ
の構造も長チヤネルのMOSデバイスにしか適
用できない。(b) SOS (Silicon on Sapphire) SOS has a Si/Al 2 O 3 structure. This structure uses heteroepitaxial growth, and there are lattice mismatches, differences in thermal expansion coefficients, and interdiffusion of Al and Si atoms at the interface between Si and the substrate Al 2 O 3 . Many dislocations occur. Therefore, this structure is also applicable only to long channel MOS devices.
(ハ) EPIC法
この方法はバイポーラ、MOS系の高耐圧デ
バイス用に使用されているが、プロセスが非常
に煩雑であるとか、LSIプロセスとは整合性が
悪いこと、製造歩留まりが低く、コストが高く
なる欠点がある。(c) EPIC method This method is used for bipolar and MOS high voltage devices, but the process is very complicated, it is not compatible with the LSI process, the manufacturing yield is low, and the cost is high. It has the disadvantage of being expensive.
しかるに本発明の製造方法によれば、Si活性層
直下中に予め形成した空隙中に所望の絶縁物を充
填する方式であり、歪み発生等の防止制御が可能
となる。従つて、活性Si領域中には転位などの結
晶欠陥の発生を完全になくすことができる大きな
特徴がある。今までのLSIプロセスを用いて、バ
イポーラ、MOS、Bi―CMOS等の微細デバイス
を用いた超LSIが低コストで実現できる。 However, according to the manufacturing method of the present invention, a desired insulator is filled into a gap formed in advance directly under the Si active layer, and it is possible to prevent the occurrence of distortion and the like. Therefore, the active Si region has the great feature of completely eliminating the occurrence of crystal defects such as dislocations. Using conventional LSI processes, ultra-LSIs using fine devices such as bipolar, MOS, and Bi-CMOS can be realized at low cost.
空隙形成法は高濃度Si層を予め、多孔質化した
後、除去する方法と、Ｎ形高濃度層を直接エツチ
ングする方法とがある。前者は活性素子面積が比
較的大きい場合に、後者は活性素子面積が小さい
場合に適しているものである。 There are two methods for forming voids: a method in which the high-concentration Si layer is made porous in advance and then removed, and a method in which the N-type high-concentration layer is directly etched. The former is suitable when the active element area is relatively large, and the latter is suitable when the active element area is small.
第１図ａ〜ｌは本発明の実施例を示す各工程の
半導体装置の断面図、第２図は第１図ｉの俯瞰
図、第３図ａ〜ｋ、第４図ａ〜ｃ、第５図ａ〜
ｃ、第６図ａ〜ｃ、第７図ａ〜ｃは夫夫他の実施
例を示す各工程の半導体装置の断面図を示す。
１ａ……半導体基板、２ａ，３ａ……Ｐ形又Ｎ
形高濃度層、４ａ……Ｎ形エピタキシヤル層、５
ａ……SiO2膜、６ａ……シリコン窒化膜、７ａ
……レジスト、８ａ……SiO2膜、９ａ……シリ
コン窒化膜、１０ａ……多孔質シリコン層、１１
ａ……空隙、１２ａ……Ｎ形高濃度層又はコレク
タ埋込層、１３ａ……CVD法によるSiO2膜、１
４ａ……コレクタ補償層、１５ａ……ベース層、
１６ａ……エミツタ層、１７ａ……金属配線、１
８ａ……コレクター層、１……半導体基板、２…
…Ｎ形高濃度層、３……Ｎ形エピタキシヤル層、
４……SiO2膜、５……シリコン窒化膜、６……
レジスト、７……SiO2膜、８……シリコン窒化
膜、９……空隙、１０……Ｎ形高濃度層、１１…
…CVD法によるSiO2膜、１２……コレクタ補償
層、１３……コレクター層、１４……ベース層、
１５……エミツタ層、１６……金属配線、１７…
…シリコン熱酸化膜、１８……Ｐ形高濃度層（ソ
ース）、１９……Ｎ形領域、２０……Ｐ形高濃度
層（ドレイン）、２１……Ｎ形高濃度層（ソー
ス）、２２……Ｐ形領域、２３……Ｎ形高濃度層
（ドレイン）、２４……シリコンの連結部。
1a to l are cross-sectional views of a semiconductor device at each step showing an embodiment of the present invention, FIG. 2 is an overhead view of FIG. 1i, FIGS. 3a to k, FIGS. Figure 5 a~
6c, 6a to 7c, and 7a to 7c show cross-sectional views of the semiconductor device at each step of the embodiment of Huo et al. 1a...semiconductor substrate, 2a, 3a...P type or N
type high concentration layer, 4a...N type epitaxial layer, 5
a...SiO 2 film, 6a... Silicon nitride film, 7a
...Resist, 8a...SiO 2 film, 9a...Silicon nitride film, 10a...Porous silicon layer, 11
a...Void, 12a...N-type high concentration layer or collector buried layer, 13a...SiO 2 film by CVD method, 1
4a... Collector compensation layer, 15a... Base layer,
16a... Emitter layer, 17a... Metal wiring, 1
8a...Collector layer, 1...Semiconductor substrate, 2...
...N-type high concentration layer, 3...N-type epitaxial layer,
4... SiO 2 film, 5... Silicon nitride film, 6...
Resist, 7... SiO2 film, 8...Silicon nitride film, 9...Void, 10...N-type high concentration layer, 11...
... SiO 2 film by CVD method, 12 ... Collector compensation layer, 13 ... Collector layer, 14 ... Base layer,
15... Emitter layer, 16... Metal wiring, 17...
...Silicon thermal oxide film, 18...P type high concentration layer (source), 19...N type region, 20...P type high concentration layer (drain), 21...N type high concentration layer (source), 22 . . . P type region, 23 . . . N type high concentration layer (drain), 24 . . . Silicon connection portion.
Claims (1)
工程と、 (ロ) 前記高濃度層上にエピタキシヤルSi層を形成
し、ついで前記Si層上に酸化膜を形成する工程
と、 (ハ) ついで前記酸化膜上にシリコン窒化膜を堆積
し、ついでレジストを塗布した後、前記レジス
トを所望のパタン化する工程と、 (ニ) 前記レジストをマスクとして異方性エツチン
グを施して、前記シリコン窒化膜、酸化膜及び
エピタキシヤルSi層をエツチングして、溝を形
成し、前記Ｎ形高濃度層の一部を露出する工程
と、 (ホ) ついで前記溝の内側にシリコン酸化膜及び窒
化膜を形成し、前記Ｎ形高濃度層の一部または
全部を選択的にエツチングして、素子の活性化
領域直下に空隙を形成する工程と、 (ヘ) 前記溝及び空隙をCVD法によつて絶縁物で
充填する工程 とを具備することを特徴とする半導体装置の製造
方法。 ２ 前記の溝から電解液を供給し、シリコン半導
体基板のある深さの層を全面又は部分的に多孔質
シリコン層を形成し、エツチングにより多孔質シ
リコンを除去し、素子の活性領域の直下に空隙を
形成し、前記の溝および空隙をCVD法によつて
絶縁物で充填することを特徴とする特許請求の範
囲第１項記載の半導体装置の製造方法。 ３ 前記の空隙と溝を利用して素子の活性領域の
底面からコレクター埋込層を形成することを特徴
とする特許請求の範囲第１項又は第２項記載の半
導体装置の製造方法。 ４ 前記の素子の活性領域の底面にシリサイドを
形成することを特徴とする特許請求の範囲第１項
記載の半導体装置の製造方法。 ５ 前記の素子の活性領域の底面全部に空隙を作
らずに、半導体基板と素子の活性領域とを連結す
るためのシリコンを一部残した形で溝および空隙
を作り、前記の溝および空隙をCVD法により絶
縁物で充填することを特徴とする特許請求の範囲
第１項記載の半導体装置の製造方法。 ６ 前記の素子の活性領域の底面全部に空隙を作
らずに、半導体基板と素子の活性領域とを連結す
るためのシリコンを一部残し、これを熱酸化によ
り酸化物にした後、溝および空隙をCVD法によ
り絶縁物で充填することを特徴とする特許請求の
範囲第５項記載の半導体装置の製造方法。 ７ 前記の素子の活性領域の底面全部に空隙を作
らずに、半導体基板と素子の活性領域とを連結す
るためのシリコンを一部残した形で溝および横方
向に傾きのある空隙を形成し、前記の溝および空
隙をCVD法により絶縁物で充填することを特徴
とする特許請求の範囲第１項記載の半導体装置の
製造方法。[Claims] 1. (a) forming an N-type high concentration layer on a semiconductor substrate; (b) forming an epitaxial Si layer on the high concentration layer, and then forming an oxide film on the Si layer. (c) Next, depositing a silicon nitride film on the oxide film, then applying a resist, and patterning the resist into a desired pattern; (d) Anisotropic patterning using the resist as a mask. (e) etching the silicon nitride film, oxide film and epitaxial Si layer to form a groove and exposing a part of the N-type high concentration layer; (f) forming a silicon oxide film and a nitride film on the inside, and selectively etching a part or all of the N-type high concentration layer to form a void directly under the active region of the device; and a step of filling the void with an insulator by a CVD method. 2. Supply an electrolytic solution from the groove, form a porous silicon layer on the entire or partial layer of a certain depth of the silicon semiconductor substrate, remove the porous silicon by etching, and deposit the porous silicon layer directly under the active region of the device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a void is formed, and the trench and void are filled with an insulating material by CVD. 3. The method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that the collector buried layer is formed from the bottom surface of the active region of the element using the voids and grooves. 4. The method of manufacturing a semiconductor device according to claim 1, characterized in that silicide is formed on the bottom surface of the active region of the element. 5. Instead of creating a void on the entire bottom surface of the active region of the device, grooves and voids are created with a portion of the silicon remaining for connecting the semiconductor substrate and the active region of the device, and the trench and void are A method for manufacturing a semiconductor device according to claim 1, characterized in that filling with an insulator is performed by a CVD method. 6. Without creating any voids on the entire bottom surface of the active region of the device, some silicon is left for connecting the semiconductor substrate and the active region of the device, and this is made into an oxide by thermal oxidation, and then grooves and voids are formed. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor device is filled with an insulating material by a CVD method. 7. Instead of forming a void on the entire bottom surface of the active region of the device, a trench and a void with a lateral slope are formed with a portion of the silicon remaining for connecting the semiconductor substrate and the active region of the device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the groove and the gap are filled with an insulating material by a CVD method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7516682A JPS58192345A (en) | 1982-05-07 | 1982-05-07 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7516682A JPS58192345A (en) | 1982-05-07 | 1982-05-07 | Semiconductor device and its manufacture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58192345A JPS58192345A (en) | 1983-11-09 |
| JPS6310895B2 true JPS6310895B2 (en) | 1988-03-10 |
Family
ID=13568338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7516682A Granted JPS58192345A (en) | 1982-05-07 | 1982-05-07 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58192345A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61125039A (en) * | 1984-11-21 | 1986-06-12 | Nec Corp | Semiconductor device and manufacture thereof |
| JPS61198743A (en) * | 1985-02-28 | 1986-09-03 | New Japan Radio Co Ltd | Manufacture of semiconductor device |
| JPH0799758B2 (en) * | 1985-07-05 | 1995-10-25 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
| US4888300A (en) * | 1985-11-07 | 1989-12-19 | Fairchild Camera And Instrument Corporation | Submerged wall isolation of silicon islands |
| JP4862253B2 (en) * | 2004-09-28 | 2012-01-25 | セイコーエプソン株式会社 | Semiconductor substrate manufacturing method and semiconductor device manufacturing method |
| US8426289B2 (en) * | 2011-04-14 | 2013-04-23 | Robert Bosch Gmbh | Wafer with spacer including horizontal member |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50102276A (en) * | 1974-01-09 | 1975-08-13 |
-
1982
- 1982-05-07 JP JP7516682A patent/JPS58192345A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50102276A (en) * | 1974-01-09 | 1975-08-13 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58192345A (en) | 1983-11-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5442223A (en) | Semiconductor device with stress relief | |
| EP0098374B1 (en) | Isolated dielectric structure for integrated circuits and method for fabricating such structure | |
| JP2554831B2 (en) | Semiconductor processing method for forming a substrate isolation trench | |
| JPH088270A (en) | Semiconductor device and its manufacturing method | |
| US4661832A (en) | Total dielectric isolation for integrated circuits | |
| JP2629644B2 (en) | Method for manufacturing semiconductor device | |
| JP2001024200A (en) | Semiconductor device and manufacture therefor | |
| US6362072B1 (en) | Process for realizing trench structures | |
| US4900689A (en) | Method of fabrication of isolated islands for complementary bipolar devices | |
| JP4138806B2 (en) | Method for forming a bipolar transistor | |
| JPH11145273A (en) | Manufacture of semiconductor device | |
| JPS6310895B2 (en) | ||
| KR100428526B1 (en) | Method of forming an isolation oxide for silicon-on-insulator technology | |
| JP2654607B2 (en) | Method for manufacturing semiconductor device | |
| JPH02285642A (en) | Dielectric isolation semiconductor device and its manufacture | |
| US5851901A (en) | Method of manufacturing an isolation region of a semiconductor device with advanced planarization | |
| KR100839894B1 (en) | Semiconductor device and fabrication method therefor | |
| JPH0529603A (en) | Manufacture of semiconductor device | |
| JP2000031489A (en) | Manufacturing semiconductor device | |
| JPH01214064A (en) | Insulated gate field effect transistor and its manufacture | |
| KR20010001206A (en) | Shallow trench isolation manufacturing method of semiconductor devices | |
| JP2002026027A (en) | Semiconductor device and its manufacturing method | |
| JPH09223730A (en) | Semiconductor device and manufacturing method thereof | |
| JP2531688B2 (en) | Method for manufacturing semiconductor device | |
| JPH0423828B2 (en) |