JPS63104341A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63104341A JPS63104341A JP61249434A JP24943486A JPS63104341A JP S63104341 A JPS63104341 A JP S63104341A JP 61249434 A JP61249434 A JP 61249434A JP 24943486 A JP24943486 A JP 24943486A JP S63104341 A JPS63104341 A JP S63104341A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- plating
- semiconductor device
- gold
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000007747 plating Methods 0.000 claims abstract description 24
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 8
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052709 silver Inorganic materials 0.000 claims abstract description 8
- 239000004332 silver Substances 0.000 claims abstract description 8
- 229910052718 tin Inorganic materials 0.000 claims abstract description 8
- 229910000679 solder Inorganic materials 0.000 claims abstract description 7
- 239000010931 gold Substances 0.000 claims abstract description 6
- 229910001128 Sn alloy Inorganic materials 0.000 claims abstract description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052737 gold Inorganic materials 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 20
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- 238000005538 encapsulation Methods 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 229910052729 chemical element Inorganic materials 0.000 abstract 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 6
- 230000005496 eutectics Effects 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- ZJPGOXWRFNKIQL-JYJNAYRXSA-N Phe-Pro-Pro Chemical compound C([C@H](N)C(=O)N1[C@@H](CCC1)C(=O)N1[C@@H](CCC1)C(O)=O)C1=CC=CC=C1 ZJPGOXWRFNKIQL-JYJNAYRXSA-N 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、半導体装置の製造方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device.
（従来の技術） 従来半導体装置の実装体の製造に際し、ＩＣ。(Conventional technology) Conventionally, when manufacturing a packaged body of a semiconductor device, IC.
ＬＳＩなどの素子上の外部導出電極端子を外部接続リー
ドに電気的に導出する方法として、各種の方法が開発さ
れている。Various methods have been developed for electrically leading out externally leading electrode terminals on elements such as LSIs to external connection leads.
最も良く知られた方法としては、２５〜４０μｍのＡｕ
、Ａｊなどの金属細線を用い、前記外部導出電極端子に
対する配線を相互の熱圧着もしくは超音波接続にて行う
いわゆるワイヤボンディング技術がある。The most well-known method is to deposit 25-40 μm of Au
There is a so-called wire bonding technique in which wires to the external lead-out electrode terminals are interconnected by mutual thermocompression bonding or ultrasonic bonding using thin metal wires such as , Aj, etc.
この方法は、外部導出電極端子数が比較的少ない場合に
は該接続部に対する信頼性も高い。しかし近年ＬＳＩの
ように、素子機能数が著しく高くなり、具体的には前記
外部導出電極端子数がｉｏ。This method also provides high reliability for the connecting portion when the number of external lead-out electrode terminals is relatively small. However, in recent years, the number of device functions has increased significantly, such as in LSIs, and specifically, the number of external lead-out electrode terminals has increased to IO.
〜１５０端子にも達し、かかる接続が素子側及び外部接
続リード側の２倍のボンディングを必要とすることから
接続回数が著しく多くなりそれらの接続部の信頼性低下
が免かれずかつコスト低減が困難な状況にあった。The number of connections reaches ~150 terminals, and since such connections require twice as many bondings on the element side and external connection lead side, the number of connections increases significantly, reducing the reliability of those connections and reducing costs. I was in a difficult situation.
一方かかる接続部の信頼性低下を克服すべく、上述の素
子側電極端子を一括処理するようにした金属細線を用い
ないいわゆるワイヤレス技術が実用化されるに到ってい
る。On the other hand, in order to overcome such a decrease in the reliability of the connection portion, a so-called wireless technology that does not use thin metal wires has been put into practical use, in which the above-mentioned element-side electrode terminals are processed all at once.
その一方法として、たとえばテープキャリヤ方式がある
。この方式では、ウェハプロセス段階で素子の電極端子
上に金属突起物（３ｆｆｔ常金、又は錫、ハンダが用い
らｎ１以下バンブともいう）を設け、この金属突起物に
対して、別体のポリイミドキャリヤ上の錫メッキ処理し
たｆｌ箔リードを一括して加圧、加熱し溶融接続を行う
ものである。One method is, for example, a tape carrier method. In this method, metal protrusions (3ft normal metal, tin, or solder are used and are also called n1 or less bumps) are provided on the electrode terminals of the device at the wafer process stage, and a separate polyimide The tin-plated fl foil leads on the carrier are pressurized and heated all at once to perform fusion connection.
ここで先づ、第６図〜第９図によってより具体的に外部
導出リードが取り付けられたテープキャリヤ方式による
実装体及びこれをリードフレームに溶着する例を説明す
る。例えば第６図において、映画用のフィルムと同様に
、送り孔（２）が形成されたポリイミド等の耐熱性テー
プ１の長手方向に多数の半導体素子用の孔３を形成する
。次にこの孔３の部分に銅箔（図示せず）を貼りあらか
じめ設計された所定のパターンにエツチング加工する。First, an example of a tape carrier type mounting body to which external leads are attached and welding this to a lead frame will be described in more detail with reference to FIGS. 6 to 9. For example, in FIG. 6, a large number of holes 3 for semiconductor elements are formed in the longitudinal direction of a heat-resistant tape 1 made of polyimide or the like in which feed holes (2) are formed, similar to a movie film. Next, copper foil (not shown) is applied to the hole 3 and etched into a predetermined pattern designed in advance.
このエツチング加工により銅箔リード４が、図の如く配
置された半導体素子５の方向に孔３の中心方向に突出さ
れた構成となる（この中心方向への突出部をインナリー
ド部とも言う）。該銅箔リード４はその表面にハンダま
たは錫メッキが施しである。By this etching process, the copper foil lead 4 is configured to protrude toward the center of the hole 3 in the direction of the semiconductor element 5 arranged as shown in the figure (this protrusion toward the center is also referred to as an inner lead section). The surface of the copper foil lead 4 is plated with solder or tin.
次にこの銅箔リード４の後記するインナリード部分を半
導体素子５の外部導出電極に形成したバンプ６に対応さ
せボンディングツールを押しあてパルス電流を流し接続
を行う。そして常法の如くこれらの部分をエポキシ樹脂
などで封止する。Next, the inner lead portion of the copper foil lead 4, which will be described later, corresponds to the bump 6 formed on the external lead-out electrode of the semiconductor element 5, and a bonding tool is pressed against the bump 6 to establish a connection by flowing a pulse current. These parts are then sealed with epoxy resin or the like in the usual manner.
尚図中７はインナリード部の支持枠である。一方素子５
の周辺開口部８内で銅箔リード４を切断し第８図の形状
に打ち抜き素子を個別に分離する。Note that 7 in the figure is a support frame for the inner lead portion. On the other hand element 5
The copper foil lead 4 is cut within the peripheral opening 8 to separately separate the punched elements in the shape shown in FIG.
次に上記素子５から外方に延びる銅箔リード４（以下こ
の部分をアウタリード部とも言う）をプレス成形等で折
り曲げ加工し第９図の如くリードフレーム９の中央部に
搭載し、該リードフレーム９の内方端９ａにアウタリー
ドを位置させ、同様にボンディングツールによって溶着
し電気的な接続を行い半導体装置を得るのである。Next, the copper foil lead 4 extending outward from the element 5 (hereinafter this part is also referred to as the outer lead part) is bent by press molding or the like and mounted on the center part of the lead frame 9 as shown in FIG. An outer lead is positioned at the inner end 9a of the lead 9, and similarly welded using a bonding tool to make an electrical connection, thereby obtaining a semiconductor device.
（発明が解決しようとする問題点）
しかしかかる従来の方式では、上記素子５から外方に延
びろアウタリード部はその材料７が小さく、幅も狭いな
どの理由で上記プレス手段による切断および折り曲げ加
工時それらの先端形状が必ずしも一定にならない。(Problems to be Solved by the Invention) However, in such a conventional method, the outer lead portion extending outward from the element 5 is cut and bent by the pressing means because the material 7 is small and has a narrow width. The shapes of their tips are not always constant.
即ち上記折り曲げ加工などによってアウタリード先端の
ピッチずれ又は上下方向への位置変動等を生じ、その結
果リードフレームに対向させる際に相互の対向位置関係
が不均一化することが多く、接続不良、及びその接続部
の強度低下等を招（。In other words, due to the above-mentioned bending process, etc., the tip of the outer lead may be shifted in pitch or shifted in the vertical direction, and as a result, when facing the lead frame, the mutual positional relationship often becomes uneven, resulting in poor connection and the like. This may cause a decrease in the strength of the connection part.
そして上記ボンディングツールによる加熱、圧着条件が
一定せず信頼性を低下させかつ作業性、歩留の低下によ
り経済的に不利益を蒙るなどの問題があった。Furthermore, there have been problems in that the heating and compression conditions by the bonding tool are not constant, resulting in lower reliability and lowering workability and yield, resulting in economic disadvantage.
この発明は、特に上記アウタリードのリードフレームに
対する接続不良等の問題点について適切に解決した半導
体装置の製造方法を提供するものである。The present invention provides a method of manufacturing a semiconductor device that appropriately solves problems such as poor connection of the outer lead to the lead frame.
（問題点を解決するための手段）
この発明は、上記テープキャリヤ実装方式による実装体
のアウタリードのリードフレームに対する接続部におい
て、該リードフレーム側に充分に厚く錫、ハンダまたは
金−錫合金のいづれがのメッキを施し加圧加熱により接
続することを特徴とするものである。(Means for Solving the Problems) The present invention provides that, in the connection portion of the outer lead of the mounting body using the tape carrier mounting method to the lead frame, a sufficiently thick layer of tin, solder, or gold-tin alloy is applied to the lead frame side. It is characterized by being plated with metal and connected by pressure and heating.
（作 用）
この発明によれば、テープキャリヤ方式による実装体の
アウタリードが、リードフレーム接続部のメッキ部に当
接されるので、加熱加圧により上記アウタリードが上記
メッキ部に埋設される構成になり、上記変形等をカバー
し前記接続不良等の問題点を除去できる。(Function) According to the present invention, the outer lead of the tape carrier type mounting body is brought into contact with the plated part of the lead frame connection part, so that the outer lead is buried in the plated part by heating and pressurizing. Therefore, the above-mentioned deformation etc. can be covered and problems such as the above-mentioned poor connection can be eliminated.
（実 施 例）
以下この発明の実施例について第１図ないし第５図に基
づき説明する。これらの各図中特に第１図及び第３図は
、上記第８図及び第９図に略対応するので同一部分には
同一符号を付してその説明を省略する。(Embodiments) Examples of the present invention will be described below with reference to FIGS. 1 to 5. Among these figures, especially FIGS. 1 and 3 roughly correspond to the above-mentioned FIGS. 8 and 9, so the same parts are given the same reference numerals and the explanation thereof will be omitted.
本発明においては図示省略したが、上記従来例と同様の
テープキャリヤ方式により素子５のバンプ６にリード４
のインナーリード部を固着し、該リード４の他端部、即
ちアウタリード部を残して第１図のごとく切断し、同様
にプレス成形等で所望の折り曲げ加工を施すのである。Although not shown in the present invention, the leads 4 are attached to the bumps 6 of the element 5 using a tape carrier system similar to the conventional example described above.
The inner lead portion of the lead 4 is fixed, and the other end of the lead 4, that is, the outer lead portion, is cut as shown in FIG. 1, and the desired bending process is similarly performed by press molding or the like.
次に第２図の如くリードフレーム２０の内方端２１には
、金又は銀による第１メッキ部２２を設け、該メッキ２
２の上に更に錫またはハンダ、または金−錫合金メッキ
による第２のメッキ部２３を重層させる。尚、図中３０
はアイランドで上記と同様の第１．第２のメッキが施さ
れている。Next, as shown in FIG. 2, a first plated part 22 of gold or silver is provided on the inner end 21 of the lead frame 20, and
A second plating portion 23 made of tin, solder, or gold-tin alloy plating is further layered on top of the second plating portion 23 . In addition, 30 in the figure
is an island and the first . A second plating is applied.
そしてアウタリード部とリードフレーム２０とを第３図
の如く対向させ、その対向部間に上記第１及び第２のメ
ッキ２２及び２３を介在させ、図示しないボンディング
ツールによる抑圧下パルス電流により加熱圧着し、メッ
キ部を溶融させ接続する。（この場合の条件は３００〜
５００℃、０゜２〜３秒程度である）なお、図中３１は
アイランドと素子との接続材である銀ペーストを示す。Then, the outer lead part and the lead frame 20 are opposed to each other as shown in FIG. 3, and the first and second platings 22 and 23 are interposed between the opposed parts, and they are heated and crimped by a pulsed current under pressure by a bonding tool (not shown). , melt and connect the plated parts. (The conditions in this case are 300~
(500° C., 0° for about 2 to 3 seconds) In the figure, numeral 31 indicates a silver paste which is a connecting material between the island and the element.
第４図は第３図のＡ部分の拡大図であり、リード４のア
ウタリード部のリードフレーム２０に対する溶融接続状
況を示し、図中４０はこのときに形成される共晶接続部
である。FIG. 4 is an enlarged view of part A in FIG. 3, showing the state of fusion connection of the outer lead portion of the lead 4 to the lead frame 20, and numeral 40 in the figure indicates the eutectic connection portion formed at this time.
図の如く上記加熱圧着によりリードフレーム２０上の第
２のメッキ２３は溶融され押圧されたアウタリード部が
該メッキ部中に埋設する構成で両者が接続される。この
第２のメッキ厚は特に５〜２０μｍ程度であるのがこれ
らメッキ部による例えば金錫共晶を充分に与え得ろ点で
特に好結果を与える。As shown in the figure, the second plating 23 on the lead frame 20 is melted and pressed by the heat and pressure bonding, and the pressed outer lead portion is buried in the plated portion, thereby connecting the two. A thickness of about 5 to 20 .mu.m for this second plating gives particularly good results in that sufficient gold-tin eutectic, for example, can be produced by these plating parts.
さらに本発明において上記ホンディングツールによる圧
着温度は３００℃〜５００℃で設定されろが、実際の作
業上その両端では空冷により溶解がうまくいかず、接続
強度低下の原因になることがある。そこでその中央部温
度を上昇させろことが好ましいる。Further, in the present invention, the crimping temperature by the honding tool is set at 300°C to 500°C, but in actual work, the melting may not be successful at both ends due to air cooling, which may cause a decrease in connection strength. Therefore, it is preferable to increase the temperature of the central part.
本発明において上記第２のメッキ２３の下地金メッキ２
２を銀メッキとした場合には、アウタリード４の通常の
錫メッキと該銀メッキとにより共晶を作り、結果的に金
−錫共晶接続と同様の接続が行われ、即ち金−錫合金の
メッキを行ってもよいことになる。In the present invention, the base gold plating 2 of the second plating 23
When 2 is silver plated, a eutectic is created by the usual tin plating of the outer lead 4 and the silver plating, and as a result, a connection similar to the gold-tin eutectic connection is made, that is, a gold-tin alloy. This means that plating may be performed.
以上のようにして得られたリードフレーム上搭載された
テープキャリア実装体は、通常の樹脂封止半導体装置の
製造方法と同様にしてエポキシ樹脂などにより樹脂封止
を行い、Ｄ■Ｐ（ＤｕＡＬ ＩＮＬＩＮＥ ＰＡＣＫ
ＡＧＥ）またはＰＬＣＣ（ＰＬＡＳＴＩＣＬＥＡＤＥＤ
Ｃ１（ＩＰ ＣＡＲＲＩＥＲ） 、 ＦＰＰ （ＦＬ
ＡＴ ＰＬＡＳＴＴＣＰＡＣＫＡＧＥ）などの樹脂封止
半導体装置とする。The tape carrier mounted body mounted on the lead frame obtained in the above manner is resin-sealed with epoxy resin or the like in the same manner as in the manufacturing method of ordinary resin-sealed semiconductor devices, and is then processed into D■P (DuAL INLINE). PACK
AGE) or PLCC (PLASTICLEADED
C1 (IP CARRIER), FPP (FL
It is a resin-sealed semiconductor device such as ATPLASTTCPACKAGE).
第５図はかかる実施例の上記ＰＬＣＣを示す。FIG. 5 shows the PLCC of such an embodiment.
（発明の効果）
以上、詳細に説明したようにこの発明によればテープキ
ャリヤ実装方式による実装体のアウタリード部をアウタ
リード部に接続する該リードフレーム接続部側に錫また
はハンダ、金及び銀などから選択された金属を部分的に
メッキしたので、両者接続部の溶融共晶量が多くなり、
その結果上記アウタリードのｍ械加工等に起因する上下
方向での浮き等による位置不均一化による接続不良を好
適に回避することができ、また、上記の如くボンディン
グツールの設定温度を高温側に設定し得るなど作業条件
の設定範囲が広くなり、作業性が向上し、同時に歩留が
向上するなど経済性に有利である等の効果がある。(Effects of the Invention) As described above in detail, according to the present invention, tin, solder, gold, silver, etc. Since the selected metal was partially plated, the amount of fused eutectic at the connection between the two was increased,
As a result, it is possible to suitably avoid connection failures due to positional unevenness due to lifting in the vertical direction due to machining of the outer lead, etc., and also to set the temperature of the bonding tool on the high temperature side as described above. This method has the effect of widening the setting range of working conditions, improving workability, and at the same time improving yield, which is advantageous for economy.
第１図〜第３図はこの発明の半導体装置の製造方法の一
例中特にアウタリードとリードフレームとの接続工程の
説明図、第４図は第３図Ａ部の拡大斜視図、第５図は本
発明半導体装置の一例の断面図、第６図ないし第９図は
従来のテープキャリア半導体装置の組立工程図である。
４・・・リード部、５・・・半導体素子、６・・・バン
ブ、７・・・支持枠、９，２０・・・リードフレーム、
２２・、。
第１のメッキ、２３・・・第２のメッキ、３０・・・ア
イランド、４０・・・金−錫共晶。
特許出願人 沖電気工業株式会社
７フグリーＦｆｊ！ｊｊ７＊Ｌ７：〒４１岑糸千Ｆ１ｍ
ａｍ２２ 牙ｉｌｌノγ１
１１−ドアし一ム音険のＦｗ面図
２３ 才２つメ／ｉ第２図
アフタリードｔ’ｌ−トフレーム”ｊ苧＃ ＬＴ＝ Ｙ
＃ｒ面図Ｍ４図のＡ部ト広入ネ４オ几区
第４図1 to 3 are explanatory diagrams of the process of connecting an outer lead and a lead frame in an example of the method of manufacturing a semiconductor device of the present invention, FIG. 4 is an enlarged perspective view of part A in FIG. 3, and FIG. 6 to 9, which are cross-sectional views of an example of the semiconductor device of the present invention, are assembly process diagrams of a conventional tape carrier semiconductor device. 4... Lead portion, 5... Semiconductor element, 6... Bump, 7... Support frame, 9, 20... Lead frame,
22.. First plating, 23... Second plating, 30... Island, 40... Gold-tin eutectic. Patent applicant Oki Electric Industry Co., Ltd. 7 Fugly Ffj! jj7*L7: 〒41 Shiitosen F1m
am22 Fw side view of Fw side
23 years old 2 years old/i Figure 2 After lead t'l-to frame"j # LT= Y
#r side drawing M4 drawing A section
Claims (4)
よる実装体のアウタリードをリードフレームに接続搭載
し、以下樹脂封止を行って半導体装置を得るに際して、 （ａ）前記リードフレームの前記アウタリードに対応す
る接続部上に錫、ハンダ、または金−錫合金のいずれか
のメッキを施し、 （ｂ）該メッキ部分に前記アウタリードの接続部を当接
させて加圧加熱して接続することを特徴とする半導体装
置の製造方法。(1) When the outer leads of a packaged body are connected and mounted on a lead frame using a tape carrier mounting method using heat-resistant tape, and then resin encapsulation is performed to obtain a semiconductor device, (a) Correspond to the outer leads of the lead frame. (b) The connecting portion of the outer lead is brought into contact with the plated portion and the connecting portion is heated under pressure to make the connection. A method for manufacturing a semiconductor device.
メッキからなる２層メッキ構造であることを特徴とする
特許請求の範囲第１項記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the plating of the lead frame has a two-layer plating structure consisting of first and second plating.
特徴とする特許請求の範囲第２項記載の半導体装置の製
造方法。(3) The method for manufacturing a semiconductor device according to claim 2, wherein the first plating is gold or silver plating.
金メッキであることを特徴とする特許請求の範囲第２項
記載の半導体装置の製造方法。(4) The method for manufacturing a semiconductor device according to claim 2, wherein the second plating is tin, solder, or gold-tin alloy plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61249434A JPS63104341A (en) | 1986-10-22 | 1986-10-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61249434A JPS63104341A (en) | 1986-10-22 | 1986-10-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63104341A true JPS63104341A (en) | 1988-05-09 |
Family
ID=17192908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61249434A Pending JPS63104341A (en) | 1986-10-22 | 1986-10-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63104341A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5208186A (en) * | 1989-02-09 | 1993-05-04 | National Semiconductor Corporation | Process for reflow bonding of bumps in IC devices |
-
1986
- 1986-10-22 JP JP61249434A patent/JPS63104341A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5208186A (en) * | 1989-02-09 | 1993-05-04 | National Semiconductor Corporation | Process for reflow bonding of bumps in IC devices |
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