JPS6294032A - Delay correction system - Google Patents
Delay correction systemInfo
- Publication number
- JPS6294032A JPS6294032A JP60234041A JP23404185A JPS6294032A JP S6294032 A JPS6294032 A JP S6294032A JP 60234041 A JP60234041 A JP 60234041A JP 23404185 A JP23404185 A JP 23404185A JP S6294032 A JPS6294032 A JP S6294032A
- Authority
- JP
- Japan
- Prior art keywords
- control signal
- parity
- transmission
- panel
- relay station
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Radio Relay Systems (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明に遅延補正方式に関し、特にディジタル無線通信
回線において、打合わせ通話信号、監視制御信号等の制
御用信号を主信号にビット挿入して伝送する無線システ
ムと、制御用信号す伝送しない他の無線システムとの間
の伝送時間差?補正する遅延補正方式に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a delay correction method, and particularly relates to a method for transmitting a control signal such as a meeting call signal or a supervisory control signal by inserting bits into the main signal in a digital wireless communication line. What is the transmission time difference between wireless systems that transmit control signals and other wireless systems that do not transmit control signals? This invention relates to a delay correction method for correction.
し従来の技術〕
ディジタル無線通信回線において、打合わせ通話信号、
監視制御信号等の制御用信号音伝送する方法には、主信
号にFM等の複合変調音11つアナログ方式と、主信号
にビット挿入して伝送するディジタル方式とがある。ア
ナログ方式は構成が簡単で安価であることから従来広く
使わIていたが、周波数帯域有効利用の観点から最近開
発さnた多値直交振幅変調方式(例えば16値QAM又
は64iQAMなど)では、主としてディジタル方式が
用いられる。[Prior art] In digital wireless communication lines, meeting call signals,
Methods for transmitting control signal sounds such as supervisory control signals include an analog method in which 11 complex modulated sounds such as FM are added to the main signal, and a digital method in which bits are inserted into the main signal and transmitted. Analog systems have been widely used in the past due to their simple configuration and low cost, but from the perspective of effective use of frequency bands, recently developed multilevel quadrature amplitude modulation systems (such as 16-QAM or 64iQAM) have mainly A digital method is used.
上述の制御用信号に、通常は予備無線システムと現用の
1無線システムとに並列に伝送され、他の現用無線シス
テムには制御用信号は伝送されない。制御用信号全伝送
する無線システムには、各中間中継局にこの制御用信号
?分岐お工び挿入する定めの分岐挿入盤が設けられる。The control signal described above is normally transmitted in parallel to the standby radio system and one working radio system, and is not transmitted to the other working radio system. In a wireless system that transmits all control signals, is this control signal sent to each intermediate relay station? A branch/insertion board is provided for branching and inserting.
この分岐挿入盤?挿入することにエリ、中継さnるデー
タ信号には少なくとも数ビットの時間遅延が発生する。This branch insertion board? Due to the insertion, a time delay of at least several bits occurs in the relayed data signal.
従って、制御用信号を伝送する無線システムと、制御用
信号全伝送しない無線システムとでは、中間中継局の数
が多くなると可成りの伝送時間差が生ずる。ディジタル
無線通信回線ではフェーシング等VC,よる回線障害全
防止するtめ、無線断の同巧1切替が採用されることが
多い。この場合、制御用信号?伝送する予備無線システ
ムと、伝送用信号全伝送しない現用の無線システムとの
間で大きな伝送時間差があると同期切替ができなくなる
ため、制御用信号?伝送しない無線システムに補正用遅
延回路金挿入することが行わfる。Therefore, when the number of intermediate relay stations increases, a considerable difference in transmission time occurs between a wireless system that transmits control signals and a wireless system that does not transmit all control signals. In digital wireless communication lines, in order to completely prevent line failures caused by VCs such as facing, a single switch with wireless disconnection is often adopted. In this case, the control signal? If there is a large transmission time difference between the standby wireless system that transmits and the working wireless system that does not transmit all of the transmission signals, synchronized switching will not be possible. A correction delay circuit is inserted into a wireless system that does not transmit data.
〔発明が解決し7エうとする問題点〕
(−か(−ながら、上述し7?、従来の遅延補正方式は
、伝送時間差の補正のみを目的とする専用の遅延回路が
必要であるという間組点がある。本発明の目的は、上述
の問題点を除去し、専用の遅延[!’il路を必要とし
ない遅延補正方式を提供することである。[Problems that the invention aims to solve] It is an object of the present invention to eliminate the above-mentioned problems and provide a delay correction scheme that does not require a dedicated delay path.
[問題?解決するための手段〕
本発明の遅延補正方式は、送信端局、中間中継局、受信
端局から構成さ扛るディジタル無線通信回線で、打合わ
せ通話信号、監視告1j御信号等の制御用信号を主信号
にビット挿入して伝送する第1の無線システムと前記制
御用信号ケ伝送しない第2の無線システムとの伝送時間
の差を補正する遅延補正方式において、前記第1の無線
システムの前記中間中継局に設けられ前記制御用信号の
分岐挿入とパリティ・チェ、・り・パルスの監視87行
う分岐挿入盤の挿入遅延時間と、前記第247’)無線
システムの前記中間中継局に設けられ・・:11テイ・
チェック・パルスの監視ケ行うハIJティ蛤視盤の挿入
遅延時間とが等しくなるように構成さハている。[problem? Means for Solving the Problem] The delay correction method of the present invention uses a digital wireless communication line consisting of a transmitting terminal station, an intermediate relay station, and a receiving terminal station to transmit control signals such as meeting call signals and monitoring notification control signals. In a delay correction method for correcting a difference in transmission time between a first wireless system that inserts bits into the main signal and transmits the control signal, and a second wireless system that does not transmit the control signal, 247') An insertion delay time of a drop-and-drop board installed at the intermediate relay station that performs drop-and-add of the control signal and monitoring 87 of parity check, re-pulse, and 247') installed at the intermediate relay station of the wireless system.・・・:11 tei・
The insertion delay time of the IJ tee for monitoring the check pulse is made equal to the insertion delay time of the IJ tee.
次に、本発明の実施例ゲ図面ゲ参照して説明する。 Next, an embodiment of the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の回線構成?示すプロ、ツク
図であり、中間中継局が1局の場合VCついて、−伝送
方向のみ金示しである。第1図において、予備無線シス
テムSP及び現用無線システム5YSIは制御用信号を
主信号にビット挿入して伝送する第1の無線システム、
現用無線システム、5Y82〜5YSnは制御用信号を
伝送しない練2の無線システムであり、送信端局10.
中間中継局20.受信端局30はそれぞれ下記の二うに
構成されている。Figure 1 shows the line configuration of an embodiment of the present invention? This is a professional diagram showing only the -transmission direction for VC when there is one intermediate relay station. In FIG. 1, the backup radio system SP and the working radio system 5YSI are a first radio system that inserts bits into the main signal and transmits the control signal;
The active wireless systems 5Y82 to 5YSn are the second wireless systems that do not transmit control signals, and transmit terminal stations 10.
Intermediate relay station 20. Each receiving terminal station 30 has the following two configurations.
送信端局10において、正常時5YSx〜5YSnで伝
送さfるデータ入力信号は送信符号処理盤11゜12で
バイポーラ符号からユニポーラ符号に変換され、フレー
ム同期パルス、パリティ中チェック・パルス?含む付加
ビットが挿入さnたのち、各送信装置13とSPの送信
符号処理盤14の後に役目ら几た送1x同期切替器15
とに分配さnる。In the transmitting terminal station 10, the data input signal, which is normally transmitted at 5YSx to 5YSn, is converted from bipolar code to unipolar code by the transmitting code processing board 11, 12, and a frame synchronization pulse, a check pulse during parity, etc. After the additional bits containing are inserted, a transmission 1x synchronization switch 15 is installed after each transmitter 13 and the transmission code processing board 14 of the SP.
It is distributed to n.
SP及び5YSIT伝送、;n−ル割御用信号101け
3分さn、その−万はSYS 1の送信ハ号処理盤12
1/ic、他万は送信同期切替器15の後に設けられて
いる信号挿入盤16に送らオフ1、そハぞれ主信号にビ
ット挿入され文制御用信号の付加ビット全置換して信号
全挿入する工う構成さn、でいる。SP and 5YSIT transmission; n-le allocation signal 101 digits divided into 3;
1/ic, the other bits are sent to the signal insertion board 16 provided after the transmission synchronization switch 15, and the 1/ic bit is inserted into the main signal. It is configured to be inserted.
中間中継局20においては、各無線システムのつち制御
用信号を伝送するSP及び5YSIには、受信装置21
と送信装ft22との間に制御用信号の分岐挿入と区間
用パリテイ・チェック・パルスの監視および訂正とを行
う分岐挿入盤23が挿入され制御用信号?伝送しない5
YS2〜5Y8nには、区間用パリティ−チェック・パ
ルスの監視お工び訂正のみ?行うパリティ監視盤24が
挿入されている。そして、分岐挿入盤23及びパリティ
監視盤24?挿入したための主信号の伝送時間の遅れ(
挿入遅延時間)は、両者が等しくなるLうに構成されて
いる。なお、各無線システムの機能配置お工び信号ケー
ブル長、導波管長は1通常各無線システムの伝送時間が
ほぼ等しくなるように設定されている。In the intermediate relay station 20, the receiving device 21 is connected to the SP and 5YSI that transmit the control signals of each wireless system.
A branch/insertion board 23 is inserted between the control signal ft22 and the control signal ft22 for branching/inserting the control signal and monitoring and correcting the section parity check pulse. No transmission 5
For YS2 to 5Y8n, is there only parity check pulse monitoring and correction for the section? A parity monitoring board 24 is inserted to perform the parity monitoring. And the branch/insertion board 23 and the parity monitoring board 24? Delay in main signal transmission time due to insertion (
(insertion delay time) are configured so that both are equal. Note that the functional arrangement, signal cable length, and waveguide length of each wireless system are usually set so that the transmission time of each wireless system is approximately equal.
受信端局30においては、各受信装置作31で受(W復
調さ汎た信号のうち、5YSI〜5YSnの信号は受信
fE=1期切替器32?経て受信符号処理盤33.34
に、SPの信号は受信分配盤35を経て受信符号処理盤
33に加えらtl、、そ几ぞn送信符号処理盤と逆の符
号処理が行われる。SPの信号に受信分配盤35で5Y
SI〜5YSnの各受イぎ回期切替器32VC分配きれ
、受信同期切替器32は送信端局から現用と予備とに並
列に送出された信号間の同期をとり、フェージングにエ
リ発生するフレーム同期パルス間の位相ずれを合わせた
のち、無瞬断の同期切替が行われるように構成さルてい
る。なお、受信符号処理盤33では制御用信号の抽出が
行われる。In the receiving terminal station 30, among the signals received (W demodulated and spread) by each receiving device 31, the signals of 5YSI to 5YSn are sent to the reception code processing board 33, 34 via the reception fE=1 period switch 32?
Next, the SP signal is applied to the reception code processing board 33 via the reception distribution board 35, where it undergoes the reverse code processing as in the transmission code processing board. 5Y at the reception distribution board 35 to the SP signal
Each receiving cycle switcher 32VC of SI to 5YSn is distributed, and the receiving synchronization switcher 32 synchronizes the signals sent in parallel from the transmitting terminal station to the working and backup signals, and eliminates frame synchronization that occurs due to fading. After adjusting the phase difference between the pulses, the system is configured to perform synchronous switching without momentary interruption. Note that the received code processing board 33 extracts control signals.
大容量の通信金貸なう最近のディジタル無線通信回線で
は、送受信端局間の伝送品質?監視し予備無線システム
への切替全制御するためのシステム切替用のパリテイ・
チェック・パルスのほかに。In recent digital wireless communication lines that lend large amounts of communication money, what is the transmission quality between the transmitting and receiving end stations? Monitor and switch to backup radio system Parity/parity for system switching for full control
Besides check pulse.
各無線中継区間の伝送品質ケ監視し不良中継区間の特定
を容易にするための区間用パリテイ・チェック・パルス
全設定し、各中間中継局でこn音検出して監視する方法
が用いら扛る。この目的の九め各中間中継局に挿入さ几
るパリティ監視盤24の挿入遅延時間音、上述したぶり
に制御用信号の分岐挿入とパリティ監視とを行なう分岐
挿入盤23の挿入遅延時間と同じ(て設定しておけば、
第1の無線システムと第2の無線システムとの伝送時間
差をなくてことができる。従って、受信端局において、
制御用信号?伝送するSPと制御用信号?伝送しない5
YS2〜5YSnとの間に、7エージンにLる動的な変
動(こ′nは受信同期切替器で調整できる)を除いては
伝送時間差の補正のために専用の遅延回路金膜ける必要
がない。なお、送信端局お工び受信端局の構成は従来と
同様である。In order to monitor the transmission quality of each wireless relay section and easily identify defective relay sections, a method is used in which all section parity check pulses are set, and each intermediate relay station detects and monitors the noise. Ru. The ninth point for this purpose is that the insertion delay time of the parity monitoring board 24 inserted into each intermediate relay station is the same as the insertion delay time of the drop-and-add board 23, which performs drop-insertion of control signals and parity monitoring as described above. (If you set
It is possible to eliminate the transmission time difference between the first wireless system and the second wireless system. Therefore, at the receiving terminal,
Control signal? SP and control signal to be transmitted? No transmission 5
Between YS2 and 5YSn, it is necessary to install a dedicated delay circuit with gold film to correct the transmission time difference, except for dynamic fluctuations in the 7-age period (this can be adjusted with the reception synchronization switch). do not have. Note that the configurations of the transmitting terminal station and receiving terminal station are the same as those of the prior art.
以上詳細に説明したエラに、本発明の遅延補正方式にj
:fLば、各中間中継局で制御用信号ゲ伝送する無線シ
ステムに挿入される分岐挿入盤と、制御用信号?伝送し
ない無線システムに挿入さnるパリティ監視盤の挿入遅
延時間が同一となる=うに構成さn、ているので、中間
中継局g′ll数にかかわらず軸止金目的とする専用の
遅延回路?用いることなく、同期切替?行うディジタル
無線通信回線全構成できる効果がある。To address the errors described in detail above, the delay correction method of the present invention
: fL, the branch/additional board inserted into the wireless system that transmits the control signal at each intermediate relay station, and the control signal? Since the insertion delay time of each parity monitoring board inserted into a wireless system that does not transmit data is the same, a dedicated delay circuit for shaft clamping is required regardless of the number of intermediate relay stations. ? Synchronous switching without using it? This has the effect of allowing all digital wireless communication lines to be configured.
第1図は本発明の一実施例の回線構成?示すブロック図
である。
10・・・・・・送信端局、11.12.14・・・・
・・送信符号処理盤、13.22・・・・・・送信装置
、15・・・・・・送信同期切替器、16・・・・・・
信号挿入盤、20・・・・・・中間中継局、21.31
・−・・・受信装置、23・・・・・・分岐挿入盤、2
4・・・・・・パリティ監視盤、30・−・・・・受信
端局、32・・−・・・受信同期切替器、33. 34
・・・・・・受信符号処理盤、35・・・・・・受信分
配盤。Figure 1 shows the line configuration of an embodiment of the present invention? FIG. 10... Transmitting terminal station, 11.12.14...
...Transmission code processing board, 13.22...Transmission device, 15...Transmission synchronization switch, 16...
Signal insertion board, 20...Intermediate relay station, 21.31
...Receiving device, 23... Branch/insertion board, 2
4... Parity monitoring board, 30... Receiving terminal station, 32... Receiving synchronization switch, 33. 34
...Reception code processing board, 35...Reception distribution board.
Claims (1)
タル無線通信回線で、打合わせ通話信号、監視制御信号
等の制御用信号を主信号にビット挿入して伝送する第1
の無線システムと前記制御用信号を伝送しない第2の無
線システムとの伝送時間の差を補正する遅延補正方式に
おいて、前記第1の無線システムの前記中間中継局に設
けられ前記制御用信号の分岐挿入とパリテイ・チェック
・パルスの監視とを行う分岐挿入盤の挿入遅延時間と、
前記第2の無線システムの前記中間中継局に設けられパ
リテイ・チェック・パルスの監視を行うパリテイ監視盤
の挿入遅延時間とを等しく設定したことを特徴とする遅
延補正方式。A digital wireless communication line consisting of a transmitting terminal station, an intermediate relay station, and a receiving terminal station, which transmits control signals such as meeting call signals and supervisory control signals by inserting bits into the main signal.
In the delay correction method for correcting the difference in transmission time between a wireless system and a second wireless system that does not transmit the control signal, the control signal is branched at the intermediate relay station of the first wireless system. an insertion delay time of a branch/insertion board that performs insertion and monitors parity check pulses;
A delay correction method characterized in that the insertion delay time of a parity monitoring board provided at the intermediate relay station of the second radio system and monitoring parity check pulses is set to be equal to the insertion delay time.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60234041A JPS6294032A (en) | 1985-10-18 | 1985-10-18 | Delay correction system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60234041A JPS6294032A (en) | 1985-10-18 | 1985-10-18 | Delay correction system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6294032A true JPS6294032A (en) | 1987-04-30 |
JPH0535931B2 JPH0535931B2 (en) | 1993-05-27 |
Family
ID=16964640
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60234041A Granted JPS6294032A (en) | 1985-10-18 | 1985-10-18 | Delay correction system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6294032A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0330535A (en) * | 1989-06-28 | 1991-02-08 | Nec Corp | Auxiliary signal transmission circuit |
JPH03204249A (en) * | 1989-12-29 | 1991-09-05 | Nec Corp | Code error detection system |
-
1985
- 1985-10-18 JP JP60234041A patent/JPS6294032A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0330535A (en) * | 1989-06-28 | 1991-02-08 | Nec Corp | Auxiliary signal transmission circuit |
JPH03204249A (en) * | 1989-12-29 | 1991-09-05 | Nec Corp | Code error detection system |
Also Published As
Publication number | Publication date |
---|---|
JPH0535931B2 (en) | 1993-05-27 |
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