JPS6286968A - Picture signal correcting circuit - Google Patents
Picture signal correcting circuitInfo
- Publication number
- JPS6286968A JPS6286968A JP60226439A JP22643985A JPS6286968A JP S6286968 A JPS6286968 A JP S6286968A JP 60226439 A JP60226439 A JP 60226439A JP 22643985 A JP22643985 A JP 22643985A JP S6286968 A JPS6286968 A JP S6286968A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- ccd
- picture element
- output
- storage circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Facsimile Image Signal Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ＣＣＤ等の一次元イメージ七ンサを使用する
画情報読取回路に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image information reading circuit using a one-dimensional image sensor such as a CCD.
従来の技術
ＣＣＤ等の固体イメージセンサを使用して白黒コ値の画
情報を読み取る技術は、ファクシミリ装置の画情報読取
部あるいはＯＣＲ等の画情報読取り部、その他一般のス
キャナ装置に応用されている。これらに使用されるＣＣ
Ｄ固体イメージセンナは、半導体製品であり、製造上、
光電変換画素に欠隔が発生し、第１図に示す様に光電変
換部に一様光を照射した時、その出力信号が離散的に出
力されないか、あるいは出力振幅が他の画素て比べて非
常に小さくなる様なものが、製造されることがある。Conventional technology The technology of reading black and white image information using a solid-state image sensor such as a CCD is applied to the image information reading section of a facsimile machine, the image information reading section such as OCR, and other general scanner devices. . CC used for these
D solid-state image sensor is a semiconductor product, and in manufacturing,
When a gap occurs in the photoelectric conversion pixel and the photoelectric conversion section is irradiated with uniform light as shown in Figure 1, the output signal may not be output discretely, or the output amplitude may be different from that of other pixels. Items that are extremely small are sometimes manufactured.
発明が解決しようとする問題点
欠陥画素があると、原稿を走査して得られる画情報を記
録した時に、欠陥画素と対応する位置に副走査方向全域
にわたって黒い細線が記録され、画質に著しい悪影響を
与える。Problems to be Solved by the Invention If there is a defective pixel, when image information obtained by scanning a document is recorded, a thin black line will be recorded over the entire sub-scanning direction at the position corresponding to the defective pixel, which will have a significant negative impact on image quality. give.
本発明は従来の技術に内在する上記欠点を解消する為に
なされたものであり、従って、本発明の目的は、離散的
な出力不能画素をもつＣ，ＣＤ固体イメージセンサであ
っても、外部回路を付加することにより、ファクシミリ
等の画情報読取素子として実用上問題なく使用できるよ
うに画信号を補正することを可能とした新規な画信号補
正回路を提供することである。The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the conventional technology, and therefore, an object of the present invention is to eliminate the need for external It is an object of the present invention to provide a novel image signal correction circuit which, by adding a circuit, can correct an image signal so that it can be used as an image information reading element in a facsimile or the like without any problem in practical use.
問題点を解決するための手段
上記目的を達成する為に、本発明に係る画信号補正回路
は、ＣＣＤ等の一次元固体イメージセンナと、この一次
元固体イメージセンナの光電変換出力を処理する光電変
換出力処理回路と、この光電変換出力処理回路の出力を
一時記憶格納する格納回路と、この格納回路の任意の番
地の内容を複数個出力しこれを保持・演算する演算手段
と、この演算手段の演算結果を前記格納回路の任意の番
地に格納する格納手段とを含み構成され、前記固体イメ
ージセンサの特定の画素の出力を補正して出力すること
を特徴とする。Means for Solving the Problems In order to achieve the above object, the image signal correction circuit according to the present invention includes a one-dimensional solid-state image sensor such as a CCD, and a photoelectric converter that processes the photoelectric conversion output of the one-dimensional solid-state image sensor. A conversion output processing circuit, a storage circuit for temporarily storing the output of the photoelectric conversion output processing circuit, a calculation means for outputting, holding and calculating a plurality of contents of an arbitrary address of this storage circuit, and this calculation means. and storage means for storing the calculation result at an arbitrary address of the storage circuit, and is characterized in that the output of a specific pixel of the solid-state image sensor is corrected and output.
実施例
以下に、本発明をその好ましい一実施例について図面を
参照して具体的に説明する。EXAMPLE Hereinafter, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.
第１図は本発明に係る画信号補正回路の一実施例を示す
ブロック構成図である。第一図において、参照番号１０
０はＣＣＤ駆動回路、１０／はＣＣＤイメージセンサ、
１０２はＣＣＤの光電変換信号をアナログ処理するアナ
ログ処理回路、１０３はアナログ処理した信号を白、黒
の二値レベルにする二値化回路、１０ＩＩは７２４７分
の画情報を記憶する記憶回路、１０Ｓは記憶回路ＩＯ’
ｔのアドレス制御と記憶回路／υの読出し、書込みを制
御する制御回路、１０６は欠陥画素の位置情報を記憶保
持している欠陥画素位置記憶回路％ １０’／は欠陥画
素の信号レベルを決定する両信号レベル決定回路１０１
，１０９はスイッチ回路をそれぞれ示す。回路１０４に
は、使用しているＣＣＤの欠陥画素の位ｆｔｆ報を予め
記憶させておく。FIG. 1 is a block diagram showing an embodiment of an image signal correction circuit according to the present invention. In Figure 1, reference number 10
0 is a CCD drive circuit, 10/ is a CCD image sensor,
102 is an analog processing circuit that performs analog processing on the photoelectric conversion signal of the CCD; 103 is a binarization circuit that converts the analog-processed signal into binary levels of white and black; 10II is a storage circuit that stores image information for 7247 minutes; 10S is the memory circuit IO'
t address control and storage circuit/control circuit for controlling reading and writing of υ; 106 is a defective pixel position storage circuit that stores and holds position information of the defective pixel; 10'/ determines the signal level of the defective pixel; Both signal level determination circuit 101
, 109 indicate switch circuits, respectively. The circuit 104 stores in advance information about the number of defective pixels of the CCD being used.
いま、アナログ処理回路／θコの出力が、＃ｃＪ図（ａ
）の様であって、矢印で図示した如く離散的な３つの欠
陥画素ｙ・＋ Ｙ２．’Ｙ’があるものとする。Now, the output of the analog processing circuit/θ is shown in diagram #cJ (a
), and as shown by the arrows, there are three discrete defective pixels y.+Y2. Assume that there is a 'Y'.
即ち、白の中に欠陥画素ｙ１が、黒の中には欠陥画素ｙ
２が、白と黒の境界に欠陥画素ｙ５が存在する場合であ
る。アナログ処理回路１０．２の出力Ｉ１０を二値化回
路１０３に入力すると、その出力／／／は８Ｊ３図（ｂ
）のようになる。この場合、欠陥画素ｙ１のために白い
画情報を読みとっているにも拘らず黒い点が発生する。That is, the defective pixel y1 is in white, and the defective pixel y is in black.
2 is a case where the defective pixel y5 exists on the boundary between white and black. When the output I10 of the analog processing circuit 10.2 is input to the binarization circuit 103, the output /// is shown in Fig. 8J3 (b
)become that way. In this case, black dots occur even though white image information is being read due to the defective pixel y1.
たまたま、 ｙ２の欠陥画素は周辺が黒であるために、
周辺と同一の信号レベルにあるが、欠陥画素ｙ２の周辺
が白画素のときには、やはり欠陥画素ｙ１と同様に白の
画情報の中に、黒い点が発生する。欠陥画素ｙ３につい
ても同様である。By chance, the defective pixel of y2 has black surroundings, so
Although the signal level is the same as that of the surrounding area, when the area around the defective pixel y2 is a white pixel, a black dot is generated in the white image information as in the case of the defective pixel y1. The same applies to the defective pixel y3.
つまり、第１図に示す様な離散的な欠陥画素が存在する
とき如は、例えば全面白の画情報を読みとらせても、記
録面としては、欠陥画素に対応する位置に副走査方向全
域にわたって黒の細線が発生することになる。In other words, when there are discrete defective pixels as shown in Figure 1, for example, even if full white image information is read, the recording surface will have the entire area in the sub-scanning direction at the position corresponding to the defective pixel. A thin black line will appear across the area.
以下、実施例では第３図（ａ）の３つの欠陥画素がある
場合につき、補正回路の動作を説明する。欠陥画素を有
するＣＣＤの出力をアナログ処理し、さら【二値化した
７２４７分の画信号を７２４７分のビット幅をもつ記憶
回路／Ｉｌｌに記憶させる。７２４７分の画情報が記憶
回路ＩＯ’ｌに格納されると、制御回路ｉｏｒからの制
御により、スイッチｉｏざと１０９をＳｌ側に接続する
。欠陥画素位置記憶回路１０４には、予めＣＣＤの欠陥
画素の位置情報が記憶されている。制御回路ｉｏｚから
記憶回路ｉｏｂへの画素補正開始信号／／弘を受けて、
記憶回路１０６は最初の欠陥画素ｙ１のひとつ前とひと
つ後の画素のアドレスを連続的に発生させるよう、制御
回路ＩＯ５に対し欠陥画素ｙ１に対応するアドレスｌノ
コと、制御信号／／、７を出力する。制御回路ｉｏｓは
記憶回路１ＯＩＩに対して欠陥画素ｙ１のひとつ前のア
ドレスをアクセスし、記憶回路ＩＯ’ｌからの出力は画
信号レベル決定回路１０りにラッチされる。続いて、制
御回路１０！は記憶回路ｉｏａに対し欠陥画素ｙ１のひ
とつ後のアドレスをアクセスし、そのメモリ出力は画信
号レベル決定回路１０りにラッチされる。回路１０りは
、欠陥画素ｙ１のひとつ前とひとつ後の信号レベルがラ
ッチされると、各々が”Ｈ１ｇｈ″レヘルなレベ結果と
して”ｉ（ｉｇｈ”を、各々が”Ｌｏｖｒ”レベルなら
ば結果としてＬｏｗ ”を、ひとつが１Ｈｘｇｈ’レベ
ルでもう一方が” Ｌｏｗ”レベルならば結果として“
Ｌｏｗ″レベルを出力する様、構成されている。ｙｌの
欠陥画素の場合、その前後の信号レベルが共に”Ｈ１ｇ
ｈ″レベルであるので、画信号レベル決定回路１０７は
Ｈｉｇｈ”レベルを出力し、制御回路１０５に記憶回路
１０１４への書込み要求／／３を通知する。制御回路１
０ｊは、欠陥画素位置記憶回路／θ６からの欠陥アドレ
ス情報ｌノコと、画信号レベル決定回路１０７からの書
込要求／１５とから、記憶回路ＩＯ’ｌに対し、欠陥画
素ｙ１に相当するアドレスへ、回路１０りの出力ｌ／り
を書込む。こ、の一連の動作でｙｌの欠陥画素に相当す
るメモリのアドレスにはひとつ前とひとつ後のアドレス
て格納されている信号レベルと同じＨｔｇｈ”レベルが
Ｓき込まれて、それ以前て書かれていた論理レベルが補
正される。In the following example, the operation of the correction circuit will be described for the case where there are three defective pixels as shown in FIG. 3(a). The output of the CCD having the defective pixel is subjected to analog processing, and the binarized image signal of 7247 minutes is stored in a storage circuit/Ill having a bit width of 7247 minutes. When 7247 worth of image information is stored in the storage circuit IO'l, the switch io end 109 is connected to the Sl side under control from the control circuit ior. In the defective pixel position storage circuit 104, position information of defective pixels of the CCD is stored in advance. In response to the pixel correction start signal sent from the control circuit ioz to the storage circuit iob,
The memory circuit 106 sends an address l saw corresponding to the defective pixel y1 and control signals // and 7 to the control circuit IO5 so as to continuously generate the addresses of the pixels before and after the first defective pixel y1. Output. The control circuit ios accesses the address immediately before the defective pixel y1 to the memory circuit 1OII, and the output from the memory circuit IO'l is latched by the image signal level determining circuit 10. Next, control circuit 10! accesses the address immediately after the defective pixel y1 to the memory circuit ioa, and the memory output is latched by the image signal level determination circuit 10. In the circuit 10, when the signal levels one before and one after the defective pixel y1 are latched, each outputs ``i(igh'' as a level result of ``H1gh'' level, and ``i(igh'') as a result of each level of ``Lovr'' level. “Low”, if one is at 1Hxgh’ level and the other is at “Low” level, the result is “
It is configured to output a "Low" level.In the case of a defective pixel of yl, the signal levels before and after it are both "H1g".
h'' level, the image signal level determining circuit 107 outputs the High'' level and notifies the control circuit 105 of a write request //3 to the storage circuit 1014. Control circuit 1
0j is the address corresponding to the defective pixel y1 for the storage circuit IO'l based on the defect address information l saw from the defective pixel position storage circuit /θ6 and the write request /15 from the image signal level determination circuit 107. Write the output l/l of the circuit 10 to . Through this series of operations, the same Htgh" level as the signal level stored in the previous and next addresses is written into the memory address corresponding to the defective pixel of yl, and The logic level that was previously used will be corrected.
次に、制御回路ｌＯ５から開始信号／／ＩＩを受けて、
記憶回路１０６は、次の欠陥画素ｙ２のアドレスな／／
コとして出力し、同時に欠陥画素ｙ２のひとつ前とひと
つ後のアドレスを連続的に発生させるように制御信号／
／３を出力する。上記したのと同じ動作で記憶回路の欠
陥画素ｙ２の位置に対応するアドレスには、補正信号（
この場合には” Ｌｏｗ”レベル）が書きこまれる。Next, upon receiving the start signal //II from the control circuit lO5,
The memory circuit 106 stores the address of the next defective pixel y2.
The control signal /
/3 is output. In the same operation as described above, a correction signal (
In this case, "Low" level) is written.
次に、制御回路ｉｏｓから欠陥画素位置記憶回路ｉｏｔ
、への開始信号／／’Ｉにより、記憶回路１０６は欠陥
画素ｙ５のアドレス情報を／／−として出力し、かつ欠
陥画素ｙ３のひとつ前と後のアドレスを発生させるよう
に、制御回路１０ｊへの制御信号／／Ｊを出力する。制
御回路ｌ０ｊｒが記憶回路１０ＩＩに対し、欠陥画素ｙ
５の前後のアドレスを連続してアクセスし、回路１０７
に欠陥画素ｙ３の前後二画素の情報が入力されると、欠
陥画素ｙ３のひとつ前の画素は゛Ｈｔｇｈ″レベル、欠
陥画素ｙ５のひとつ後は” Ｌｏｗ ”レベルであるの
で、回路１０’）け、“ＬＯＷ ”レベルを出力し、／
／Ｓの書込み要求を受けて、制御回路１０Ｓは記憶回路
のｙ３に対応するアドレスにＬｏｗ”レベルを書込む。Next, from the control circuit ios to the defective pixel position storage circuit iot
, the memory circuit 106 outputs the address information of the defective pixel y5 as //-, and sends the address information to the control circuit 10j to generate the addresses immediately before and after the defective pixel y3. outputs the control signal //J. The control circuit l0jr sends the defective pixel y to the memory circuit 10II.
The addresses before and after 5 are accessed consecutively, and the circuit 107
When information on two pixels before and after the defective pixel y3 is input to , the pixel immediately before the defective pixel y3 is at the "Htgh" level, and the pixel after the defective pixel y5 is at the "Low" level, so the circuit 10') Outputs “LOW” level, /
In response to the write request of /S, the control circuit 10S writes "Low" level to the address corresponding to y3 in the storage circuit.
以上、欠陥画素位置記憶回路１０４が記憶保持している
全ての欠陥画素に対する補正が終了すると、スイッチ１
０ｇと１０９はＳユ側に接続されて、記憶回路１０１１
を読出しモードとして、−ライン分の画情報を出力する
。As described above, when the correction for all the defective pixels stored in the defective pixel position storage circuit 104 is completed, the switch 1
0g and 109 are connected to the S side, and the memory circuit 1011
is set to read mode, and image information for -lines is output.
欠陥画素に対する補正と、補正を施された記憶回路内の
画情報出力は、第３図（ｃ） Ｋ示す様に、二値化回路
１０３の出力／／／の有効画信号区間と次の有効画信号
区間の間で行なわれ、補正済み画信号の出力が終了する
と、制御回路１０５はＣ０Ｄ−動画路ｉｏｏからの同期
信号／／ｌ、により、次の有効画信号を記憶回路１０Ｉ
Ｉに入力出来るよう、アドレスの発生と記憶回路ｔｏｌ
Ｉの書込み制御を行なう。記憶回路１０（Ｉに次の画信
号が７２４７分入力されると、前述と同様の操作を行な
って補正画信号を記憶回路１０ダから出力する。The correction for the defective pixel and the output of the corrected image information in the storage circuit are as shown in FIG. This is performed during the image signal section, and when the output of the corrected image signal is completed, the control circuit 105 stores the next effective image signal in the storage circuit 10I using the synchronization signal //l from the C0D-video path ioo.
Address generation and storage circuit tol so that it can be input to I
Performs write control of I. When the next image signal 7247 minutes is input to the storage circuit 10(I), the same operation as described above is performed to output a corrected image signal from the storage circuit 10(I).
発明の効果
以上述べた様に、本発明の画信号補正回路は、欠陥画素
を有するＣＣＤイメージセンサで原画を走査して得られ
る画信号の、欠陥画素に対応する出力部分を、周囲の正
常な画素の出力に合わせて補正できるので、欠陥画素を
有するＣＣＩ）であっても。Effects of the Invention As described above, the image signal correction circuit of the present invention converts the output portion corresponding to the defective pixel of the image signal obtained by scanning an original image with a CCD image sensor having a defective pixel into surrounding normal pixels. Since it can be corrected according to the output of the pixel, even if the CCI has a defective pixel.
従来のように廃棄等することなく、使用できるという効
果がある。It has the advantage that it can be used without having to be disposed of as in the past.
第１図は欠陥が発生した光電変換画素の例な示す図、第
２図は本発明の一実施例を示すブロック構成図、第３図
は本発明による補正動作を説明する為のタイムチャート
である。Fig. 1 is a diagram showing an example of a photoelectric conversion pixel in which a defect has occurred, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a time chart for explaining the correction operation according to the present invention. be.
Claims (1)
体イメージセンサの光電変換出力を処理する光電変換出
力処理回路と、この光電変換出力処理回路の出力を一時
記憶格納する格納回路と、この格納回路の任意の番地の
内容を複数個出力しこれを保持・演算する演算手段と、
この演算手段の演算結果を前記格納回路の任意の番地に
格納する格納手段とを含み、前記固体イメージセンサの
特定の画素の出力を補正して出力することを特徴とする
画信号補正回路。A one-dimensional solid-state image sensor such as a CCD, a photoelectric conversion output processing circuit that processes the photoelectric conversion output of this one-dimensional solid-state image sensor, a storage circuit that temporarily stores the output of this photoelectric conversion output processing circuit, and this storage circuit. arithmetic means for outputting, holding and calculating a plurality of contents of arbitrary addresses;
An image signal correction circuit comprising storage means for storing the calculation result of the calculation means at an arbitrary address of the storage circuit, and correcting and outputting the output of a specific pixel of the solid-state image sensor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60226439A JPS6286968A (en) | 1985-10-11 | 1985-10-11 | Picture signal correcting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60226439A JPS6286968A (en) | 1985-10-11 | 1985-10-11 | Picture signal correcting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6286968A true JPS6286968A (en) | 1987-04-21 |
Family
ID=16845126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60226439A Pending JPS6286968A (en) | 1985-10-11 | 1985-10-11 | Picture signal correcting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6286968A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7564761B2 (en) | 2005-02-28 | 2009-07-21 | Fujitsu Limited | Recording and reproducing device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5394719A (en) * | 1977-01-31 | 1978-08-19 | Nec Corp | Removing system for defective picture element of photoelectric conversion pickup unit |
| JPS57211875A (en) * | 1981-06-24 | 1982-12-25 | Fujitsu Ltd | Picture data processing circuit |
-
1985
- 1985-10-11 JP JP60226439A patent/JPS6286968A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5394719A (en) * | 1977-01-31 | 1978-08-19 | Nec Corp | Removing system for defective picture element of photoelectric conversion pickup unit |
| JPS57211875A (en) * | 1981-06-24 | 1982-12-25 | Fujitsu Ltd | Picture data processing circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7564761B2 (en) | 2005-02-28 | 2009-07-21 | Fujitsu Limited | Recording and reproducing device |
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