JPS628601U - - Google Patents
Info
- Publication number
- JPS628601U JPS628601U JP10064585U JP10064585U JPS628601U JP S628601 U JPS628601 U JP S628601U JP 10064585 U JP10064585 U JP 10064585U JP 10064585 U JP10064585 U JP 10064585U JP S628601 U JPS628601 U JP S628601U
- Authority
- JP
- Japan
- Prior art keywords
- thermistor substrate
- inrush current
- current suppressing
- circuit diagram
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
- 238000009499 grossing Methods 0.000 description 3
Landscapes
- Details Of Resistors (AREA)
- Thermistors And Varistors (AREA)
Description
第１図ａ，ｂ，ｃは本考案の一実施例による突
入電流抑制素子の背面図、断面図、正面図、第２
図は同等価回路図、第３図は同適用例を示す整流
・平滑回路図、第４図ａ，ｂは従来の突入電流抑
制素子の断面図、正面図、第５図は従来の整流・
平滑回路図である。 １…サーミスタ基板、２…電極。
入電流抑制素子の背面図、断面図、正面図、第２
図は同等価回路図、第３図は同適用例を示す整流
・平滑回路図、第４図ａ，ｂは従来の突入電流抑
制素子の断面図、正面図、第５図は従来の整流・
平滑回路図である。 １…サーミスタ基板、２…電極。
Claims (1)
- 単一のサーミスタ基板と、前記サーミスタ基板
上に形成した３つの電極とを備えた突入電流抑制
素子。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10064585U JPS628601U (ja) | 1985-07-02 | 1985-07-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10064585U JPS628601U (ja) | 1985-07-02 | 1985-07-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS628601U true JPS628601U (ja) | 1987-01-19 |
Family
ID=30970658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10064585U Pending JPS628601U (ja) | 1985-07-02 | 1985-07-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS628601U (ja) |
-
1985
- 1985-07-02 JP JP10064585U patent/JPS628601U/ja active Pending