JPS628550A - Resistor-element forming method for semiconductor device - Google Patents
Resistor-element forming method for semiconductor deviceInfo
- Publication number
- JPS628550A JPS628550A JP14797085A JP14797085A JPS628550A JP S628550 A JPS628550 A JP S628550A JP 14797085 A JP14797085 A JP 14797085A JP 14797085 A JP14797085 A JP 14797085A JP S628550 A JPS628550 A JP S628550A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- resistor
- interlayer insulating
- wiring layer
- layer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims description 7
- 239000010410 layer Substances 0.000 claims abstract description 29
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 10
- 239000012535 impurity Substances 0.000 abstract description 6
- 238000002955 isolation Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/8605—Resistors with PN junctions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の抵抗素子形成方法に関し、特に
下層配線と上層配線とを接続させるための層間絶縁膜に
開口する接続孔部に設けた抵抗素子の形成方法に関する
。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for forming a resistor element in a semiconductor device, and in particular, the present invention relates to a method for forming a resistor element in a semiconductor device. The present invention relates to a method for forming a resistive element.
従来の半導体装置の抵抗素子は、半導体基板中に抵抗素
子形成のための絶縁分離領域を設け、その領域内に不純
物をドープし、抵抗素子を形成する。あるいは、半導体
基板上の絶縁膜上に多結晶シリコンを成長させ、不純物
をドープして抵抗素子を形成し、抵抗素子以外の多結晶
シリコンを酸化またはエツチングすることで抵抗素子領
域の絶縁分離を行なうなどの方法をとっていた。A conventional resistive element of a semiconductor device is formed by providing an insulating isolation region for forming a resistive element in a semiconductor substrate, and doping impurities into the region to form a resistive element. Alternatively, polycrystalline silicon is grown on an insulating film on a semiconductor substrate, doped with impurities to form a resistance element, and the polycrystalline silicon other than the resistance element is oxidized or etched to isolate the resistance element region. The following methods were used.
上述した従来の抵抗素子では、特に半導体基板中に抵抗
素子を形成する場合、その抵抗素子と他の素子との絶縁
分離を行なうための領域が必要であり、素子の集積度が
低下する。また、多結晶シリコン抵抗素子形成の際に、
その抵抗素子と絶縁分離を行なうために形成された、抵
抗素子と絶縁分離領域との境界面で生じる段差により、
上層配線層の段切れが生じる。さらに、半導体基板中に
形成する抵抗素子では、特に抵抗素子と基板間で、多結
晶シリコン抵抗素子ではその下層のｍ間絶縁膜を通して
さらに下層の半導体基板との間で、または上層の局間絶
縁膜を通してさらに上層の配線層との間で、各々生じる
寄生容量によシ回路構成上スピードパワー積が増加する
等の問題が生じろという欠点があった。In the conventional resistive element described above, especially when forming the resistive element in a semiconductor substrate, a region is required for insulating and separating the resistive element from other elements, which reduces the degree of integration of the element. Also, when forming a polycrystalline silicon resistance element,
Due to the step created at the interface between the resistance element and the insulation isolation region, which is formed to provide insulation isolation from the resistance element,
A break occurs in the upper wiring layer. Furthermore, in the case of a resistor element formed in a semiconductor substrate, in particular between the resistor element and the substrate, in the case of a polycrystalline silicon resistor element, there is a connection between the resistor element and the semiconductor substrate in the lower layer through the m-layer insulating film in the lower layer, or in the case of an inter-station insulator in the upper layer. There is a drawback that problems such as an increase in the speed-power product due to the parasitic capacitance generated between the film and the upper wiring layer occur in the circuit configuration.
本発明の半導体装置の抵抗素子形成方法は、下層配線と
上層配線とを′Ｓ続させるために層間絶縁膜に開口する
接続孔に、抵抗素子となシうる物質を充填して抵抗素子
を形成するのである。The method for forming a resistive element in a semiconductor device of the present invention is to form a resistive element by filling a connection hole opened in an interlayer insulating film with a substance that can be used as a resistive element in order to connect a lower layer wiring and an upper layer wiring. That's what I do.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の一実施例の平面図、第２図は第１図
のＡ−Ａ線断面図である。これらの図において、１は半
導体基板、２は半導体基板との層間絶縁膜、３は下層配
線、６は上層配線、４は下層配線と上層配線との間の眉
間絶縁膜、５は、抵抗素子を形成するための不純物をド
ープして形成した多結晶シリコンである。この実施例に
よると。FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a sectional view taken along line A--A in FIG. In these figures, 1 is a semiconductor substrate, 2 is an interlayer insulating film with the semiconductor substrate, 3 is a lower layer wiring, 6 is an upper layer wiring, 4 is an insulating film between the eyebrows between the lower layer wiring and the upper layer wiring, and 5 is a resistance element. Polycrystalline silicon is doped with impurities to form a polycrystalline silicon. According to this example.
抵抗素子は下層配線と上層配線との間の層間絶縁膜中の
抵抗が必要な配線間の接続孔部にのみに選択的に形成し
ている。接続孔の大きさを変えることで、あるいは多結
晶シリコン内にドープする不純物の濃度を変えることで
、抵抗値を変化させることが可能である。The resistance element is selectively formed only in the connection hole between the wirings where resistance is required in the interlayer insulating film between the lower layer wiring and the upper layer wiring. The resistance value can be changed by changing the size of the connection hole or by changing the concentration of impurities doped into polycrystalline silicon.
なお、上記実施例では抵抗素子として多結晶シリコンを
用いたが、それ以外の物質を用いることでも抵抗素子が
形成できることはいうまでもない。Although polycrystalline silicon is used as the resistance element in the above embodiment, it goes without saying that the resistance element can also be formed using other materials.
以上説明したように、本発明は、下層配線と上層配線と
を接続する層間絶縁膜の接続孔部において、抵抗素子を
形成することによシ、抵抗素子形成のための領域ならび
にその抵抗素子と他の素子との絶縁分離を行なうための
領域が不要となシ、これによりて素子の集積度が向上す
る。また抵抗素子形成による上層配線の段切れが減少す
る。以上の２点の改善に伴い歩留シが向上する。さらに
、抵抗素子形成に伴う寄生容量の減少によシ、本発明に
よる抵抗素子を論理回路に用いることでスピードパワー
積が減少するとφう効果もある。As explained above, the present invention provides a region for forming a resistive element and a region for forming the resistive element by forming a resistive element in a connection hole of an interlayer insulating film that connects a lower layer wiring and an upper layer wiring. There is no need for a region for insulating and separating the device from other devices, which improves the degree of device integration. In addition, disconnections in the upper layer wiring due to the formation of resistance elements are reduced. With the above two improvements, the yield is improved. Furthermore, due to the reduction in parasitic capacitance that accompanies the formation of the resistance element, there is also the effect that the speed-power product is reduced by using the resistance element according to the present invention in a logic circuit.
第１図は本発明の一実施例の平面図、第２図は第１図の
Ａ−Ａ線断面図である。
１・・・・・・半導体基板、２・・・・・・半導体基板
上の層間絶縁、膜、３、・・・・・・下層配線、４・・
・・・・層間絶縁膜、５・・・・・・抵抗素子、６・・
・・・・上層配線。FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line A--A in FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Interlayer insulation, film on semiconductor substrate, 3... Lower layer wiring, 4...
...Interlayer insulating film, 5...Resistance element, 6...
...Upper layer wiring.
Claims (1)
記下層配線と上層配線の間の層間絶縁膜にあけ、この孔
を抵抗物質で充填して抵抗素子を形成することを特徴と
する半導体装置の抵抗素子形成方法。A semiconductor device characterized in that a connection hole for connecting a lower layer wiring and an upper layer wiring is formed in an interlayer insulating film between the lower layer wiring and the upper layer wiring, and the hole is filled with a resistive material to form a resistive element. A method for forming a resistive element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14797085A JPS628550A (en) | 1985-07-04 | 1985-07-04 | Resistor-element forming method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14797085A JPS628550A (en) | 1985-07-04 | 1985-07-04 | Resistor-element forming method for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS628550A true JPS628550A (en) | 1987-01-16 |
Family
ID=15442216
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14797085A Pending JPS628550A (en) | 1985-07-04 | 1985-07-04 | Resistor-element forming method for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS628550A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63292665A (en) * | 1987-05-25 | 1988-11-29 | Nec Corp | Resistance load type semiconductor device |
| JPH04365370A (en) * | 1991-06-13 | 1992-12-17 | Nec Corp | Semiconductor integrated circuit |
| US5789783A (en) * | 1996-04-02 | 1998-08-04 | Lsi Logic Corporation | Multilevel metallization structure for integrated circuit I/O lines for increased current capacity and ESD protection |
| WO2019131702A1 (en) * | 2017-12-28 | 2019-07-04 | 株式会社村田製作所 | Semiconductor device |
| WO2019131704A1 (en) * | 2017-12-28 | 2019-07-04 | 株式会社村田製作所 | Semiconductor device |
-
1985
- 1985-07-04 JP JP14797085A patent/JPS628550A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63292665A (en) * | 1987-05-25 | 1988-11-29 | Nec Corp | Resistance load type semiconductor device |
| JPH04365370A (en) * | 1991-06-13 | 1992-12-17 | Nec Corp | Semiconductor integrated circuit |
| US5789783A (en) * | 1996-04-02 | 1998-08-04 | Lsi Logic Corporation | Multilevel metallization structure for integrated circuit I/O lines for increased current capacity and ESD protection |
| WO2019131702A1 (en) * | 2017-12-28 | 2019-07-04 | 株式会社村田製作所 | Semiconductor device |
| WO2019131704A1 (en) * | 2017-12-28 | 2019-07-04 | 株式会社村田製作所 | Semiconductor device |
| CN111263978A (en) * | 2017-12-28 | 2020-06-09 | 株式会社村田制作所 | Semiconductor device with a plurality of semiconductor chips |
| JPWO2019131702A1 (en) * | 2017-12-28 | 2020-09-10 | 株式会社村田製作所 | Semiconductor device |
| JPWO2019131704A1 (en) * | 2017-12-28 | 2020-10-01 | 株式会社村田製作所 | Semiconductor device |
| US11239159B2 (en) | 2017-12-28 | 2022-02-01 | Murata Manufacturing Co., Ltd. | Semiconductor device |
| US11239226B2 (en) | 2017-12-28 | 2022-02-01 | Murata Manufacturing Co., Ltd. | Semiconductor apparatus |
| CN111263978B (en) * | 2017-12-28 | 2023-10-13 | 株式会社村田制作所 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
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