JPS6285030U - - Google Patents

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Publication number
JPS6285030U
JPS6285030U JP17700085U JP17700085U JPS6285030U JP S6285030 U JPS6285030 U JP S6285030U JP 17700085 U JP17700085 U JP 17700085U JP 17700085 U JP17700085 U JP 17700085U JP S6285030 U JPS6285030 U JP S6285030U
Authority
JP
Japan
Prior art keywords
code conversion
control signal
data
gate circuit
code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17700085U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17700085U priority Critical patent/JPS6285030U/ja
Publication of JPS6285030U publication Critical patent/JPS6285030U/ja
Pending legal-status Critical Current

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  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案のデータ変換回路を示すブロ
ツク図、第２図は第１図に示したデータ変換回録
の動作を示す図、第３図は補正後の入力データを
示す図、第４図および第５図は従来のデータ変換
回路を示すブロツク図である。 １２……ゲート回路、１４……コード変換手段
としてのＢＣＤカウンタ、１６……補正手段とし
ての記憶素子（ＲＯＭ）。 FIG. 1 is a block diagram showing the data conversion circuit of this invention, FIG. 2 is a diagram showing the operation of data conversion and recording shown in FIG. 1, FIG. 3 is a diagram showing input data after correction, and FIG. 1 and 5 are block diagrams showing a conventional data conversion circuit. 12...gate circuit, 14...BCD counter as code conversion means, 16...memory element (ROM) as correction means.

Claims (1)

【実用新案登録請求の範囲】 制御信号に応じて入力データを取り込むゲート
回路と、 このゲート回路を通過したデータを特定のコー
ドに変換するコード変換手段と、 このコード変換手段が発生するコード変換出力
値に応じて制御信号を続み出し、この制御信号に
よつて前記ゲート回路のデータ通過を制御して前
記コード変換出力に補正を施す補正手段とから構
成したことを特徴とするデータ変換回路。[Claims for Utility Model Registration] A gate circuit that takes in input data in response to a control signal, a code conversion means that converts the data that has passed through this gate circuit into a specific code, and a code conversion output generated by this code conversion means. 1. A data conversion circuit comprising: correction means for successively outputting a control signal in accordance with a value, and controlling data passing through the gate circuit using the control signal to correct the code conversion output.
JP17700085U 1985-11-18 1985-11-18 Pending JPS6285030U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17700085U JPS6285030U (en) 1985-11-18 1985-11-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17700085U JPS6285030U (en) 1985-11-18 1985-11-18

Publications (1)

Publication Number Publication Date
JPS6285030U true JPS6285030U (en) 1987-05-30

Family

ID=31117785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17700085U Pending JPS6285030U (en) 1985-11-18 1985-11-18

Country Status (1)

Country Link
JP (1) JPS6285030U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5592041A (en) * 1978-12-29 1980-07-12 Seikosha Co Ltd Frequency correction unit
JPS575430A (en) * 1980-06-13 1982-01-12 Fujitsu Ltd Binary coded decimal converter
JPS57113621A (en) * 1980-12-29 1982-07-15 Fujitsu Ltd Code converter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5592041A (en) * 1978-12-29 1980-07-12 Seikosha Co Ltd Frequency correction unit
JPS575430A (en) * 1980-06-13 1982-01-12 Fujitsu Ltd Binary coded decimal converter
JPS57113621A (en) * 1980-12-29 1982-07-15 Fujitsu Ltd Code converter

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