JPS6282729A - Echo erasing device - Google Patents

Echo erasing device

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Publication number
JPS6282729A
JPS6282729A JP22198385A JP22198385A JPS6282729A JP S6282729 A JPS6282729 A JP S6282729A JP 22198385 A JP22198385 A JP 22198385A JP 22198385 A JP22198385 A JP 22198385A JP S6282729 A JPS6282729 A JP S6282729A
Authority
JP
Japan
Prior art keywords
circuit
signal
echo
characteristic parameter
storage circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22198385A
Other languages
Japanese (ja)
Inventor
Tetsuo Fujii
哲郎 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP22198385A priority Critical patent/JPS6282729A/en
Publication of JPS6282729A publication Critical patent/JPS6282729A/en
Pending legal-status Critical Current

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  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To obtain an echo erasing circuit having a sufficiently faster converging speed even to an input signal with a strong correlativity such as a sound signal by using a forecast error signal brought into a white level as a tap coefficiency correction vector. CONSTITUTION:An echo erasing section 26 consists of a reception signal storage circuit 15 storing signals X inputted from a transmission line 9, an echo characteristic parameter storage circuit 18 storing an echo characteristic parameter hi of an echo path, a superimposing integration circuit 19 multiplying an echo characteristic parameter to the output of an reception signal storage circuit and outputting an approximate echo signal (v), a forecast error signal calculating circuit 22 bringing the reception signal into a white level, a forecast error storage circuit 23, an inner product calculation circuit calculating the inner product between the reception signal and the forecast error signal and a correction quantity calculation circuit 25 calculating a correction quantity hi of the echo characteristic parameter hi from a correction coefficient alpha, an output of the forecast error signal storage circuit 23, an output of the inner product calculation circuit 24 and a residual signal (z) outputted from a subtraction circuit 16. Further, the echo characteristic parameter storage circuit 18 corrects sequentially the parameter according to the correction quantity inputted from the correction quantity calculation circuit 25.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は反響消去装置に関し、特に音声信号のように自
己相関の強い信号が入力されたときに生じる収束速度の
大幅な劣化を防ぐことにより1反響消去装置の特性の改
善を計るものである。
[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to an echo canceling device, and in particular, by preventing a significant deterioration in convergence speed that occurs when a signal with strong autocorrelation such as an audio signal is input. 1. This is intended to improve the characteristics of the echo canceller.

(従来の技術) 第3図に示すような対地A、B間を結ぶ会議電話等にお
いて、対地Aのマイク1から入力された信号は増幅回路
2および伝送路3七通して対地Bに送信され増幅回路5
およびスピーカ4で音響信号に変換され、対地Bの反響
径路6を経由してマイク7に廻りこみ入力される。さら
にこの信号は増幅回路8、伝送路9および増幅回路10
全通してスピーカ11に伝送され1反響径路12ヲ経て
再びマイク1に入力される。このような−巡ループの利
得が1以上の場合、いわゆるハウリング現象が生じてし
まう。これを防止するために、対地A、Bにおいてそれ
ぞれ反響消去回路13 、14を送信回線と受信回線の
間に挿入する。この反響消去回路は。
(Prior Art) In a conference call or the like that connects destinations A and B as shown in FIG. Amplification circuit 5
Then, the signal is converted into an acoustic signal by the speaker 4, and is inputted to the microphone 7 via the echo path 6 to the ground B. Further, this signal is transmitted to an amplifier circuit 8, a transmission line 9 and an amplifier circuit 10.
The entire signal is transmitted to the speaker 11, passes through one echo path 12, and is again input to the microphone 1. When the gain of such a -circuit loop is 1 or more, a so-called howling phenomenon occurs. In order to prevent this, echo canceling circuits 13 and 14 are inserted between the transmitting line and the receiving line at the destinations A and B, respectively. This echo cancellation circuit.

反響信号と等価な近似反響信号を生成し、これをもとに
送信信号に混入する反響信号を等制約に除去するように
構成されている(例えば、昭和58年度電子通信学会総
合全国大会/L2034  rテレビ会議用エコー消去
方式の一検討」)。
It is configured to generate an approximate echo signal equivalent to the echo signal, and based on this, remove the echo signal mixed into the transmitted signal with equal constraints (for example, the 1981 IEICE General National Conference/L2034 ``A study of an echo cancellation method for video conferencing'').

第4図は、一般的に用いられている反響消去回路のブロ
ック構成図である。すなわち、伝送路9から入力される
受信信号X (t) ?記憶する受信信号記憶回路15
と1反響経路(増幅回路10−スピーカ11−反響経路
12−マイク1−増幅回路2)の推定値である反響特性
パラメータJ(i=o、l、2゜・・・、M−1)’e
記憶させるための反響特性パラメータ記憶回路18と、
受信信号記憶回路15の出力に反響特性パラメータ記憶
回路18のパラメータを乗じ重畳積分して近似反響信号
V(t)’e出力する重畳積分回路19と、主入力信号
y(t)から近似反響消去信号V (t) ’!r減じ
て残差信号z (t) f出力する減算回路16と、残
差信号z (t)と受信信号x (t)よシ反響特性パ
ラメータの修正量Δhiヲ求める修正量算出回路17と
から構成され1反響特性パラメータ記憶回路18は修正
量算出回路17から入力される修正量によって逐次パラ
メータを修正する。なお、受信信号X(t)はRin信
号、主入力信号y(t)はSin信号と呼ばれている。
FIG. 4 is a block diagram of a commonly used echo cancellation circuit. That is, the received signal X (t) input from the transmission path 9? Received signal storage circuit 15 for storing
and the reverberation characteristic parameter J (i=o, l, 2°..., M-1)' which is the estimated value of one reverberation path (amplification circuit 10 - speaker 11 - reflection path 12 - microphone 1 - amplifier circuit 2). e
a reverberation characteristic parameter storage circuit 18 for storing;
A superimposition and integration circuit 19 multiplies the output of the received signal storage circuit 15 by the parameters of the echo characteristics parameter storage circuit 18 and performs superimposition integration to output an approximate echo signal V(t)'e, and approximate echo cancellation is performed from the main input signal y(t). Signal V(t)'! A subtraction circuit 16 that subtracts r and outputs a residual signal z (t) f, and a correction amount calculation circuit 17 that calculates a correction amount Δhi of the echo characteristic parameter from the residual signal z (t) and the received signal x (t). The echo characteristic parameter storage circuit 18 sequentially modifies the parameters according to the modification amount inputted from the modification amount calculation circuit 17. Note that the received signal X(t) is called a Rin signal, and the main input signal y(t) is called a Sin signal.

一般に反響消去回路は、学習同定法を用いて反響経路の
推定を行い、近似反響信号を生成し反響信号の除去を行
っている。適応時における反響消去回路の動作は下記の
式で表わされる。但し、tは時間を表し、Nはタップ数
を表わしている。
Generally, an echo cancellation circuit estimates an echo path using a learning identification method, generates an approximate echo signal, and removes the echo signal. The operation of the echo cancellation circuit during adaptation is expressed by the following equation. However, t represents time and N represents the number of taps.

hi(t) =hi(t−1)+Δhi(t)z(t)
=y(t)−v(t) 但し、i=0.l、2.・・、N−1 ここに、修正係数αは通常Oくαく1の間で設定され、
α=1に設定した場合に最も速く定常値に収束すること
が知られている。
hi(t) =hi(t-1)+Δhi(t)z(t)
=y(t)-v(t) However, i=0. l, 2. ..., N-1 Here, the correction coefficient α is usually set between O × α × 1,
It is known that when α is set to 1, it converges to a steady value most quickly.

(発明が解決しようとする問題点) ところが学習同定法を用いた方式では、Rin信号とし
て音声信号のように相関の強い信号が入力された場合、
収束速度が大幅に劣下してしまう。
(Problem to be solved by the invention) However, in the method using the learning identification method, when a highly correlated signal such as an audio signal is input as the Rin signal,
The convergence speed will be significantly reduced.

これを解決するために第5図に示すような反響消去回路
が提案されている(例えば、田村、来由。
To solve this problem, an echo cancellation circuit as shown in Fig. 5 has been proposed (for example, Tamura and Raiyu).

白木1石上“線形予測差分形エコー制御方式“、電子通
信学会1通信法式研資、C379−52,1979年)
。これは受信信号記憶回路へ受信信号X (t)を入力
する前に予測誤差算出回路20ヲ挿入し、反響消去回路
へのRin信号を白色化し、Rin信号の相関を塩9除
くことによシ収束速度の劣下金防いでいる。
Ishigami Shiraki, “Linear predictive differential echo control method”, Institute of Electronics and Communication Engineers 1 Communication Law Research Fund, C379-52, 1979)
. This is achieved by inserting a prediction error calculation circuit 20 before inputting the received signal Convergence speed deterioration is prevented.

しかしこの方式においては、予測誤差算出回路の逆特性
と反響経路の特性とを合せた特性パラメータhi を算
出する必要がある。また付加回路21を挿入する必要も
ある。このために、十ミリ秒毎に特性が変化する音声信
号に追従して変化する予測フィルタの動きに合せて、反
響特性パラメータhi  O値も変化させなければなら
ない。ところが、会議電話等に用いられる反響消去装置
の処理時間長は百ミリ秒以上あり、反響特性パラメータ
を音声信号の変化に対応させて変化させるのは困難であ
る。従って、単純に予測誤差算出回路を挿入するだけで
は所望の特性は得られない。
However, in this method, it is necessary to calculate a characteristic parameter hi that is a combination of the inverse characteristic of the prediction error calculation circuit and the characteristic of the echo path. It is also necessary to insert an additional circuit 21. For this reason, the reverberation characteristic parameter hi O value must also be changed in accordance with the movement of the prediction filter, which changes in accordance with the audio signal whose characteristics change every 10 milliseconds. However, the processing time of an echo canceling device used for conference calls and the like is 100 milliseconds or more, and it is difficult to change echo characteristic parameters in response to changes in audio signals. Therefore, desired characteristics cannot be obtained by simply inserting a prediction error calculation circuit.

本発明の目的は、上述の従来の欠点を解決し、音声信号
のような相関の強い入力信号にたいしても充分に収束速
度の速い反響消去回路を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional drawbacks and to provide an echo cancellation circuit that has a sufficiently high convergence speed even for highly correlated input signals such as audio signals.

(問題点を解決するための手段) 上記目的を達成するための本発明の特徴は、伝送路から
入力される受信信号をそえそれ記憶するための受信信号
記憶回路と、前記受信信号の予測誤差信号を求める予測
誤差算出回路と、前記予測誤差信号を記憶する予測誤差
信号記憶回路と、前2伝送路から主入力回路へいたる反
響経路の推定値を記憶するための反響特性パラメータ記
憶回路と、前記受信信号記憶回路の出力と反響特性パラ
メータ記憶回路の出力を重畳積分して近似反響信号を出
力する重畳積分回路と、受信信号と予測誤差信号の内積
を算出する内積算出回路と、主入力回路より入力される
主入力信号から前記重畳積分回路の出力を減算して反響
信号が消去された残差信号を算力する減算回路と、前記
予測誤差信号記憶回路の出力と前記内積算出回路と前記
減算回路の出力する残差信号とから反響特性パラメータ
の修正量を算出する修正量算出回路とを備えて、該減算
回路の出力する残差信号全伝送路に送出するように構成
した反響消去装置にある。
(Means for Solving the Problems) The features of the present invention for achieving the above object include a received signal storage circuit for storing and storing a received signal inputted from a transmission path, and a prediction error of the received signal. a prediction error calculation circuit for calculating a signal; a prediction error signal storage circuit for storing the prediction error signal; and a reverberation characteristic parameter storage circuit for storing an estimated value of the reverberation path from the first two transmission lines to the main input circuit; a superposition integration circuit that performs superimposition integration of the output of the received signal storage circuit and the output of the echo characteristic parameter storage circuit to output an approximate echo signal; an inner product calculation circuit that calculates an inner product of the reception signal and the prediction error signal; and a main input. a subtraction circuit that subtracts the output of the convolution integration circuit from the main input signal input from the circuit to calculate a residual signal from which the echo signal has been removed; and an output of the prediction error signal storage circuit and the inner product calculation circuit. and a correction amount calculation circuit for calculating a correction amount of the echo characteristic parameter from the residual signal output from the subtraction circuit, and configured to send the residual signal output from the subtraction circuit to all transmission paths. It's in the eraser.

(実施例) 第1図は、本発明の一実施例を示すブロック図である。(Example) FIG. 1 is a block diagram showing one embodiment of the present invention.

すなわち、伝送路9よ多入力されるRin信号X(t)
e蓄積する受信信号記憶回路15と1反響経路(増幅回
路10−スピーカ11−反響経路12−マイク1−増幅
回路2)の反響特性パラメータhi(i=0.1,2.
・・、M)’e記憶するための反響特性パラメータ記憶
回路18と、受信信号記憶回路の出力に反響特性パラメ
ータを乗じ重畳積分して近似反響信号V(t)を出力す
る重畳積分回路19と、受信信号を白色化するための予
測誤差信号算出回路nと、この予測誤差信号を記憶する
ための予測誤差記憶回路nと、受信信号と予測誤差信号
の内積を計算するための内積算出回路24と、修正係数
αと予測誤差信号記憶回路nの出力と内積算出回路24
の出力と減算回路16の出力する残差信号z (t)よ
り反響特性パラメータhi(t)の修正量Δhi(t)
を算出する修正量算出回路5とから反響消去部あは構成
されている。なお、反響特性パラメータ記憶回路18は
修正量算出回路5から入力される修正量に従って逐次パ
ラメータを修正する。
That is, the Rin signal X(t) that is input multiple times through the transmission line 9
e Accumulating received signal storage circuit 15 and echo characteristic parameters hi (i=0.1, 2.
..., M)'e; a reverberation characteristic parameter storage circuit 18 for storing the received signal storage circuit; and a superposition integration circuit 19 that multiplies the output of the received signal storage circuit by the reverberation characteristic parameter and performs superposition integration to output an approximate reverberation signal V(t). , a prediction error signal calculation circuit n for whitening the received signal, a prediction error storage circuit n for storing this prediction error signal, and an inner product calculation circuit for calculating the inner product of the reception signal and the prediction error signal. 24, the correction coefficient α, the output of the prediction error signal storage circuit n, and the inner product calculation circuit 24
The correction amount Δhi(t) of the echo characteristic parameter hi(t) is calculated from the output of
The echo canceling section A is composed of a correction amount calculation circuit 5 that calculates the amount of correction. Note that the echo characteristic parameter storage circuit 18 sequentially modifies the parameters according to the modification amount inputted from the modification amount calculation circuit 5.

次に1本実施例の動作について説明する。まずt時点に
おけるRin信号t−X(t)、Rin信号の予測誤差
信号k u (t) 、 Sin信号ty(t)、i番
目のタップ係数6hi(t)と書き表し、タップ数をN
とする。このときタップ係数修正式は以下のように書き
表せる。
Next, the operation of this embodiment will be explained. First, the Rin signal t-X(t) at time t, the prediction error signal k u (t) of the Rin signal, the Sin signal ty(t), and the i-th tap coefficient 6hi(t) are written, and the number of taps is N.
shall be. In this case, the tap coefficient correction formula can be written as follows.

H(t)=H(t−1)+ΔH(t )ΔH(t ) 
=β−z(t) U(t)/Ut(t)X (t)v(
t)=Ht(t)X(t) z(t)=y(t)−v(t) 但し、  a(t)=(ho(t)、ht(t)、・、
hN−□(t))tX(t) = (x(t ) 、x
(t−1) 、・−、x(t−N+ 1))tU(t 
) = (u(t) 、u(t−1)、 −−−、u(
t−N+1))t*1は行列の転置を表す。
H(t)=H(t-1)+ΔH(t)ΔH(t)
=β−z(t) U(t)/Ut(t)X (t)v(
t)=Ht(t)X(t) z(t)=y(t)-v(t) However, a(t)=(ho(t), ht(t),...
hN−□(t))tX(t) = (x(t), x
(t-1) ,・-,x(t-N+ 1))tU(t
) = (u(t), u(t-1), ---, u(
t-N+1)) t*1 represents the transpose of the matrix.

ここで用いる予測誤差信号算出回路の構成は、最も簡単
な前値予測からC0DECに用いられているようなフレ
ーム処理を伴う複雑な適応予測方式までのいずれかを用
いればよい。当然、タップ係数修正ベクトルとして用い
られる予測誤差信号は白色に近ければ近いほど収束速度
は速くなる。最も簡単な適応前値予測フィルタを用いた
場合、予測誤差信号は例えば以下の様に求めることもで
きる。
The configuration of the prediction error signal calculation circuit used here may be any one from the simplest previous value prediction to a complex adaptive prediction method involving frame processing as used in CODEC. Naturally, the closer the prediction error signal used as the tap coefficient correction vector is to white, the faster the convergence speed will be. When using the simplest adaptive prior value prediction filter, the prediction error signal can also be obtained as follows, for example.

u(t)=x(t)−γ−x(t−1)但し、γはOく
γ<1.0の間に適応的に設定される。
u(t)=x(t)−γ−x(t−1) However, γ is adaptively set between O and γ<1.0.

第2図は本実施例を用いてシミュレーション全行った結
果と、第3図の従来の回路を用いた7ミユレーシヨ/結
果とを比較した図である。同図は真の反響経路のパラメ
ータとタップ係数hi  との差の2乗平均値の収束過
程を示した図でアシ、特性aは本実施例金、特性すは第
3図の従来回路の収束特性を示している。エコーギヤ/
セラのタップ数は2000タツプ(時間長250rnS
)、収束係数βは1.0に設定し、入力信号Rinとし
ては実際の音声信号(約3.5秒間)を用いている。ま
た。
FIG. 2 is a diagram comparing the results of all the simulations performed using this embodiment and the results of 7 cycles per simulation using the conventional circuit shown in FIG. This figure shows the convergence process of the root mean square value of the difference between the parameters of the true echo path and the tap coefficient hi. It shows the characteristics. echo gear/
The number of taps of Sera is 2000 taps (duration 250rnS)
), the convergence coefficient β is set to 1.0, and an actual audio signal (approximately 3.5 seconds) is used as the input signal Rin. Also.

予測誤差算出回路としては適応前値予測を用いている。Adaptive pre-value prediction is used as the prediction error calculation circuit.

同図よシ明らかなように、音声信号のように相関の強い
入力信号に対して本方式が有効でるることが確認される
As is clear from the figure, it is confirmed that the present method is effective for highly correlated input signals such as audio signals.

なお1本方式はダブルトーク検出回路、修正係数制御回
路などと組み合せて使用されることは明らかでるる。
It is clear that the single method can be used in combination with a double talk detection circuit, a correction coefficient control circuit, etc.

(発明の効果) 以上説明したように。(Effect of the invention) As explained above.

(1)  タップ係数修正ベクトルとして白色化された
予測誤差信号を用いていることにより収束速度が大幅に
改善される。
(1) The convergence speed is significantly improved by using the whitened prediction error signal as the tap coefficient correction vector.

(2)各タップへの入力信号はRin信号をそのit用
いている為に白色化を補償する回路が必要でない。
(2) Since the Rin signal is used as the input signal to each tap, there is no need for a circuit to compensate for whitening.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例、第2図は第1図の回路のシ
ミュレーション結果、第3図は会議電話における反響消
去装置の組み込み例、第4図は一般的な反響消去装置の
構成図、第5図は従来の予測器を用いた反響消去装置の
構成図である。 ■、7−マイク、2.5,8.10−増幅回路、3.9
−伝送路、4.10−スピーカ、6.12−反響経路、
 13 、14−反響消去回路、15−受信信号記憶回
路、16−減算回路、17−修正量算出回路、18−反
響特性パラメータ記憶回路、19−重畳積分回路、加、
21−線形予測フィルタ、22−予測誤差算出回路、2
3−予測誤差記憶回路、24−内積算出回路、25−修
正量算出回路、26−予測誤差信号を修正ベクトルとし
て用いた反響消去回路、27−音声信号。
Fig. 1 shows an embodiment of the present invention, Fig. 2 shows simulation results of the circuit shown in Fig. 1, Fig. 3 shows an example of incorporating an echo canceling device into a conference phone, and Fig. 4 shows the configuration of a general echo canceling device. FIG. 5 is a block diagram of an echo canceling device using a conventional predictor. ■, 7-Microphone, 2.5, 8.10-Amplification circuit, 3.9
- transmission path, 4.10 - loudspeaker, 6.12 - echo path,
13, 14-echo cancellation circuit, 15-received signal storage circuit, 16-subtraction circuit, 17-correction amount calculation circuit, 18-echo characteristic parameter storage circuit, 19-superposition integration circuit,
21-linear prediction filter, 22-prediction error calculation circuit, 2
3 - Prediction error storage circuit, 24 - Inner product calculation circuit, 25 - Correction amount calculation circuit, 26 - Echo cancellation circuit using prediction error signal as correction vector, 27 - Audio signal.

Claims (1)

【特許請求の範囲】 伝送路から入力される受信信号を記憶するための受信信
号記憶回路と、 前記受信信号の予測誤差信号を求める予測誤差算出回路
と、 前記予測誤差信号を記憶する予測誤差信号記憶回路と、 前記伝送路から主入力回路へいたる反響経路の推定値を
記憶するための反響特性パラメータ記憶回路と、 前記受信信号記憶回路の出力と反響特性パラメータ記憶
回路の出力を重畳積分して近似反響信号を出力する重畳
積分回路と、 受信信号と予測誤差信号の内積を算出する内積算出回路
と、 主入力回路より入力される主入力信号から前記重畳積分
回路の出力を減算して反響信号が消去された残差信号を
算力する減算回路と、 前記予測誤差信号記憶回路の出力と前記内積算出回路と
前記減算回路の出力する残差信号とから反響特性パラメ
ータの修正量を算出する修正量算出回路とを備えて、該
減算回路の出力する残差信号を伝送路に送出するように
構成したことを特徴とする反響消去装置。
[Scope of Claims] A received signal storage circuit for storing a received signal input from a transmission path, a prediction error calculation circuit for calculating a prediction error signal of the received signal, and a prediction error signal for storing the prediction error signal. a storage circuit; a reverberation characteristic parameter storage circuit for storing an estimated value of the reverberation path from the transmission path to the main input circuit; a convolution integrating circuit that outputs an approximate echo signal; an inner product calculation circuit that calculates an inner product of the received signal and the prediction error signal; a subtraction circuit that calculates the residual signal from which the signal has been erased, and a correction amount of the reverberation characteristic parameter calculated from the output of the prediction error signal storage circuit, the residual signal output from the inner product calculation circuit and the subtraction circuit. 1. An echo canceling device comprising: a correction amount calculation circuit, and configured to send a residual signal output from the subtraction circuit to a transmission path.
JP22198385A 1985-10-07 1985-10-07 Echo erasing device Pending JPS6282729A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22198385A JPS6282729A (en) 1985-10-07 1985-10-07 Echo erasing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22198385A JPS6282729A (en) 1985-10-07 1985-10-07 Echo erasing device

Publications (1)

Publication Number Publication Date
JPS6282729A true JPS6282729A (en) 1987-04-16

Family

ID=16775234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22198385A Pending JPS6282729A (en) 1985-10-07 1985-10-07 Echo erasing device

Country Status (1)

Country Link
JP (1) JPS6282729A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6035312A (en) * 1997-02-13 2000-03-07 Nec Corporation Adaptive filter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6035312A (en) * 1997-02-13 2000-03-07 Nec Corporation Adaptive filter

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