JPS6276766A - Solid state image pickup device - Google Patents
Solid state image pickup deviceInfo
- Publication number
- JPS6276766A JPS6276766A JP60217261A JP21726185A JPS6276766A JP S6276766 A JPS6276766 A JP S6276766A JP 60217261 A JP60217261 A JP 60217261A JP 21726185 A JP21726185 A JP 21726185A JP S6276766 A JPS6276766 A JP S6276766A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- type
- vertical
- gate
- signal line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000007787 solid Substances 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims description 29
- 238000003384 imaging method Methods 0.000 claims description 26
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 239000010410 layer Substances 0.000 abstract description 33
- 239000011229 interlayer Substances 0.000 abstract description 4
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000002344 surface layer Substances 0.000 abstract 1
- 230000003287 optical effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14831—Area CCD imagers
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体基板上に光程変換素子Ｓよび走査回路を
集積化した固体撮像装置′置にｊ′５１するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is implemented in a solid-state imaging device in which a light distance conversion element S and a scanning circuit are integrated on a semiconductor substrate.
本発明はテレビカメラ等に１目いる固体撮像装置におい
て、固本撮像装・ｇの光電変換部の構造を第１項に記述
した如くすることによって、撮像・′時性の向上を計っ
たものである。The present invention is a solid-state imaging device used in a television camera, etc., in which the structure of the photoelectric conversion section of the solid-state imaging device is as described in Section 1, thereby improving the imaging speed. It is.
従来の技術の概要を第２図（、）及び第２図（ｂ）を用
いて説明する。An overview of the conventional technology will be explained using FIGS. 2(a) and 2(b).
第２図（、）は二次元固体撮像装置の構成例を示す。FIG. 2(,) shows an example of the configuration of a two-dimensional solid-state imaging device.
光′辺変喚素子は元ダイオード１を用いており、光ダイ
オード１はマ） ｌ）ツクス状に配置されている。The light side changing element uses an original diode 1, and the photodiodes 1 are arranged in a matrix.
たとえば光ダイオード１を選択するスイッチはｈｒｏｓ
トランジスタ２および５であり、ＭＯ３Ｉ−ランジスタ
２および３は各々垂直走査回路９及び水平走査回路１０
により垂直走査ゲート４及び水平ゲート５を通じ１ｆｆ
ｌＪ ＠されている。すなわち垂直走査回ｗＩ９により
選択された光ダイオード１の光情報は垂直信号課６Ｖこ
スイッチ用ＭＯ８）ランジヌタ２を通じ読み出される。For example, the switch that selects photodiode 1 is hros
transistors 2 and 5; MO3I-transistors 2 and 3 are vertical scanning circuit 9 and horizontal scanning circuit 10, respectively;
1ff through vertical scanning gate 4 and horizontal gate 5
lJ has been @. That is, the optical information of the photodiode 1 selected by the vertical scanning circuit wI9 is read out through the vertical signal section 6V and the switch MO8).
次に水平走査回路１０により選択されたスイッチ用ＭＯ
８）ランジスタ３は垂直信号線６にある光・清報を水平
１ｄ号線７に読み出し、出力端８に光情報を出力する。Next, the MO for the switch selected by the horizontal scanning circuit 10
8) The transistor 3 reads out the optical information on the vertical signal line 6 to the horizontal line 1d 7, and outputs the optical information to the output terminal 8.
このようにマトリックス状に配置された光ダイオード１
に蓄積された光情報を順次選択及び走査することにより
１画像信号として取り出すものである。Photodiodes 1 arranged in a matrix like this
One image signal is extracted by sequentially selecting and scanning the optical information accumulated in the image signal.
スイッチ用ＭＯＳトランジスタ２及び３または垂直走査
ゲート４、水平ゲート５または垂直信号線６、水平信号
線７、出力端８は目的に応じ複数になっている場合もあ
る。There may be a plurality of switching MOS transistors 2 and 3, vertical scanning gate 4, horizontal gate 5, vertical signal line 6, horizontal signal line 7, and output terminal 8 depending on the purpose.
第２図（ｂ）は光電変換部の単位画素の断面構造を示す
。以下説明の便宜上、電子を信号電荷とするＮチャンネ
ル型の撮像装置について述べるが、正孔を信号１荷とす
るＰチャンネル型の撮像装置においても以下の説明は極
性および導電型を逆にするのみで、同様に適用できるも
のである＠単位画素は、Ｐ型ｓｉ単結晶からなるＳｔ基
板１４とｎ型拡散ノー１１で形成される光ダイオード、
と同時に形成されるｎ型拡散層１１をソースとして多結
晶Ｓ１からなるゲートｆ’［極１３及びｎ型拡散層１２
をドレイ／とするＭＯ８型電界効果トランジスタで形成
される。ドレイン１２はＡＬなとの金属からなる電極１
５と接続され第１図に示す垂直信号線６を形成する。FIG. 2(b) shows a cross-sectional structure of a unit pixel of the photoelectric conversion section. For convenience of explanation, an N-channel type imaging device that uses electrons as the signal charge will be described below, but even for a P-channel type imaging device that uses holes as the signal charge, the following explanation will only be made by reversing the polarity and conductivity type. The unit pixel which can be similarly applied is a photodiode formed by an St substrate 14 made of a P-type Si single crystal and an N-type diffusion node 11;
Gate f' [pole 13 and n-type diffusion layer 12
It is formed of an MO8 type field effect transistor with a drain/. The drain 12 is an electrode 1 made of metal such as AL.
5 to form a vertical signal line 6 shown in FIG.
光１７が撮像面に入射すると口型拡散層１１およびＰ型
Ｓｌ基板１４内で電子−正孔対を発生し、この内遊子が
信号電荷としてｎ型拡散層１１に注入され、ｎ型拡散層
１１とＰ型Ｓｌ基板１４で形成される接合容せにより蓄
積される。垂直走査ゲート１３に正のパルスが印加され
ると、正電位となっているｎ型拡散Ｊ１．２（ドレイン
）に上記電子すなわち信号電荷が電極１５（第２図（ａ
）では垂直信号線６）Ｋ読み出され、第２図（轟）で説
明した如く出力端８まで読み出される。このときＤ型拡
散層１１（ソース）は正の電位となり、次に走査される
まで光１７により発生する電子を蓄積しつづけ正の電位
が低下する。このように各単位画素を選択走置し画像信
号として出力ｇ８８に取り出す〇〔発明が解決しようと
する問題点及び目的〕しかし以下の欠点を有しているた
め実用化がはばまれている。When the light 17 is incident on the imaging surface, electron-hole pairs are generated within the mouth-shaped diffusion layer 11 and the P-type Sl substrate 14, and these inner electrons are injected as signal charges into the n-type diffusion layer 11, and the n-type diffusion layer 11 and a P-type Sl substrate 14. When a positive pulse is applied to the vertical scanning gate 13, the electrons, that is, signal charges are transferred to the n-type diffusion J1.2 (drain), which is at a positive potential, on the electrode 15 (Fig. 2(a)
), the vertical signal line 6)K is read out, and the signal is read out to the output end 8 as explained in FIG. 2 (Todoroki). At this time, the D-type diffusion layer 11 (source) has a positive potential, continues to accumulate electrons generated by the light 17 until the next scan, and the positive potential decreases. In this way, each unit pixel is selectively scanned and output as an image signal to the output g88. [Problems and Objectives to be Solved by the Invention] However, the following drawbacks prevent it from being put to practical use.
撮像装置の解像度を向上するためには、単位画素の数を
増加しなければならない。すると当然のことながら単位
ｌＩ！ｉｉ索の面積が小なくなる。必然的にｎ型拡散層
１１の面積が小さくなり信号電荷を蓄積する８量も小さ
くなる。それと同時にｎ型拡散層１２の数が増え、それ
と接続されている垂直信号線１６の容量が増大する。以
上のことから、ｎ型拡散層１１の面積及びｄ量が小さく
なるために感度の低下及び最大信号「イ荷献が小さくな
る。In order to improve the resolution of an imaging device, the number of unit pixels must be increased. Then, of course, the unit is lI! ii The area of the cord becomes smaller. Inevitably, the area of the n-type diffusion layer 11 becomes smaller, and the amount of signal charge accumulated therein also becomes smaller. At the same time, the number of n-type diffusion layers 12 increases, and the capacitance of the vertical signal line 16 connected thereto increases. From the above, since the area and the amount d of the n-type diffusion layer 11 are reduced, the sensitivity is reduced and the maximum signal charge is reduced.
また垂直信号線６の容量が増大するため電気的雑音が大
きくなる。水平信号＠７についても垂直信号線６と同様
のことがいえる。このためダイナミックレンジを低下さ
せ、撮像・持件の悪化を招き、解像度の向上を計ること
が不可能であるという問題点を有している。そこで、本
発明は従来のこのような問題点を解決するため、固体撮
像装置ｄの最大電荷量を増加させ、垂直信号線６及び水
平信号線７の容量を低下させることにより電気的雑音を
抑圧しダイナミックレンジを増大させることにより解像
度及び撮像特性を向上させることを目的とする。Furthermore, since the capacitance of the vertical signal line 6 increases, electrical noise increases. The same thing can be said about the horizontal signal @7 as for the vertical signal line 6. This poses a problem in that the dynamic range is reduced, the imaging quality is deteriorated, and it is impossible to improve the resolution. Therefore, in order to solve these conventional problems, the present invention suppresses electrical noise by increasing the maximum charge amount of the solid-state imaging device d and reducing the capacitance of the vertical signal line 6 and the horizontal signal line 7. The objective is to improve resolution and imaging characteristics by increasing the dynamic range.
本発明の固体撮像装置は第１導電型の半導体基板と、該
半導体基板の１主表面に１次元あるいは２次元状に配置
された上記半導体基板と逆の導電型を有する複数個の拡
散層と、からなる４数個の光′電変換素子と、該光電変
換素子の光情報を順次読み出す上記半導体の上記１主表
面に投げられたスイッチ用ＭＯＳトランジスタと走置回
路を備えた固体撮像装置において、上記スイッチ用ＭＯ
Ｓトランジスタのドレインの拡散層の下および横方向に
上記半導体基板と同一の導電型の不純物の濃度がぼい低
ａ度不純物層を股ゆたことを特徴とするＯ
〔作用〕
本発明の上記の構造にすることによって、光電変換素子
を形成する光ダイオードの受台容量を増加すると同時に
垂直信号線及び水平信号線の容量を低下することができ
、最大電荷量の増加、電気的雑音の低下によりダイナミ
ックレンジの増加が可り目となり、解像度の向上をさま
たげることなく撮像特性を向上させることが可能になる
のである。The solid-state imaging device of the present invention includes a semiconductor substrate of a first conductivity type, and a plurality of diffusion layers having a conductivity type opposite to that of the semiconductor substrate arranged one-dimensionally or two-dimensionally on one main surface of the semiconductor substrate. In a solid-state imaging device comprising four or more photoelectric conversion elements consisting of , a switching MOS transistor and a scanning circuit thrown on the first main surface of the semiconductor for sequentially reading out optical information of the photoelectric conversion elements. , MO for the above switch
O characterized in that a low-a-degree impurity layer having a low concentration of impurities of the same conductivity type as the semiconductor substrate is disposed below and in the lateral direction of the drain diffusion layer of the S transistor. By adopting this structure, it is possible to increase the pedestal capacity of the photodiode forming the photoelectric conversion element and at the same time reduce the capacity of the vertical signal line and horizontal signal line, increasing the maximum charge amount and reducing electrical noise. This significantly increases the dynamic range, making it possible to improve imaging characteristics without hindering the improvement of resolution.
本発明の固体＃Ｌ像装置纒の実施例を第１図（、）、
（ｂ）に示す。An embodiment of the solid-state #L imaging device of the present invention is shown in FIG.
Shown in (b).
第２図に示した従来の単位画素と比較して異なる点は、
ｎ型拡散層２２の下Ｈよび横方向にＰ型不純物濃度の低
いｐ−ｊｄ ２７を設けている。Ｐ一層２７はｎ型拡散
層２２の真下に埋込層として形成しても同様な効果を得
る。すなわち光ダイオードを形成するｎ型拡散層２１と
Ｐ型半導体基板２４のｎ−Ｐ接合部量を大きくするため
にＰ型半導体基板の濃度を自由に大きく接定した場合で
も、垂直信号線６の容量はｎ型拡散層２２とＰ一層２７
の接合容量で決定されるため、増の口することがない。The differences compared to the conventional unit pixel shown in Figure 2 are as follows.
A p-jd layer 27 having a low concentration of P-type impurities is provided below the n-type diffusion layer 22 and in the lateral direction. The same effect can be obtained even if the P layer 27 is formed as a buried layer directly under the n-type diffusion layer 22. In other words, even if the concentration of the P-type semiconductor substrate is freely set to a large value in order to increase the amount of n-P junction between the n-type diffusion layer 21 and the P-type semiconductor substrate 24 that form the photodiode, the vertical signal line 6 The capacitance is the n-type diffusion layer 22 and the P layer 27
Since it is determined by the junction capacitance, there is no need to increase it.
これは換言すると、垂［頁信号線６の容置成分となるｎ
型拡散層２２とＰ一層２７の接合部量と、光ダイオード
を形成するｎ型拡散層２１とＰ型半導体基板２４の接合
部ｔは互いに分離されているため、各々の容量は自由に
設定可能となる。また水平信号線７の容量についても垂
直信号線６と同様のことがいえる。〔第１図（ｂ）〕
光ダイオードの接合容量と当直スイッチ用ＭＯＳトラン
ジスタのドレイ／の接合容管のちがいは、ｎ型拡散層２
１及び２２の接合部の面積及び不純物濃度を同一と仮定
すると、ｎ型拡散ノーと接合している導電体の不純物濃
度の差ということになる。In other words, this means that n is the vertical component of the page signal line 6.
Since the amount of the junction between the type diffusion layer 22 and the P layer 27 and the junction t between the n-type diffusion layer 21 and the P-type semiconductor substrate 24 that form the photodiode are separated from each other, the capacitance of each can be set freely. becomes. The same can be said about the capacitance of the horizontal signal line 7 as that of the vertical signal line 6. [Figure 1(b)] The difference between the junction capacitance of the photodiode and the drain/junction capacitance of the duty switch MOS transistor is that the n-type diffusion layer 2
Assuming that the area and impurity concentration of the junctions 1 and 22 are the same, this is the difference in the impurity concentration of the conductor connected to the n-type diffusion node.
すなわち接合容量はｎ型拡散層２１及び２２と接合して
いるＰ型半導体２４の不純物＊ｉ及びＰ一層の不純物濃
度のＡ乗に比例するため、ＰＷ半導体基板２４の不純物
濃度がＰ−／−の不純物４度より大きくしであることか
ら、光ダイオードの単位面積当りの接合容量の方が、岳
直スインテ用ＭＯＳトランジスタのドレインの単位面積
当りの接合部量より大きい。That is, since the junction capacitance is proportional to the A power of the impurity concentration of the P-type semiconductor 24 which is in contact with the n-type diffusion layers 21 and 22 and the impurity concentration of the P layer, the impurity concentration of the PW semiconductor substrate 24 is P-/- Since the impurity is larger than 4 degrees, the junction capacitance per unit area of the photodiode is larger than the junction amount per unit area of the drain of the MOS transistor for direct integration.
このようなことから光ダイオード及び垂直信号線と水平
信号線の容量を各々分離して設定可能となる。For this reason, it becomes possible to separately set the capacitance of the photodiode, the vertical signal line, and the horizontal signal line.
本発明は固体撮像装置の単位画素の垂直走査スイッチ用
ＭＯＳトランジスタのドレインであるｎ型拡散層の下も
しくは横方向にＰ一層を形成する構成としたので、元ダ
イオードを形成するｎ型拡散層とＰ型半導体基板の接合
部量を大きくでき、また同時に垂直信号線及び水平信号
線の容量を小さくすることが可能となり、従って最大信
号′笹荷量の増加、電気的雑音の低下が可能となり、こ
れらによりダイナミックレンジの拡大が容易になり固体
撮像装置の撮像特性の向上を計ることが可・１ヒになる
という効果が得られる。また解像度を向上させるため単
位１面素の数を大きくし、それに伴なって単位画素のサ
イズが小さくなっても、以上説明した如く撮像特性を悪
化することなく、解像度の向上を計ることが可能である
という効果が得られる。The present invention has a structure in which a single P layer is formed below or in the lateral direction of the n-type diffusion layer which is the drain of the vertical scanning switch MOS transistor of the unit pixel of the solid-state imaging device. It is possible to increase the amount of joints on the P-type semiconductor substrate, and at the same time, it is possible to reduce the capacitance of the vertical and horizontal signal lines, thereby increasing the maximum signal load and reducing electrical noise. As a result, it is easy to expand the dynamic range, and it is possible to improve the imaging characteristics of the solid-state imaging device. Furthermore, even if the number of pixels per unit pixel is increased in order to improve the resolution, and the size of the unit pixel is accordingly reduced, it is possible to improve the resolution without deteriorating the imaging characteristics as explained above. The effect is obtained.
第１図（、）は本発明による固体撮１象装置の単位画素
のＩｆｒ面図であり、第１図（ｂ）は固体撮像装置のス
インチ用ＭＯＳトランジスタの断面図であり、第２図（
、）は従来の固体撮像装置の回路図であり、第２図（ｂ
）は従来の固体撮像装置の単位画素の断面図であ゛る。
１・・・・・・光ダイオード
２・・・・・・垂直走査スイッチ用ＭＯＳトランジスタ
３・・・・・・水平走置スイッチ用ＭＯＳトランジスタ
４・・・・・・垂直走査ゲート及び配線５・・・・・・
水平走査ゲート及び配線６・・・・・・垂直信号線
７・・・・・・水平信号線
８・・・・・・出力端
９・・・・・・垂直走査回路
１０・・・・・水平走査回路
１１・・・・・・ｎ型拡散層（ソース）１２・・・・・
・ｎ型拡散層（ドレイン）１６・・・・・・ゲート電極
（垂直走査ゲート及び配線）１４・・・・・・Ｐ型半導
体基板
１５・・・・・・配線（垂直信号線）
１８・・・・・・層間膜
２１・・・・・・ｎ型拡散層（ノース）２２・・・・・
・ｎ型拡散１ｄ （ドレイン）２５・・・・・・ゲート
（垂直走置ゲート及び配、！Ｉり２４・・・・・・Ｐ型
半導体基板
２５・・・・・・配線（垂直信号線）
２６・・・・・・酸化膜
２７・・・・・・Ｐ一層
２８・・・・・・層間膜
３１・・・・・・ｎ型拡散１−（ソース）３２・・・・
・・ｎ型拡赦ｆ−（ドレイン）３３・・・・・・ゲート
（水平走査ゲート及び配線）５４・・・・・・Ｐ型半導
体基板
３５・・・・・・配線（水平信号線）
３６・・・・・・酸化膜
３７・・・・・・Ｐ−・讐
３８・・・・・・層間膜
４０・・・・・・配線（垂ＩＭ信号線）０以上
メｌ雪 （１＞）
舅フ」（ｂ）FIG. 1(,) is an Ifr plane view of a unit pixel of a solid-state imaging device according to the present invention, FIG.
) is a circuit diagram of a conventional solid-state imaging device, and Fig. 2(b) is a circuit diagram of a conventional solid-state imaging device.
) is a cross-sectional view of a unit pixel of a conventional solid-state imaging device. 1... Photodiode 2... MOS transistor for vertical scanning switch 3... MOS transistor for horizontal scanning switch 4... Vertical scanning gate and wiring 5.・・・・・・
Horizontal scanning gate and wiring 6... Vertical signal line 7... Horizontal signal line 8... Output end 9... Vertical scanning circuit 10... Horizontal scanning circuit 11...N-type diffusion layer (source) 12...
・N-type diffusion layer (drain) 16...Gate electrode (vertical scanning gate and wiring) 14...P-type semiconductor substrate 15...Wiring (vertical signal line) 18. ...Interlayer film 21...N-type diffusion layer (north) 22...
・N-type diffusion 1d (drain) 25...Gate (vertical scanning gate and wiring, !Iri 24...P-type semiconductor substrate 25...Wiring (vertical signal line) ) 26...Oxide film 27...P layer 28...Interlayer film 31...N-type diffusion 1-(source) 32...
...N-type expanded f- (drain) 33...Gate (horizontal scanning gate and wiring) 54...P-type semiconductor substrate 35...Wiring (horizontal signal line) 36...Oxide film 37...P-, 38...Interlayer film 40...Wiring (vertical IM signal line) 0 or more (1 >) “Father-in-law” (b)
Claims (1)
１次元あるいは２次元状に配置された上記半導体基板と
逆の導電型を有する複数個の拡散層と、からなる複数個
の光電変換素子と、該光電変換素子の光の情報を順次読
み出す上記半導体の上記１主表面に設けられたスイッチ
用ＭＯＳトランジスタと走査回路を備えた固体撮像装置
において、上記スイッチ用ＭＯＳトランジスタのドレイ
ンの拡散層の下および横方向に、上記半導体基板と同一
の導電型の不純物の濃度が低い低濃度不純物層を設けた
ことを特徴とする固体撮像装置。A plurality of photoconductors each comprising a semiconductor substrate of a first conductivity type, and a plurality of diffusion layers having a conductivity type opposite to that of the semiconductor substrate arranged one-dimensionally or two-dimensionally on one main surface of the semiconductor substrate. In a solid-state imaging device comprising a conversion element, a switching MOS transistor provided on the first main surface of the semiconductor for sequentially reading light information of the photoelectric conversion element, and a scanning circuit, diffusion of the drain of the switching MOS transistor is provided. A solid-state imaging device characterized in that a low concentration impurity layer having a low concentration of impurities of the same conductivity type as the semiconductor substrate is provided below the layer and in the lateral direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60217261A JPS6276766A (en) | 1985-09-30 | 1985-09-30 | Solid state image pickup device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60217261A JPS6276766A (en) | 1985-09-30 | 1985-09-30 | Solid state image pickup device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6276766A true JPS6276766A (en) | 1987-04-08 |
Family
ID=16701367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60217261A Pending JPS6276766A (en) | 1985-09-30 | 1985-09-30 | Solid state image pickup device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6276766A (en) |
-
1985
- 1985-09-30 JP JP60217261A patent/JPS6276766A/en active Pending
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