JPS6276661A - Resin sealed type semiconductor device - Google Patents

Resin sealed type semiconductor device

Info

Publication number
JPS6276661A
JPS6276661A JP60216529A JP21652985A JPS6276661A JP S6276661 A JPS6276661 A JP S6276661A JP 60216529 A JP60216529 A JP 60216529A JP 21652985 A JP21652985 A JP 21652985A JP S6276661 A JPS6276661 A JP S6276661A
Authority
JP
Japan
Prior art keywords
resin
bonding
inner leads
lead
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60216529A
Other languages
Japanese (ja)
Inventor
Shinichi Shibata
柴田　進一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60216529A priority Critical patent/JPS6276661A/en
Publication of JPS6276661A publication Critical patent/JPS6276661A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

PURPOSE:To seal a plurality of semiconductor ships in a single resin molded package by using the same lead frame even if the size and the number of the semiconductor chips to be mounted are changed, by using the lead frame, which does not have a bed part, bonding a flexible resin substrate on the back surfaces of the tip parts of inner leads of the frame, and mounting the semiconductor chip thereon. CONSTITUTION:There is no bed part in a region surrounded by tips 11 of inner leads. This region has the largest space being considered in the same package. A flexible resin substrate 12, which is slightly larger than this region, is bonded and fixed to the back surfaces of the tip parts of the inner leads through a thermosetting type bonding agent 13. Even if a bonding wire 16 becomes long, short circuits due to so-called bed touch are not caused. The bonding posts of the inner leads 11 become higher than the bonding surface of semiconductor ships 151 and 152. Even if the wire is bonded between the semiconductor chip 152 and the inner lead, the wire 16 is not contacted with a conduction pattern 14.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は樹脂封止型半導体装置に関し、特に複数個の半
導体素子（以下チップという）を一つのパッケージに組
込んだ樹脂封止型半導体装置の改良に係る。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a resin-sealed semiconductor device, and particularly to a resin-sealed semiconductor device in which a plurality of semiconductor elements (hereinafter referred to as chips) are assembled into one package. Regarding improvements.

〔発明の技術的背景〕[Technical background of the invention]

複数個の半導体チップを単一の樹脂封止パッケージに組
込む場合、従来は通常のリードフレームを用いて行なわ
れていた。Conventionally, when a plurality of semiconductor chips are assembled into a single resin-sealed package, an ordinary lead frame is used.

第３図はその一例を示す図で、樹脂封止前の状態を示す
断面図である。同図において、１はリードフレームのベ
ッド部、２はインナーリード部である。ベッド部１上に
は接着剤層３を介してフレキシブル基板４が貼着されＣ
いる。該フレキシブル基板の表面には所定の導電性パタ
ーン５が形成され、そのパターンに対して所定の位置に
二個の半導体チップ６１．６２がマウントされている。FIG. 3 is a diagram showing an example thereof, and is a sectional view showing a state before resin sealing. In the figure, 1 is a bed portion of the lead frame, and 2 is an inner lead portion. A flexible substrate 4 is pasted on the bed portion 1 via an adhesive layer 3.
There is. A predetermined conductive pattern 5 is formed on the surface of the flexible substrate, and two semiconductor chips 61 and 62 are mounted at predetermined positions with respect to the pattern.

そして、半導体チップ６１．６２はボンディングワイヤ
７を介して前記導電性パターン５、または前記インナー
リード２との間に必要な接続がなされている。こうして
アセンブリーされた状態を樹脂封止することにより、外
観的には単一の樹脂モールドパッケージ内に二個の半導
体チップを封止した樹脂封止型半導体装置が製造されて
いる。The semiconductor chips 61 and 62 are connected to the conductive pattern 5 or the inner leads 2 via bonding wires 7 as necessary. By resin-sealing the thus assembled state, a resin-sealed semiconductor device is manufactured in which externally, two semiconductor chips are sealed in a single resin mold package.

〔背景技術の問題点〕[Problems with background technology]

上記従来の樹脂封止型半導体装置では、樹脂パッケージ
内に封止する半導体チップの数や大きさ等によって使用
するリードフレームにおけるベッド部の大きさや、イン
ナーリード部の配置を変更しなければならない問題があ
る。The conventional resin-sealed semiconductor device described above has the problem of having to change the size of the bed part of the lead frame used and the arrangement of the inner lead part depending on the number and size of semiconductor chips to be sealed in the resin package. There is.

例えば第４図に示すように、図示の断面では一個の半導
体チップ６のみがマウントされる場合、第３図の場合と
同じリードフレームを用いてアセンブリーするとすれば
、半導体チ・ツブ６から直接インナーリードに接続する
ボンディングワイヤ７が長くなり、図中Ｔで示すような
ベッドタッチによる短絡生じることになる。For example, as shown in FIG. 4, when only one semiconductor chip 6 is mounted in the cross section shown, if the assembly is performed using the same lead frame as in FIG. The bonding wire 7 connected to the lead becomes long, and a short circuit as shown by T in the figure due to bed touch occurs.

また、第３図と同じリードフレームを用いてより多数の
半導体チップ６１〜６３をマウントする場合には、第５
図に示すように大きいフレキシブル基板４′を用いなけ
ればならないから、フレキシブル基板４′がインナーリ
ード部２の近傍上にまで延在することになる。このため
、半導体チップ６３から直接インナーリード２に接続す
るボンディングワイヤ７は、フレキシブル基板の端部に
接触し、導電性パターン５との間で短絡を生じてしまう
。In addition, when mounting a larger number of semiconductor chips 61 to 63 using the same lead frame as in FIG.
As shown in the figure, since a large flexible substrate 4' must be used, the flexible substrate 4' extends close to the inner lead portion 2. Therefore, the bonding wire 7 directly connected from the semiconductor chip 63 to the inner lead 2 comes into contact with the end of the flexible substrate, causing a short circuit with the conductive pattern 5.

従って、上記のような問題を回避するためには、Ａこ 夫々の場合ｐ応じてフレキシブル基板の寸法だけでなく
、リードフレームそのものを変更しなければならない。Therefore, in order to avoid the above-mentioned problems, it is necessary to change not only the dimensions of the flexible substrate but also the lead frame itself in accordance with each case of A and P.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情に鑑みてなされたもので、搭載する半
導体チップの大きさや個数が変っても、同じリードフレ
ームを用いてこれら複数の半導体チップを単一の樹脂モ
ールドパッケージ内に封止することができる樹脂封止型
半導体装置を提供するものである。The present invention has been made in view of the above circumstances, and it is possible to encapsulate a plurality of semiconductor chips in a single resin mold package using the same lead frame even if the size or number of semiconductor chips to be mounted changes. The object of the present invention is to provide a resin-sealed semiconductor device that can be used.

〔発明の概要〕[Summary of the invention]

本発明による樹脂封止型半導体装置は、インナーリード
先端が所定の領域を領域を取囲むように配置されたリー
ドと、該リードのインナーリード先端部裏面に接着固定
された前記所定領域よりも大きい形状を有するフレキシ
ブル樹脂基板と、該フレキシブル基板上にマウントされ
た複数個の半導体チップと、該半導体チップと前記イン
ナーリードの間に必要な接続を行なうボンディングワイ
ヤと、前記インナーリード、前記フレキシブル樹脂基板
、前記複数の半導体チップ及び前記ボンディングワイヤ
を封止する単一の樹脂モールド層とを具備したことを特
徴とするものである。The resin-sealed semiconductor device according to the present invention includes a lead whose inner lead tip is arranged so as to surround a predetermined area, and a lead which is larger than the predetermined area and which is adhesively fixed to the back surface of the inner lead tip of the lead. a flexible resin substrate having a shape, a plurality of semiconductor chips mounted on the flexible substrate, bonding wires for making necessary connections between the semiconductor chips and the inner leads, the inner leads, and the flexible resin substrate. , a single resin mold layer sealing the plurality of semiconductor chips and the bonding wire.

上記本発明による樹脂封止型半導体装置は、リードパタ
ーンだけでベッド部がないリードフレームを用い、該リ
ードフレームのインナーリード先端部裏面にフレキシブ
ル樹脂基板を接着してその上に半導体チップをマウント
するようにすれば、後は従来の樹脂封止型半導体装置と
同様にして製造することができる。The resin-sealed semiconductor device according to the present invention uses a lead frame with only a lead pattern and no bed part, and a flexible resin substrate is bonded to the back surface of the inner lead tip of the lead frame, and a semiconductor chip is mounted on the flexible resin substrate. By doing so, the rest can be manufactured in the same manner as a conventional resin-sealed semiconductor device.

その場合、リードフレームのインナーリード先端で囲ま
れた領域（通常のリードフレームではベッド部がある場
所）を大きめに取っておけば、半導体チップの大きさや
個数、更には配列が変っても、従来のようにボンディン
グ不良を生じることなく同じリードフレームを用いて実
施できる利点がある。In that case, if you set aside a larger area surrounded by the tips of the inner leads of the lead frame (where the bed is located in a normal lead frame), even if the size, number, or even arrangement of semiconductor chips changes, There is an advantage that the same lead frame can be used without causing bonding defects.

なお、本発明におけるフレキシブル樹脂基板としては、
ガラスエポキシ樹脂膜、ポリイミド樹脂膜等を用いるこ
とができる。Note that the flexible resin substrate in the present invention includes:
A glass epoxy resin film, a polyimide resin film, etc. can be used.

〔発明の実施例〕[Embodiments of the invention]

第３図は本発明の一実施例になる樹脂封止型半導体装置
を説明するための図で、樹脂封止前のアセンブリー状態
を示す断面図である。同図において、１１はリードフレ
ームのインナーリード部分である。該インナーリード先
端で囲まれる領域には通常のリードフレームにおけるベ
ッド部は存在せず、またこの領域は同一パッケージで考
えられる最大のスペースになっている。そして、この領
域よりもやや大きいフレキシブル樹脂基板１２が、前記
インナーリード先端部の裏面に熱硬化型接着剤１３を介
して接着固定されている。該フレキシブル樹脂基板１２
は厚さ０．１　ｙ〜０．３賭のポリイミド樹脂膜からな
り、その上には厚さ３５４のＣｕ箔および厚さ　５〜２
０ｘのＮｉメッキ層、更に厚さ３〜５ｐのＡｇメッキ層
または厚さ０．５〜１．０ｐのＡｕメッキ層を積層した
導電性パターン１４が形成されている。そして、このフ
レキシブル樹脂基板１２の所定位置には半導体チップ１
５１゜１５２がエポキシ導電性ペースト等でマウントさ
れ、且つキュアされている。更に、半導体チップ１５＋
　、１５２は夫々ボンディングワイヤ１６を介してイン
ナーリード１１、導電性パターン１４と接続されている
。この実施例になる樹脂封止型半導体装置は、第１図の
状態にアセンブリーした後に所定の封止領域を樹脂モー
ルド層で封止した構造を有している。FIG. 3 is a diagram for explaining a resin-sealed semiconductor device according to an embodiment of the present invention, and is a sectional view showing an assembled state before resin-sealing. In the figure, 11 is an inner lead portion of the lead frame. In the area surrounded by the tips of the inner leads, there is no bed part in a normal lead frame, and this area is the largest possible space in the same package. A flexible resin substrate 12, which is slightly larger than this area, is adhesively fixed to the back surface of the tip of the inner lead via a thermosetting adhesive 13. The flexible resin substrate 12
consists of a polyimide resin film with a thickness of 0.1 to 0.3 mm, on which is a Cu foil with a thickness of 35 mm and a layer of 5 to 2 mm thick.
A conductive pattern 14 is formed by laminating a 0x Ni plating layer, and further a 3-5p thick Ag plating layer or a 0.5-1.0p thick Au plating layer. A semiconductor chip 1 is placed at a predetermined position on this flexible resin substrate 12.
51.degree. 152 are mounted with epoxy conductive paste or the like and cured. Furthermore, semiconductor chip 15+
, 152 are connected to the inner lead 11 and the conductive pattern 14 via bonding wires 16, respectively. The resin-sealed semiconductor device of this embodiment has a structure in which a predetermined sealing area is sealed with a resin mold layer after being assembled in the state shown in FIG.

上記実施例の樹脂封止型半導体装置では、第１図に示し
たように従来例と違ってベッド部が存在せず、従ってボ
ンディングワイヤ１６が長くなっても所謂ベッドタッチ
による短絡といったボンディング不良を生じることがな
い。また、フレキシブル樹脂基板１２がインナーリード
１１の裏面に貼着されているため、図示のようにインナ
ーリード１１のボンディングポストは半導体チップ１５
＋、１５２のボンディング面よりもレベルが高くなる。Unlike the conventional example, the resin-sealed semiconductor device of the above embodiment does not have a bed portion, as shown in FIG. It never occurs. Furthermore, since the flexible resin substrate 12 is attached to the back surface of the inner lead 11, the bonding post of the inner lead 11 is attached to the semiconductor chip 15 as shown in the figure.
+, the level is higher than the bonding surface of 152.

従って、インナーリードに近接して配置された半導体チ
ップ１５２とインナーリードとの間にワイヤボンディン
グを行なっても、ボンディングワイヤ１６がフレキシブ
ル樹脂基板」二の導電性パターン１４に接触して生じる
ボンディング不良を回避することができる。Therefore, even if wire bonding is performed between the semiconductor chip 152 and the inner leads, which are placed close to the inner leads, bonding defects caused by the bonding wires 16 coming into contact with the conductive patterns 14 of the flexible resin substrate are avoided. can be avoided.

このため、第２図に示すように半導体チップ１５＋　、
１５２の大きさや配列が違ったり、またマウントする半
導体チップの数が多くなったり少なくなったりした場合
にも、何等の問題を生じることなく第１図と同じリード
フレームを用いて製造することができる。Therefore, as shown in FIG. 2, the semiconductor chips 15+,
Even if the size or arrangement of the 152 is different, or if the number of semiconductor chips to be mounted is increased or decreased, it can be manufactured using the same lead frame as shown in Figure 1 without any problems. .

〔発明の効果〕〔Effect of the invention〕

以上詳述したように、本発明による樹脂封止型半導体装
置は、搭載する半導体チップの大きさや個数が変っても
、何等の問題を生じることなく、同じリードフレームを
用いてこれら複数の半導体チップを単一の樹脂モールド
パッケージ内に封止できる等、顕著な効果を奏するもの
である。As described in detail above, the resin-sealed semiconductor device according to the present invention does not cause any problems even if the size or number of semiconductor chips to be mounted changes, and the same lead frame can be used to accommodate multiple semiconductor chips. It has remarkable effects, such as being able to seal everything in a single resin mold package.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例になる樹脂封止型半導体装置
における樹脂封止前のアセンブリー状態を示す断面図、
第２図は第１図の実施例と同じリードフレームを用い、
且つ搭載する半導体チップの配列および大きさを変えた
他の実施例における樹脂封止前のアセンブリー状態を示
す断面図、第３図は従来の樹脂封止型半導体装置におけ
る樹脂封止前のアセンブリー状態を示す断面図、第４図
および第５図は従来の樹脂封止型半導体装置の問題点を
説明するための断面図である。 １１−・・インナーリード、１２・・・フレキシブル樹
脂猜板、１３・・・熱硬化型接着剤層、１４・・・導電
性パターン、１５１，１５２・・・半導体チップ、１６
・・・ボンディングワイヤ 出願人代理人　弁理士　鈴江武彦 Ｚ 第１図 第３図 ち 第４図FIG. 1 is a sectional view showing an assembly state before resin sealing in a resin-sealed semiconductor device according to an embodiment of the present invention;
Figure 2 uses the same lead frame as the example in Figure 1,
In addition, it is a sectional view showing an assembly state before resin sealing in another embodiment in which the arrangement and size of the semiconductor chips to be mounted are changed, and FIG. 3 is an assembly state before resin sealing in a conventional resin-sealed semiconductor device. FIGS. 4 and 5 are cross-sectional views for explaining problems with conventional resin-sealed semiconductor devices. DESCRIPTION OF SYMBOLS 11-- Inner lead, 12... Flexible resin board, 13... Thermosetting adhesive layer, 14... Conductive pattern, 151, 152... Semiconductor chip, 16
...Bonding wire applicant's representative Patent attorney Takehiko Suzue Z Figure 1 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] インナーリード先端が所定の領域を領域を取囲むように
配置されたリードと、該リードのインナーリード先端部
裏面に接着固定された前記所定領域よりも大きい形状を
有するフレキシブル樹脂基板と、該フレキシブル基板上
にマウントされた複数個の半導体チップと、該半導体チ
ップと前記インナーリードの間に必要な接続を行なうボ
ンディングワイヤと、前記インナーリード、前記フレキ
シブル樹脂基板、前記複数の半導体チップ及び前記ボン
ディングワイヤを封止する単一の樹脂モールド層とを具
備したことを特徴とする樹脂封止型半導体装置。a lead arranged such that the tip of the inner lead surrounds a predetermined area; a flexible resin substrate having a shape larger than the predetermined area adhesively fixed to the back surface of the tip of the inner lead of the lead; and the flexible substrate a plurality of semiconductor chips mounted thereon, bonding wires for making necessary connections between the semiconductor chips and the inner leads, and the inner leads, the flexible resin substrate, the plurality of semiconductor chips, and the bonding wires; 1. A resin-sealed semiconductor device comprising a single resin mold layer for sealing.
JP60216529A 1985-09-30 1985-09-30 Resin sealed type semiconductor device Pending JPS6276661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60216529A JPS6276661A (en) 1985-09-30 1985-09-30 Resin sealed type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60216529A JPS6276661A (en) 1985-09-30 1985-09-30 Resin sealed type semiconductor device

Publications (1)

Publication Number Publication Date
JPS6276661A true JPS6276661A (en) 1987-04-08

Family

ID=16689859

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60216529A Pending JPS6276661A (en) 1985-09-30 1985-09-30 Resin sealed type semiconductor device

Country Status (1)

Country Link
JP (1) JPS6276661A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0378209A2 (en) * 1989-01-11 1990-07-18 Kabushiki Kaisha Toshiba Hybrid resin-sealed semiconductor device
US5420751A (en) * 1990-08-01 1995-05-30 Staktek Corporation Ultra high density modular integrated circuit package
US5446620A (en) * 1990-08-01 1995-08-29 Staktek Corporation Ultra high density integrated circuit packages
US5585668A (en) * 1995-01-30 1996-12-17 Staktek Corporation Integrated circuit package with overlapped die on a common lead frame

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0378209A2 (en) * 1989-01-11 1990-07-18 Kabushiki Kaisha Toshiba Hybrid resin-sealed semiconductor device
US5420751A (en) * 1990-08-01 1995-05-30 Staktek Corporation Ultra high density modular integrated circuit package
US5446620A (en) * 1990-08-01 1995-08-29 Staktek Corporation Ultra high density integrated circuit packages
US5543664A (en) * 1990-08-01 1996-08-06 Staktek Corporation Ultra high density integrated circuit package
US6049123A (en) * 1990-08-01 2000-04-11 Staktek Corporation Ultra high density integrated circuit packages
US5585668A (en) * 1995-01-30 1996-12-17 Staktek Corporation Integrated circuit package with overlapped die on a common lead frame
US5615475A (en) * 1995-01-30 1997-04-01 Staktek Corporation Method of manufacturing an integrated package having a pair of die on a common lead frame

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