JPS6271755U - - Google Patents
Info
- Publication number
- JPS6271755U JPS6271755U JP16021585U JP16021585U JPS6271755U JP S6271755 U JPS6271755 U JP S6271755U JP 16021585 U JP16021585 U JP 16021585U JP 16021585 U JP16021585 U JP 16021585U JP S6271755 U JPS6271755 U JP S6271755U
- Authority
- JP
- Japan
- Prior art keywords
- reset
- microcomputers
- confirmation operation
- response confirmation
- internal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012790 confirmation Methods 0.000 claims 2
- 230000005856 abnormality Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
- Multi Processors (AREA)
Description
図面はこの考案のコンピユータ装置の1実施例
を示し、第1図はブロツク図、第2図は第1図の
動作説明用のフローチヤートである。
1,2…第1、第2マイコン、3,4…第1、
第2リセツト回路、RSI…リセツト入力端子、
RSO…リセツト出力端子。
The drawings show one embodiment of the computer device of this invention, and FIG. 1 is a block diagram, and FIG. 2 is a flowchart for explaining the operation of FIG. 1. 1, 2...first, second microcontroller, 3,4...first,
Second reset circuit, RSI...reset input terminal,
RSO...Reset output terminal.
Claims (1)
称する)により構成され、2つ以上のマイコン間
で応答確認動作を伴なつた通信を行なうコンピユ
ータ装置において、前記各マイコンに、前記応答
確認動作によつて異常を検出したときにリセツト
出力を行なうリセツト出力端子と、前記リセツト
出力から一定期間内部リセツトを行なう内部リセ
ツト手段とを設け、かつ前記各リセツト出力端子
それぞれに他のマイコンにリセツトをかけるリセ
ツト回路を接続したコンピユータ装置。 In a computer device that is composed of a plurality of microcomputers (hereinafter referred to as microcomputers) and performs communication accompanied by a response confirmation operation between two or more microcomputers, an abnormality is detected in each of the microcomputers by the response confirmation operation. A computer is provided with a reset output terminal that outputs a reset when the microcomputer is reset, and an internal reset means that performs an internal reset for a certain period of time from the reset output, and a reset circuit that resets other microcomputers is connected to each of the reset output terminals. Device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16021585U JPS6271755U (en) | 1985-10-19 | 1985-10-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16021585U JPS6271755U (en) | 1985-10-19 | 1985-10-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6271755U true JPS6271755U (en) | 1987-05-08 |
Family
ID=31085383
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16021585U Pending JPS6271755U (en) | 1985-10-19 | 1985-10-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6271755U (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5597647A (en) * | 1979-01-20 | 1980-07-25 | Oki Electric Ind Co Ltd | Fault monitor system for multi-processor control system |
JPS55127652A (en) * | 1979-03-26 | 1980-10-02 | Hitachi Ltd | Mutual supervision system between computers |
JPS57130131A (en) * | 1981-02-03 | 1982-08-12 | Nippon Denso Co Ltd | Multiple computer device |
JPS582047B2 (en) * | 1979-11-15 | 1983-01-13 | 三菱鉱業セメント株式会社 | Method for partially reinforcing cementum tubes |
-
1985
- 1985-10-19 JP JP16021585U patent/JPS6271755U/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5597647A (en) * | 1979-01-20 | 1980-07-25 | Oki Electric Ind Co Ltd | Fault monitor system for multi-processor control system |
JPS55127652A (en) * | 1979-03-26 | 1980-10-02 | Hitachi Ltd | Mutual supervision system between computers |
JPS582047B2 (en) * | 1979-11-15 | 1983-01-13 | 三菱鉱業セメント株式会社 | Method for partially reinforcing cementum tubes |
JPS57130131A (en) * | 1981-02-03 | 1982-08-12 | Nippon Denso Co Ltd | Multiple computer device |
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