JPS6269696A - Electrolessly plating method for printed circuit board - Google Patents

Electrolessly plating method for printed circuit board

Info

Publication number
JPS6269696A
JPS6269696A JP21068785A JP21068785A JPS6269696A JP S6269696 A JPS6269696 A JP S6269696A JP 21068785 A JP21068785 A JP 21068785A JP 21068785 A JP21068785 A JP 21068785A JP S6269696 A JPS6269696 A JP S6269696A
Authority
JP
Japan
Prior art keywords
catalyst
electroless plating
resist
printed wiring
plating method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21068785A
Other languages
Japanese (ja)
Inventor
敏行 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP21068785A priority Critical patent/JPS6269696A/en
Publication of JPS6269696A publication Critical patent/JPS6269696A/en
Pending legal-status Critical Current

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  • Chemically Coating (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 発明の背景 プリント配線基板を無電解メッキする方法はフルアデイ
テイブ方式として知られている、この方法は回路形成面
に接着剤を塗布し又はしないで絶縁板の面を粗化中和し
、その全面にメッキ反応の触媒を付与し活性化する、次
いで乾燥後回路形成部以外にレジスト層を形成する、次
いで無電解メッキ液に浸漬し、その時間を変えることに
よって必要厚の金属を回路形成部にのみ析出させる方法
である、 しかし、この方法で得られるプリント配線板は回路と回
路との間隔、即ち、回路間隔となっているレジスト層の
下にメッキ反応の触媒が残存している、このため、プリ
ント配線板を温湿度下に放置すると回路間絶縁抵抗が大
きく低下する欠点を有している、 発明の目的 本発明の目的は、前記欠点を解決し、絶縁抵抗の大きい
プリント配線板をつくる方法である、発明の概要 本発明は絶縁板を粗化中和した後、その全面にメッキ反
応の触媒を付与して活性化し、次いで乾燥後回路形成部
以外にレジスト層を形成するのでなく、絶縁板を粗化中
和した後乾燥し、次いで回路形成部以外に無電解メッキ
用レジストインクを塗布し、次いで触媒液に浸漬して、
回路形成部のみに触媒を付与して活性化し、次いで無電
解メッキする方法である、即ち、この方法によれば、回
路間隔となっているレジスト層の下にメッキ反応の触媒
が存在しないため、温湿度下に放置しても回路間絶縁抵
抗が低下することは全くなくなる、本方法で触媒液に浸
漬すると、回路形成部は粗化されたままの状態であるた
め、この部には触媒が極めて強く付着するが、回路形成
部以外の粗化面はレジスト皮膜層により完全に隠蔽され
ているため、触媒が付着しなくなる、 又触媒が付着したとしても、極めて弱い状態であるため
、これを除去することは容易であり、その方法は任意で
あるが、特に両者の触媒の付着度の極めて大きな差を利
用して、全面を水洗することにより、回路形成部の触媒
は除去せず、回路形成部以外のレジスト皮膜面に極めて
弱く付着した触媒を除去することは容易であり、生産的
にも、又経済的にも極めて好しい方法である、水洗を加
圧水洗にしたり、又は加温水洗にしたり、振動水洗(た
とえば、超音波水洗)にしたりすると、その効果が更に
倍加する、 水洗いの程度は、当然、レジスト面の弱く付着した触媒
は除去されるが、回路形成部に強く付着した触媒は残存
していて、良好な無電解メッキが行なわれる程度でなけ
ればならない、 レジストインクを塗布した後の皮膜は、これを触媒液に
浸漬した時に、その上に触媒が付着しないものが最も好
しい、 又付着したにしても、水洗等の方法により容易に除去で
きる程度の弱い付着が好しい このために、レジストインクに硬化剤を加えておき、こ
れを塗布してレジン層を形成した後、これを硬化して硬
化レジストにすると、本効果は更に大になる、これは十
分に硬化した方がより効果が大になる、 又レジストインクに、シリコーンオイル、弗素系オイル
、パラフィン等の離型剤、可塑剤、軟化剤等を加えてお
くと、レジスト皮膜面にこれらがブリードして触媒の付
着は更にむずかしくなり、これも極めて好しい方法であ
る、 これらの薬品は絶縁性の大きいものが特に好しい、しか
し、ブリードが激しく、回路形成部にまでにじみでて、
触媒の付着を弱くし、良好な無電解メッキができなくな
る量であってはならない、本発明は無電解メッキした後
にレジスト皮膜面に弱く付着した触媒をメッキされた金
属と共に除去する場合も当然含むが、それだけでなくメ
ッキされた金属により弱く付着し触媒の除去がより容易
になり好しいが、しかし、メッキされた金属がロスとな
り、メッキ液の汚れも大きくなり、無電解メッキを行う
前に触媒を除去する方が経済的にも生産的にもより好し
い、 実施例 紙フエノール積層板に接着剤を塗布したものを絶縁板と
して用い、クロム硫酸混液にてエツチングして粗化した
、次いでアルカリ液にて中和して粗化残査物を除去し、
次いでこれを水洗して清淨にした後乾燥し、次いで下記
組成の無電解メッキ用レジストインクを絶縁板の回路形
成部以外に塗布し、150℃で30分硬化してレジスト
層を形成した、 次いで13%塩酸に浸漬し、直ちに塩化パラジウム、塩
化第一スズ、塩酸とからなる触媒液に浸漬し、回路形成
部に触媒成分を強く付着させた、この時、レジスト層面
には触媒成分が極めて弱く付着していた、次いで加圧温
水で水洗したところ、レジスト面の触媒成分は容易に除
去されたが回路形成部の触媒成分は強固に付着していた
、次いで100℃で10分間乾燥を行った、次いで下記
組成の無電解メッキ液で70℃で10時間メッキを行い
、回路形成部に金属銅を析出させた、次いで5%硫酸で
中和した後、150℃で40分間乾燥し、室温まで冷却
し、プリント配線板とした、 次いでD.C.500Vで初期の絶縁抵抗と40℃、9
0〜95%RHの温湿度槽に96時間放置した後の絶縁
抵抗を測定したところ全く変化なく、3×1012Ωと
極めて大きかった、 無電解メッキ用レジストインク組成(重量)エポキシレ
ジンービスフエノールA型エポキシ100部酸化ケイ素
 2部 フイラー 5部着色剤 5部 シリコーンオイ
ル 2部 アクリル酸エステルコポリマー 3部 オイ
レン酸ザルコシン 1部 メチルカルビトール 40部
 ジアミノ、ジフエニルメタン 13部 2エチル4メ
チルイミダゾール 0.5部 無電解メッキ液組成(1l中の量) 硫酸銅 8〜10g エチレンジアミン四酢酸30g 
37%ホルマリン 1〜3ml 水酸化ナトリウム 1
0〜12g ポリエチレングリコール(分子量400)
20ml ジピリジン 25mg
[Detailed Description of the Invention] Background of the Invention The method of electroless plating printed wiring boards is known as the fully additive method, which roughens the surface of the insulating board with or without applying an adhesive to the circuit forming surface. Neutralize, apply a plating reaction catalyst to the entire surface and activate it, then after drying, form a resist layer on areas other than the circuit forming area, then immerse in electroless plating solution and change the time to achieve the required thickness. This is a method in which the metal is deposited only in the circuit formation area.However, in the printed wiring board obtained by this method, the catalyst for the plating reaction remains in the gaps between the circuits, that is, under the resist layer that forms the circuit gaps. Therefore, when a printed wiring board is left under temperature and humidity, the insulation resistance between the circuits decreases significantly.Objective of the InventionThe object of the present invention is to solve the above-mentioned drawbacks and to improve the insulation resistance. Summary of the Invention This invention is a method for making large printed wiring boards.The present invention roughens and neutralizes an insulating board, then applies a plating reaction catalyst to the entire surface to activate it, and then, after drying, a resist layer is formed on areas other than the circuit forming area. Rather than forming an insulating plate, the insulating plate is roughened and neutralized, then dried, then a resist ink for electroless plating is applied to areas other than the circuit forming area, and then immersed in a catalyst liquid.
This is a method in which a catalyst is applied and activated only to the circuit forming area, and then electroless plating is performed. In other words, according to this method, there is no catalyst for the plating reaction under the resist layer that is the circuit interval. Even if the insulation resistance between the circuits is left exposed to temperature and humidity, there will be no reduction in the insulation resistance between the circuits.When immersed in the catalyst solution using this method, the circuit forming part remains roughened, so there is no catalyst in this part. Although it adheres extremely strongly, the roughened surface other than the circuit formation area is completely hidden by the resist film layer, so the catalyst will not adhere, and even if the catalyst does adhere, it will be in an extremely weak state, so it should be avoided. It is easy to remove, and the method is arbitrary, but in particular, by taking advantage of the extremely large difference in the degree of adhesion of the two catalysts and washing the entire surface with water, the circuit can be removed without removing the catalyst in the circuit forming area. It is easy to remove the catalyst that is very weakly attached to the resist film surface other than the forming area, and it is an extremely preferable method from both productivity and economical standpoints, such as pressurized water washing or heated water washing. The effect is further doubled when the catalyst is washed with water or vibratory water (for example, ultrasonic water washing).The degree of water washing naturally removes the catalyst that is weakly attached to the resist surface, but it removes the catalyst that is strongly attached to the circuit forming area. The catalyst must remain to a sufficient extent that good electroless plating can be performed.The film after applying the resist ink is best if no catalyst adheres to it when it is immersed in the catalyst solution. Preferably, even if it does adhere, it is preferable that the adhesion be weak enough to be easily removed by washing with water.For this reason, a hardening agent is added to the resist ink and this is applied to form a resin layer. This effect will be even greater if this is then cured to form a hardened resist.This effect will be even greater if it is sufficiently cured.Additionally, the resist ink may contain silicone oil, fluorine-based oil, paraffin, etc. Adding a mold release agent, plasticizer, softener, etc. will cause these to bleed onto the resist film surface, making it even more difficult for the catalyst to adhere. This is also an extremely preferable method. These chemicals have high insulating properties. I particularly like it, but it bleeds heavily and bleeds into the circuit forming part.
The amount must not be such that it weakens the adhesion of the catalyst and prevents good electroless plating.The present invention naturally also includes the case where the catalyst weakly adhered to the resist film surface is removed together with the plated metal after electroless plating. However, this is preferable because it adheres more weakly to the plated metal, making it easier to remove the catalyst. It is more economical and productive to remove the catalyst.Example A paper phenol laminate coated with adhesive was used as an insulating plate, roughened by etching with a chromium sulfuric acid mixture, and then Neutralize with alkaline solution to remove roughening residue,
Next, this was washed with water to make it clean and then dried, and then a resist ink for electroless plating having the following composition was applied to areas other than the circuit forming part of the insulating plate and cured at 150°C for 30 minutes to form a resist layer. It was immersed in 13% hydrochloric acid, and then immediately immersed in a catalyst solution consisting of palladium chloride, stannous chloride, and hydrochloric acid to strongly adhere the catalyst component to the circuit forming part. At this time, the catalyst component was extremely weak on the resist layer surface. Then, when washed with pressurized hot water, the catalyst component on the resist surface was easily removed, but the catalyst component in the circuit forming part was firmly attached.Next, it was dried at 100°C for 10 minutes. Then, plating was performed at 70°C for 10 hours with an electroless plating solution having the following composition to deposit metallic copper on the circuit forming part.Next, after neutralizing with 5% sulfuric acid, it was dried at 150°C for 40 minutes and brought to room temperature. It was cooled and made into a printed wiring board, and then D. C. Initial insulation resistance at 500V and 40℃, 9
Resist ink composition for electroless plating (weight) Epoxy resin-bisphenol A Type epoxy 100 parts Silicon oxide 2 parts Filler 5 parts Colorant 5 parts Silicone oil 2 parts Acrylic acid ester copolymer 3 parts Sarcosine oleate 1 part Methyl carbitol 40 parts Diamino, diphenylmethane 13 parts 2 Ethyl 4-methylimidazole 0.5 parts None Electrolytic plating solution composition (amount per liter) Copper sulfate 8-10g Ethylenediaminetetraacetic acid 30g
37% formalin 1-3ml Sodium hydroxide 1
0-12g polyethylene glycol (molecular weight 400)
20ml dipyridine 25mg

Claims (1)

【特許請求の範囲】 1、粗化した絶縁板の回路形成部以外に無電解メッキ用
レジストインクを塗布した後、触媒液に浸漬し、次いで
無電解メッキすることにより回路形成部にメッキするこ
とを特徴とするプリント配線基板の無電解メッキ法 2、レジストインクに硬化剤を加えておき、これを塗布
した後硬化する特許請求の範囲第1項記載のプリント配
線基板の無電解メッキ法 3、レジストインクに、この皮膜面に触媒が付着しない
か又はしにくくなる薬品を加える特許請求の範囲第1項
又は第2項記載のプリント配線基板の無電解メッキ法 4、触媒液に浸漬した時、レジスト皮膜面に触媒が弱く
付着する場合は、これを除去する特許請求の範囲第1項
又は第2項又は第3項記載プリント配線基板の無電解メ
ッキ法 5、触媒液に浸漬した時、レジスト皮膜面に触媒が弱く
付着する場合は、これを水洗により除去する特許請求の
範囲第1項又は第2項又は第3項又は第4項記載のプリ
ント配線基板の無電解メッキ法
[Claims] 1. After applying a resist ink for electroless plating to areas other than the circuit forming area of the roughened insulating plate, immersing the insulating plate in a catalyst solution, and then electroless plating to plate the circuit forming area. 2. Electroless plating method for printed wiring boards 2, characterized in that a curing agent is added to the resist ink, and the method 3 for electroless plating of printed wiring boards according to claim 1, in which a curing agent is added to the resist ink and the resist ink is cured after being applied. Electroless plating method for printed wiring boards according to claim 1 or 2, in which a chemical is added to the resist ink to prevent or prevent catalyst from adhering to the film surface, when immersed in a catalyst solution, If the catalyst weakly adheres to the resist film surface, it is removed. Electroless plating method for printed wiring boards according to claim 1, 2 or 3, 5, when immersed in a catalyst solution, the resist Electroless plating method for printed wiring boards according to claim 1 or 2 or 3 or 4, in which if the catalyst weakly adheres to the film surface, it is removed by washing with water.
JP21068785A 1985-09-24 1985-09-24 Electrolessly plating method for printed circuit board Pending JPS6269696A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21068785A JPS6269696A (en) 1985-09-24 1985-09-24 Electrolessly plating method for printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21068785A JPS6269696A (en) 1985-09-24 1985-09-24 Electrolessly plating method for printed circuit board

Publications (1)

Publication Number Publication Date
JPS6269696A true JPS6269696A (en) 1987-03-30

Family

ID=16593439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21068785A Pending JPS6269696A (en) 1985-09-24 1985-09-24 Electrolessly plating method for printed circuit board

Country Status (1)

Country Link
JP (1) JPS6269696A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07297520A (en) * 1994-04-20 1995-11-10 Nec Corp Manufacture of printed wiring board
JPH08199367A (en) * 1995-01-20 1996-08-06 Kenseidou Kagaku Kogyo Kk Formation of contact metallic layer on optional surface part of resin molded good
US6709803B2 (en) 2001-02-26 2004-03-23 Nec Toppan Circuit Solutions, Inc. Process for producing printed wiring board
JP2009302081A (en) * 2008-06-10 2009-12-24 Sulfur Chemical Institute Inc Method for producing molded interconnect device
JP5418497B2 (en) * 2008-06-11 2014-02-19 コニカミノルタ株式会社 Metal pattern forming method and metal pattern

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07297520A (en) * 1994-04-20 1995-11-10 Nec Corp Manufacture of printed wiring board
JPH08199367A (en) * 1995-01-20 1996-08-06 Kenseidou Kagaku Kogyo Kk Formation of contact metallic layer on optional surface part of resin molded good
US6709803B2 (en) 2001-02-26 2004-03-23 Nec Toppan Circuit Solutions, Inc. Process for producing printed wiring board
JP2009302081A (en) * 2008-06-10 2009-12-24 Sulfur Chemical Institute Inc Method for producing molded interconnect device
JP5418497B2 (en) * 2008-06-11 2014-02-19 コニカミノルタ株式会社 Metal pattern forming method and metal pattern

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