JPS6268015A - Inspecting circuit for protecting device - Google Patents
Inspecting circuit for protecting deviceInfo
- Publication number
- JPS6268015A JPS6268015A JP60209349A JP20934985A JPS6268015A JP S6268015 A JPS6268015 A JP S6268015A JP 60209349 A JP60209349 A JP 60209349A JP 20934985 A JP20934985 A JP 20934985A JP S6268015 A JPS6268015 A JP S6268015A
- Authority
- JP
- Japan
- Prior art keywords
- input
- inspection
- circuit
- input device
- judgment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Emergency Protection Circuit Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は保護装置の点検回路に関し、例えば母線保護装
置等に適用できる点検回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a test circuit for a protection device, and relates to a test circuit applicable to, for example, a busbar protection device.
第３図は最も一般的に行われている文献三菱電機技報に
示された従来の母線保護装置点検回路の接続図例で、（
１）は線路または母線等の電力系統、（２）は線路等に
接続されている変流器、（３）は母線保護リレー用入力
装置、（４Ａ）、（４Ｂ）、（４ｃ）は抑制トランス、
（ｅＡ）、（５Ｂ）、（’５ｃ）は差動トランス、（６
Ａ）。Figure 3 is an example of a connection diagram of a conventional bus protection device inspection circuit shown in the most commonly used document, Mitsubishi Electric Technical Report.
1) is a power system such as a line or bus bar, (2) is a current transformer connected to a line, etc., (3) is an input device for a bus protection relay, and (4A), (4B), and (4c) are suppression Trance,
(eA), (5B), ('5c) are differential transformers, (6
A).
（６Ｂ）、（ｆ３Ｃ）は抑制回路点検巻線、（７ｈ）
、 （７Ｂ） 、 （ツＣ）は抑制トランス２次巻線、
（８Ａ）、（８Ｂ）、（８Ｃ）、（８Ｄ）は抑制回路リ
ード線、（９）は点検判定要素、（１０は母線保護リレ
ー、０υは点検電源トランス、等からなる母線保護装置
の点検回路である。(6B), (f3C) are suppression circuit inspection windings, (7h)
, (7B) and (tsuC) are the secondary windings of the suppression transformer,
(8A), (8B), (8C), (8D) are the suppression circuit lead wires, (9) is the inspection judgment element, (10 is the bus protection relay, 0υ is the inspection power transformer, etc.) Inspection of the bus protection device It is a circuit.
次に動作について説明する。第３図において、点検入力
ＡＣ２００Ｖを点検電源トランスθυを介して母線保護
リレー用入力装置（３）内の抑制回路点検巻線（６ｈ）
、（６Ｂ）、（６ｃ）に印加し、点検判定要素（９）が
動作することを確認すれば入力装置（３）の２次回路（
ｓＡ）、（ｓＢ）、（ｅｃ）、（ｓＤ）のいずれかが断
線すれば点検判定要素（９）は入力電圧が欠けるので動
作せず、点検不良とな漫、異常を検出することが可能で
ある。Next, the operation will be explained. In Fig. 3, the inspection input AC200V is connected to the suppression circuit inspection winding (6h) in the bus protection relay input device (3) via the inspection power transformer θυ.
, (6B), and (6c) and confirm that the inspection judgment element (9) operates, the secondary circuit of the input device (3) (
If any one of sA), (sB), (ec), and (sD) is disconnected, the inspection judgment element (9) will not operate due to lack of input voltage, and it is possible to detect an inspection failure, delay, or abnormality. It is.
また、入力装置回路の点検は、従来から点検電源トラン
スＱυよｐ入力全印加Ｌ 、点検判定要素（９）が動作
、不動作で点検判定′良″、″否″ヲ決定している０
そして、点検判定要素（９）はある一定レベル値以上あ
れは動作するので、入力電圧が不足になる異常、例えは
抑制回路点検巻線（６＊）、（ａＢ）、（ａｃ）、抑制
トランス２次巻線（ツＡ）、（’７Ｂ）ｊ（’７Ｃ）の
断線、短絡、抑制回路リード線（８Ａ）、（ｎＢ）、（
ｓｃ）、（ｓＤ）の断線、短絡は検出することが可能で
ある。しかし入力電圧が過大となる異常、例えば入力装
置内部の半導体部品の劣化、過大入力電圧の印加などに
より一定レベル値以上の電圧が発生しても、現在の点検
判定方式だと検出することが不可能である。In addition, conventionally, when inspecting the input device circuit, the inspection judgment is determined as ``pass'' or ``fail'' based on the inspection power transformer Qυ, p input full application L, and inspection judgment element (9) operating or not operating. , the inspection judgment element (9) operates if it exceeds a certain level value, so there is an abnormality where the input voltage is insufficient, for example, the suppression circuit inspection windings (6*), (aB), (ac), suppression transformer 2 Next winding (tsu A), ('7B) j ('7C) disconnection, short circuit, suppression circuit lead wire (8A), (nB), (
It is possible to detect disconnections and short circuits in sc) and (sD). However, even if a voltage exceeding a certain level occurs due to an abnormality in which the input voltage is excessive, such as deterioration of semiconductor components inside the input device or application of excessive input voltage, the current inspection and judgment method cannot detect it. It is possible.
従来の母線保護装置の点検回路は以上のように、点検判
定要素に印加される各入力電圧がある一定レベル値以上
あれば、点検判定要素（９）が１異常なし」と判定する
ので、過大電圧が印加されていても現在の点検回路では
見つけることが出来ない欠点があった。As described above, the inspection circuit of the conventional bus protection device judges that if each input voltage applied to the inspection judgment element is above a certain level value, the inspection judgment element (9) is ``No abnormality''. Even if voltage was applied, there was a defect that could not be found with current inspection circuits.
この発明は上記のような従来のものの欠点を除去するた
めになされたもので、入力装置の出力が異常に小さい場
合のみでなく、異常に大きい場合にも検出できるように
点検能力を向上させることを目的とするものである。This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it is an object of the present invention to improve the inspection ability so that it can detect not only when the output of the input device is abnormally small but also when it is abnormally large. The purpose is to
この発明に係る保護装置の点検回路は、基準入力と入力
装置からの入力とをそれぞれトランスに通して上記基準
入力と上記入力装置からの入力とがキャンセルされる回
路構成として上記基準入力と上記入力装置からの入力と
を比較演算して点検判定するようにしたものである。The inspection circuit for a protection device according to the present invention has a circuit configuration in which the reference input and the input from the input device are canceled by passing the reference input and the input from the input device through transformers, respectively. The inspection is determined by comparing and calculating the input from the device.
この発明における保護装置の点検回路においては、基準
入力と入力装置からの入力とをそれぞれトランスに通し
て上記基準入力と上記入力装置からの入力とがキャンセ
ルでれる回路構成としたので、上記入力装置からの入力
が異常に小さい場合のみでなく、異常に大きい場合も検
出でき、従って例えば入力装置内での断線のみでなく、
例えば入力装置内の半導体の劣化による電圧上昇等も検
出できる。In the inspection circuit for the protection device according to the present invention, the reference input and the input from the input device are each passed through a transformer so that the reference input and the input from the input device can be cancelled. It is possible to detect not only when the input from the input device is abnormally small but also when it is abnormally large.
For example, voltage increases due to deterioration of semiconductors within the input device can also be detected.
以下この発明の一実施例を図において説明する。 An embodiment of the present invention will be described below with reference to the drawings.
Ｍ１図において、ｆｆ＞は基準入力電圧、（■Ａ）、（
ｖｍ）。In diagram M1, ff> is the reference input voltage, (■A), (
vm).
（Ｖｃ）は演算入力電圧、（１４Ａ）、（１４Ｂ）、（
１４ｃ）は演算入カドランス、（１，３Ａ） 、 （１
３Ｂ） 、 （１３Ｇ）は基準入カドランス、０５Ａ）
、０５ｎ）、（１５ｃ）は全波整流回路、０・は点検判
定回路である。(Vc) is the calculation input voltage, (14A), (14B), (
14c) is an arithmetic input quadrance, (1,3A), (1
3B), (13G) is standard input quadrence, 05A)
, 05n) and (15c) are full-wave rectifier circuits, and 0. is an inspection judgment circuit.
第１図会体は点検判定要素の内部回路図である。FIG. 1 is an internal circuit diagram of the inspection judgment element.
第２図において、（６Ａ）、（６Ｂ）、（６Ｃ）は差動
回路点検巻線、（７Ａ）、（ＶＢ）、（’７ｃ）は差動
トランス２次巻線、（８Ａ）＋（８Ｂ）＋（８ｃ）は抑
制回路リード線、（１２Ａ）は点検電源トランス０υの
２次巻線、（１２Ｂ）は基準入力電圧を発生させる点検
電源トランスの３次巻線、ａ陣はこの点検電源トランス
（１◇の３次巻線（１２１３）により発生する基準入力
電圧、０ルは点検電源トランスぐυの２次巻線（コ２Ａ
）により入力装置（３）全通して発生する演算入力電圧
である。In Figure 2, (6A), (6B), (6C) are differential circuit inspection windings, (7A), (VB), ('7c) are differential transformer secondary windings, (8A) + ( 8B) + (8c) is the suppression circuit lead wire, (12A) is the secondary winding of the inspection power transformer 0υ, (12B) is the tertiary winding of the inspection power transformer that generates the reference input voltage, group a is this inspection The reference input voltage generated by the tertiary winding (1213) of the power transformer (1◇), 0 is the secondary winding (1213) of the power transformer (1◇) for inspection.
) is the calculation input voltage generated throughout the input device (3).
他は第３図と同じである。Others are the same as in Figure 3.
第２図において、点検時のみ点検電源トランスαυよυ
λ入力装置３）全通して入力される演算入力は第３図の
場合と同様の回路図である。In Fig. 2, the power supply transformer αυ and υ are inspected only during inspection.
λ Input Device 3) The arithmetic inputs input throughout are the same circuit diagram as in FIG.
従来回路（第３図）では検出できなかった点検入力要素
に印加される電圧が一定レベル値を越える過大電圧値で
も、点検電源トランスθυよシ印加される基準入力値と
比較演算（基準入力値−演算入力値）シ、その値がある
規定値（誤差裕度値）以下であることで点検判定ゝ１良
“と判定することが可能である。Even if the voltage applied to the inspection input element exceeds a certain level value, which could not be detected by the conventional circuit (Fig. 3), a comparison operation (reference input value - Calculation input value) If the value is less than a certain specified value (error margin value), it is possible to determine that the inspection judgment is "1 good".
例えば、Ｋ３図に示す従来の点検回路では、点検判定要
素の検出値が１０ｖとすると点検入力演算値がＩＯＶ以
上で点検判定ゝゝ良“とし、１０ｖ以下で点検判定ゝゝ
否″となるので過大電圧ｃ数百ボルト）でも点検判定ゝ
ゝ良“となっていたが、今回発明した点検判定要素（第
１図）を使った一実施例による点検回路図（第２図）に
より、規定値（誤差裕度値）を土２ｖと決めると基準入
力値Ｑ１１ｏ’Ｖに対して、点挟入力演算値（１４１が
１２Ｖ以下で点検判定ゝゝ良″となり、１３Ｖになると
点検判定ゝゞ否″となり精度点検が可能となる。また、
点検入力演算値が８ｖ以上で点検判定ゝゝ良“となり、
７ｖになると（微小電圧）点検判定ゝゞ否″となυ精度
点検が可能となる。For example, in the conventional inspection circuit shown in diagram K3, if the detected value of the inspection judgment element is 10V, the inspection judgment is "Good" when the inspection input calculation value is greater than or equal to IOV, and the inspection judgment is "Fail" when it is less than 10V. Even with an overvoltage (c) of several hundred volts, the inspection judgment was "Good", but according to the inspection circuit diagram (Fig. 2) according to an example using the inspection judgment element (Fig. 1) invented this time, the specified value If the (error margin value) is determined to be 2V, the input calculation value (141) is 12V or less, the inspection judgment is "Good", and when it is 13V, the inspection judgment is "Fail". This makes it possible to check the accuracy.Also,
When the inspection input calculation value is 8V or more, the inspection judgment is "Good".
When the voltage reaches 7V (microvoltage), it becomes possible to check the accuracy of υ, which makes the inspection judgment "yes or no".
第１図は今回発明回路の点検判定要素（９）の内部回路
図である。基準入力電圧（Ｖ）と演算入力電圧（ｖム）
、（Ｖｎ）、（Ｖｃ） ｋ基準入カドランス（１３Ａ）
、（１３Ｂ）。FIG. 1 is an internal circuit diagram of the inspection determination element (9) of the circuit of the present invention. Reference input voltage (V) and calculation input voltage (vm)
, (Vn), (Vc) k standard input quadrence (13A)
, (13B).
（’１３Ｃ）と演算式カドランス（１４Ａ）、（１４Ｂ
）、（コ４Ｃ）とを通して突き合わせキャンセルするよ
うな回路構成としている。よって、判定回路ＯＱの規定
値を±２ｖと設定しておくと、基準入力値（Ｖ）ＩＯＶ
Ｋ対して、点検演算入力値（Ｖｈ）、（ＶＢ）、（ＶＣ
）が１２Ｖ以下又は８ｖ以上で点検判定ゝゞ良″とな９
．１３Ｖ、’／Ｖと点検演算入力値が変化すると点検判
定ゝゝ否″となシ精度点検が可能となるのである。('13C) and calculation formula quadrance (14A), (14B
) and (4C), the circuit configuration is such that matching and cancellation are performed. Therefore, if the specified value of the judgment circuit OQ is set to ±2V, the reference input value (V) IOV
For K, check calculation input values (Vh), (VB), (VC
) is 12V or less or 8V or more, the inspection judgment is "Good" 9
．． When the inspection calculation input value changes to 13V, '/V, the inspection judgment becomes "Yes or No", and the accuracy inspection becomes possible.
また、上記実施例では母線保護装置の入力装置２次回路
の点検判定要素について説明したが、他のリレー装置（
例えば変圧器保護装置、搬送保護装置、発電機保護装置
、表示線保護装置能）で点検判定要素（第１図）を設置
して点検しようとする回路（被点検回路）がある点検判
定回路であってもよく、上記実施例と同様の効果を奏す
る。In addition, although the above embodiment has explained the inspection determination elements of the input device secondary circuit of the busbar protection device, other relay devices (
For example, in an inspection judgment circuit where there is a circuit to be inspected (circuit to be inspected) by installing an inspection judgment element (Fig. The same effect as in the above embodiment can be achieved.
以上のようにこの発明によれば、基準入力と入力装置か
らの入力とをそれぞれトランスに通して上記基準入力と
上記入力装置からの入力と全それぞれトランスに通して
上記基準入力と上記入力装置からの入力とがキャンセル
される回路構成にして上記基準入力と上記入力装置から
の入力とを比較演算して点検判定するようにしたので、
トランスと点検判定回路を設けるだけで、上記入力装置
の出力が異常に小さい場合のみでなく、異常に大きい場
合も確実に検出出来、従って例えば断線のみでなく入力
装置内の半導体の劣化による電圧上昇、過大入力電圧の
印加等をも検出できるという効果がある。As described above, according to the present invention, the reference input and the input from the input device are passed through the transformers, and the reference input and the input from the input device are passed through the transformers, respectively, and the reference input and the input from the input device are passed through the transformers. The circuit is configured such that the input from the input device is canceled, and the inspection judgment is made by comparing the reference input and the input from the input device.
By simply installing a transformer and an inspection judgment circuit, it is possible to reliably detect not only cases where the output of the input device is abnormally small, but also cases where it is abnormally large. Therefore, for example, it is possible to detect not only a disconnection but also a voltage increase due to deterioration of the semiconductor inside the input device. , the application of excessive input voltage, etc. can also be detected.
第１図はこの発明の一実施例の要部つまり点検判定要素
の内部回路を示す接続図、第２図はこの発明の一実施例
を示す接続図で、第１図の点検判定要素を使った例を示
しである。第３図は従来の母線保護装置の点検回路図で
ある。
なお、各図中同一符号は同一または相当する部分を示す
。Fig. 1 is a connection diagram showing the main part of an embodiment of the present invention, that is, the internal circuit of the inspection judgment element, and Fig. 2 is a connection diagram showing an embodiment of the invention, in which the inspection judgment element of Fig. 1 is used. Here is an example. FIG. 3 is an inspection circuit diagram of a conventional bus bar protection device. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
の出力電流により付勢される保護リレー、点検時に上記
入力装置へ給電する点検電源トランス、及び上記入力装
置の出力側に接続され基準入力値と上記入力装置からの
入力値とを比較演算し上記入力装置の異常を検出する点
検判定要素を備えているものにおいて、上記基準入力と
上記入力装置からの入力とをそれぞれトランスに通して
上記基準入力と上記入力装置からの入力とがキャンセル
される回路構成にして、上記基準入力と上記入力装置か
らの入力とを比較演算して点検判定することを特徴とす
る保護装置の点検回路。An input device that transforms each phase current of the power system, a protection relay energized by the output current of this input device, an inspection power transformer that supplies power to the input device during inspection, and a reference input connected to the output side of the input device. In the apparatus, the reference input and the input from the input device are respectively passed through a transformer, and the reference input and the input from the input device are passed through a transformer. 1. An inspection circuit for a protective device, characterized in that the circuit has a circuit configuration in which a reference input and an input from the input device are canceled, and an inspection judgment is made by comparing the reference input and the input from the input device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60209349A JP2608701B2 (en) | 1985-09-19 | 1985-09-19 | Inspection circuit for protective device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60209349A JP2608701B2 (en) | 1985-09-19 | 1985-09-19 | Inspection circuit for protective device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6268015A true JPS6268015A (en) | 1987-03-27 |
| JP2608701B2 JP2608701B2 (en) | 1997-05-14 |
Family
ID=16571477
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60209349A Expired - Lifetime JP2608701B2 (en) | 1985-09-19 | 1985-09-19 | Inspection circuit for protective device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2608701B2 (en) |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7531894B2 (en) | 1994-12-29 | 2009-05-12 | Tessera, Inc. | Method of electrically connecting a microelectronic component |
| US7816251B2 (en) | 2003-10-06 | 2010-10-19 | Tessera, Inc. | Formation of circuitry with modification of feature height |
| US7939934B2 (en) | 2005-03-16 | 2011-05-10 | Tessera, Inc. | Microelectronic packages and methods therefor |
| US8058101B2 (en) | 2005-12-23 | 2011-11-15 | Tessera, Inc. | Microelectronic packages and methods therefor |
| US8067267B2 (en) | 2005-12-23 | 2011-11-29 | Tessera, Inc. | Microelectronic assemblies having very fine pitch stacking |
| US8207604B2 (en) | 2003-12-30 | 2012-06-26 | Tessera, Inc. | Microelectronic package comprising offset conductive posts on compliant layer |
| US8836136B2 (en) | 2011-10-17 | 2014-09-16 | Invensas Corporation | Package-on-package assembly with wire bond vias |
| US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
| US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
| US8907466B2 (en) | 2010-07-19 | 2014-12-09 | Tessera, Inc. | Stackable molded microelectronic packages |
| US8927337B2 (en) | 2004-11-03 | 2015-01-06 | Tessera, Inc. | Stacked packaging improvements |
| US8975738B2 (en) | 2012-11-12 | 2015-03-10 | Invensas Corporation | Structure for microelectronic packaging with terminals on dielectric mass |
| US9030001B2 (en) | 2010-07-27 | 2015-05-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
| US9093435B2 (en) | 2011-05-03 | 2015-07-28 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
| US9137903B2 (en) | 2010-12-21 | 2015-09-15 | Tessera, Inc. | Semiconductor chip assembly and method for making same |
| US9159708B2 (en) | 2010-07-19 | 2015-10-13 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
| US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
| US11710718B2 (en) | 2015-07-10 | 2023-07-25 | Adeia Semiconductor Technologies Llc | Structures and methods for low temperature bonding using nanoparticles |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5725119A (en) * | 1980-07-18 | 1982-02-09 | Meidensha Electric Mfg Co Ltd | Device for inspecting and monitoring protection relay |
-
1985
- 1985-09-19 JP JP60209349A patent/JP2608701B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5725119A (en) * | 1980-07-18 | 1982-02-09 | Meidensha Electric Mfg Co Ltd | Device for inspecting and monitoring protection relay |
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7531894B2 (en) | 1994-12-29 | 2009-05-12 | Tessera, Inc. | Method of electrically connecting a microelectronic component |
| US7816251B2 (en) | 2003-10-06 | 2010-10-19 | Tessera, Inc. | Formation of circuitry with modification of feature height |
| US8207604B2 (en) | 2003-12-30 | 2012-06-26 | Tessera, Inc. | Microelectronic package comprising offset conductive posts on compliant layer |
| US8927337B2 (en) | 2004-11-03 | 2015-01-06 | Tessera, Inc. | Stacked packaging improvements |
| US7939934B2 (en) | 2005-03-16 | 2011-05-10 | Tessera, Inc. | Microelectronic packages and methods therefor |
| US8058101B2 (en) | 2005-12-23 | 2011-11-15 | Tessera, Inc. | Microelectronic packages and methods therefor |
| US8067267B2 (en) | 2005-12-23 | 2011-11-29 | Tessera, Inc. | Microelectronic assemblies having very fine pitch stacking |
| US9159708B2 (en) | 2010-07-19 | 2015-10-13 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
| US8907466B2 (en) | 2010-07-19 | 2014-12-09 | Tessera, Inc. | Stackable molded microelectronic packages |
| US9030001B2 (en) | 2010-07-27 | 2015-05-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
| US9716075B2 (en) | 2010-12-21 | 2017-07-25 | Tessera, Inc. | Semiconductor chip assembly and method for making same |
| US9137903B2 (en) | 2010-12-21 | 2015-09-15 | Tessera, Inc. | Semiconductor chip assembly and method for making same |
| US9093435B2 (en) | 2011-05-03 | 2015-07-28 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
| US8836136B2 (en) | 2011-10-17 | 2014-09-16 | Invensas Corporation | Package-on-package assembly with wire bond vias |
| US9041227B2 (en) | 2011-10-17 | 2015-05-26 | Invensas Corporation | Package-on-package assembly with wire bond vias |
| US9105483B2 (en) | 2011-10-17 | 2015-08-11 | Invensas Corporation | Package-on-package assembly with wire bond vias |
| US9252122B2 (en) | 2011-10-17 | 2016-02-02 | Invensas Corporation | Package-on-package assembly with wire bond vias |
| US11735563B2 (en) | 2011-10-17 | 2023-08-22 | Invensas Llc | Package-on-package assembly with wire bond vias |
| US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
| US9953914B2 (en) | 2012-05-22 | 2018-04-24 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
| US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
| US8975738B2 (en) | 2012-11-12 | 2015-03-10 | Invensas Corporation | Structure for microelectronic packaging with terminals on dielectric mass |
| US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
| US11710718B2 (en) | 2015-07-10 | 2023-07-25 | Adeia Semiconductor Technologies Llc | Structures and methods for low temperature bonding using nanoparticles |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2608701B2 (en) | 1997-05-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6268015A (en) | Inspecting circuit for protecting device | |
| US3184644A (en) | Polyphase electroresponsive apparatus | |
| GB1599935A (en) | Circuit arrangement for detecting earth faults | |
| JPS61210820A (en) | Inspection circuit for protector | |
| JPS59226614A (en) | Power source for stationary protecting relay | |
| JPH0210655B2 (en) | ||
| JPS608518Y2 (en) | Display line protection relay device | |
| JPS61142922A (en) | Disconnection detector/relay | |
| JPS6212328A (en) | Inspection system for ratio differential relay | |
| JPS6353793B2 (en) | ||
| JPS6135112A (en) | Automatic inspecting device | |
| JPS60180434A (en) | Transformer protection relaying device | |
| JPS6117215B2 (en) | ||
| JPS5814137B2 (en) | Busbar selection relay device | |
| JPS61227630A (en) | Protective relay | |
| JPS6115520A (en) | 2-wire defect protecting relay | |
| JPS6084918A (en) | Display wire relaying device | |
| JPS60160328A (en) | Dc ground-fault detector | |
| JPS61109218A (en) | Trip circuit for breaker | |
| JPS6295923A (en) | Protective relay of transformer | |
| JPS602016A (en) | Protecting system of dc transmission line | |
| JPH01286724A (en) | Overcurrent relay | |
| JPH023371B2 (en) | ||
| JPS6343968B2 (en) | ||
| JPS63114525A (en) | Current differential relay |