JPS6266435U - - Google Patents

Info

Publication number
JPS6266435U
JPS6266435U JP15763885U JP15763885U JPS6266435U JP S6266435 U JPS6266435 U JP S6266435U JP 15763885 U JP15763885 U JP 15763885U JP 15763885 U JP15763885 U JP 15763885U JP S6266435 U JPS6266435 U JP S6266435U
Authority
JP
Japan
Prior art keywords
circuit
receiving
radio
bandwidth
clock circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15763885U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15763885U priority Critical patent/JPS6266435U/ja
Publication of JPS6266435U publication Critical patent/JPS6266435U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Noise Elimination (AREA)
  • Circuits Of Receivers In General (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例のブロツク図、第2
図は制御回路13の具体的な構成を示す電気回路
図、第3図は制御回路13Aの具体的な構成を示
す電気回路図である。 1……アンテナ、2……同調回路、3……混合
回路、4……局部発信回路、5……中間周波増幅
回路、6……検波回路、7……増幅回路、8……
スピーカ、9……処理回路、10……時計回路、
11……表示回路、13,13A……制御回路。
Figure 1 is a block diagram of one embodiment of the present invention;
The figure is an electric circuit diagram showing a specific configuration of the control circuit 13, and FIG. 3 is an electric circuit diagram showing a specific configuration of the control circuit 13A. 1... Antenna, 2... Tuning circuit, 3... Mixing circuit, 4... Local oscillation circuit, 5... Intermediate frequency amplification circuit, 6... Detection circuit, 7... Amplification circuit, 8...
Speaker, 9...processing circuit, 10...clock circuit,
11... Display circuit, 13, 13A... Control circuit.

Claims (1)

【実用新案登録請求の範囲】 受信帯域幅を広狭可変に調整可能なラジオ受信
回路と、 時計回路と、 時計回路からの出力に応答し、ラジオ受信回路
の受信帯域幅を昼間には広くし、夜間には狭く設
定する回路とを含むことを特徴とするラジオ受信
機。
[Claim for Utility Model Registration] A radio receiving circuit capable of widening and narrowing the receiving bandwidth, a clock circuit, and a radio receiving circuit whose receiving bandwidth is widened during the daytime in response to the output from the clock circuit. A radio receiver characterized in that it includes a circuit that is set narrowly at night.
JP15763885U 1985-10-14 1985-10-14 Pending JPS6266435U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15763885U JPS6266435U (en) 1985-10-14 1985-10-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15763885U JPS6266435U (en) 1985-10-14 1985-10-14

Publications (1)

Publication Number Publication Date
JPS6266435U true JPS6266435U (en) 1987-04-24

Family

ID=31080373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15763885U Pending JPS6266435U (en) 1985-10-14 1985-10-14

Country Status (1)

Country Link
JP (1) JPS6266435U (en)

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