JPS6261973B2 - - Google Patents
Info
- Publication number
- JPS6261973B2 JPS6261973B2 JP56014325A JP1432581A JPS6261973B2 JP S6261973 B2 JPS6261973 B2 JP S6261973B2 JP 56014325 A JP56014325 A JP 56014325A JP 1432581 A JP1432581 A JP 1432581A JP S6261973 B2 JPS6261973 B2 JP S6261973B2
- Authority
- JP
- Japan
- Prior art keywords
- latch
- circuit
- input
- combinational circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012360 testing method Methods 0.000 description 7
- 238000003745 diagnosis Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318577—AC testing, e.g. current testing, burn-in
- G01R31/31858—Delay testing
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
【発明の詳細な説明】 本発明は大規模な論理用集積回路に関する。[Detailed description of the invention] The present invention relates to large scale logic integrated circuits.
大規模な論理用集積回路では、入力段ラツチ
群、組合わせ論理回路および出力段論理回路の構
成になつている。そして診断及び保守を容易にす
る目的で、各ラツチには、通常使用するデータ入
力、タイミング入力の他にスキヤンイン入力を有
し、スキヤンインアドレスの指すラツチに対し、
スキヤンイン入力から“1”又は“0”の値を入
れる事ができるような構成をとるのが通常であ
る。テスト方法としては、ラツチ1ビツトずつに
値をシリアルに入れて行き、組合わせ回路を通し
た後に、出力段ラツチにタイミングパルスを入
れ、組合せ回路の出力を出力ラツチに取り込み、
出力ラツチにスキヤンアウトアドレスを与えて1
ビツトずつスキヤンアウトデータを読む方法で診
断する。 Large scale logic integrated circuits consist of input stage latches, combinational logic circuits and output stage logic circuits. In order to facilitate diagnosis and maintenance, each latch has a scan-in input in addition to the normally used data input and timing input.
Usually, the configuration is such that a value of "1" or "0" can be input from the scan-in input. The test method is to input the value into the latch serially one bit at a time, pass it through the combinational circuit, then apply a timing pulse to the output stage latch, capture the output of the combinational circuit into the output latch,
Give the scanout address to the output latch 1
Diagnosis is performed by reading scanout data bit by bit.
前記の様な従来技術では、組合わせ回路の直流
的な特性しか診断できないと言う欠点がある。即
ち、入力段ラツチ1ビツトずつに対して値を入れ
て行くために、スキヤンイン動作の終了したラツ
チの出力の影響は、レベル的な信号として組合わ
せ回路を通過してしまい、パルス的な影響を調べ
ようとした場合には、入力ラツチの最後の1ビツ
トの変化が組合わせ回路を通過する時間が出力ラ
ツチのラツチ時間に間に合うか否かのテストしか
できないと言う問題点である。 The above-mentioned conventional techniques have the disadvantage that only the direct current characteristics of the combinational circuit can be diagnosed. That is, since values are input to each input stage latch bit by bit, the influence of the output of the latch after the scan-in operation is passed through the combinational circuit as a level signal, and the pulse influence is lost. If you try to investigate this, the problem is that you can only test whether the time it takes for the last 1-bit change in the input latch to pass through the combinational circuit is in time for the latch time of the output latch.
本発明の目的は前記の問題点を解決し、遅延時
間を検査することができる集積回路を提供するこ
とにある。 SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide an integrated circuit capable of testing delay time.
本発明は同一タイミングで動作する入力ラツチ
の出力に排他的論理和回路を設け、診断時には入
力ラツチに本来のテストパターンと逆転したテス
トパターンを書き込み、全ビツトパターン書き込
み後、排他的論理和の他入力を同時に切り換えて
正規のテストパターンを組合わせ回路に入れてや
り、データ切り換わり時点から、出力ラツチの取
り込みまでの時間内に、テストパターンが組み合
わせ回路を通過できたか否かを判定できるように
する点にある。 The present invention provides an exclusive OR circuit at the output of input latches that operate at the same timing, writes a test pattern reversed from the original test pattern to the input latch during diagnosis, and after writing all bit patterns, performs an exclusive OR circuit. By switching the inputs at the same time and inputting a regular test pattern into the combinational circuit, it is possible to determine whether the test pattern has passed through the combinational circuit within the time from the data switch to the capture of the output latch. It is in the point of doing.
第1図に従来の論理集積回路のブロツク図を示
す。図において1および4は組合わせ回路であ
り、組合わせ回路1の出力はラツチタイミング入
力8,9でラツチ群にラツチされ、組合わせ回路
4に入力される。組合わせ回路4の出力はラツチ
タイミング入力10で出力ラツチ群5にラツチさ
れる。スキヤンアドレス11とスキヤンインデー
タにはスキヤンデコーダ6に入力される。スキヤ
ンアドレス11の指定するラツチ2あるいは3に
スキヤンインデータ12を書き込んで行き、出力
ラツチ群5にラツチタイミング10のタイミング
でデータを取り込み、スキヤンアウトセレクタ7
より出力し、組合わせ回路4部分の診断を行う。
このため入力ラツチ群は1ビツトずつ値が確定し
てしまい、組合わせ回路4部分を通過する遅延時
間の検査は十分に行う事はできない。 FIG. 1 shows a block diagram of a conventional logic integrated circuit. In the figure, 1 and 4 are combinational circuits, and the output of combinational circuit 1 is latched into a group of latches at latch timing inputs 8 and 9, and input to combinational circuit 4. The output of combinational circuit 4 is latched into output latch group 5 at latch timing input 10. The scan address 11 and scan-in data are input to the scan decoder 6. The scan-in data 12 is written to the latch 2 or 3 specified by the scan address 11, the data is taken into the output latch group 5 at the latch timing 10, and the scan-out selector 7
and diagnose the four parts of the combinational circuit.
For this reason, the values of the input latch group are determined bit by bit, and the delay time passing through the combinational circuit 4 cannot be sufficiently inspected.
第2図は本発明の一実施例を示し、第1図の従
来回路に排他的論理和回路13群を被診断部4の
入力部に入れたものである。通常動作時には、組
合わせ回路1を通つた信号をラツチタイミング8
により、ラツチ群2に取り込み、ラツチタイミン
グ9によりラツチ群3に取り込む。両者は組合わ
せ回路4を通り、ラツチ群5にラツチタイミング
10により取り込まれる。 FIG. 2 shows an embodiment of the present invention, in which a group of 13 exclusive OR circuits is added to the conventional circuit shown in FIG. 1 at the input section of the section 4 to be diagnosed. During normal operation, the signal passing through combinational circuit 1 is held at latch timing 8.
At latch timing 9, the signal is taken into latch group 2, and at latch timing 9, it is taken into latch group 3. Both pass through the combinational circuit 4 and are taken into the latch group 5 at the latch timing 10.
組合わせ回路4の診断は、スキヤンアドレス1
1及びスキヤンインデータ12より、ラツチ群
2,3に本来のテストパターンの反転したものを
順に書き込む。そしてラツチタイミング8の代わ
りに、診断端子14をラツチタイミング9の代わ
りに診断端子15よりパルスを入れ、組合わせ回
路4を通過させ、ラツチタイミングによりラツチ
群5に取り込めば、組合わせ回路4部分の時間検
査が可能となる。 For diagnosis of combinational circuit 4, scan address 1
1 and scan-in data 12, inverted versions of the original test patterns are sequentially written into latch groups 2 and 3. Then, if a pulse is input from the diagnostic terminal 15 instead of the latch timing 8 and the diagnostic terminal 14 instead of the latch timing 9, it passes through the combinational circuit 4, and is taken into the latch group 5 according to the latch timing. Time inspection becomes possible.
このように、スキヤンイン診断を使用しなが
ら、組合わせ回路部分の遅延時間をタイミングパ
ルスの時間間隔で検査することができる。 In this way, using scan-in diagnostics, the delay time of the combinational circuit portion can be tested in time intervals of timing pulses.
第1図は従来例を示すブロツク図、第2図は本
発明の一実施例を示すブロツク図である。
2,3,5……ラツチ群、4……組合わせ回
路、13……排他的論理和回路。
FIG. 1 is a block diagram showing a conventional example, and FIG. 2 is a block diagram showing an embodiment of the present invention. 2, 3, 5... Latch group, 4... Combinational circuit, 13... Exclusive OR circuit.
Claims (1)
ツチを含み、該ラツチに対して外部より任意の値
を入れられる構成の集積回路において、該ラツチ
出力を排他的論理和回路を介して組合わせ回路に
入力するようにし、上記ラツチに任意の値を入れ
た後、上記排他的論理和回路の他入力を切換えて
上記ラツチの値を排他的論理和回路を通して組合
わせ回路に与えることを特徴とする集積回路。1. In an integrated circuit that includes a combinational circuit and a latch connected to its input, and has a configuration in which any value can be entered into the latch from the outside, the output of the latch is sent to the combinational circuit via an exclusive OR circuit. After inputting an arbitrary value into the latch, the other inputs of the exclusive OR circuit are switched and the value of the latch is applied to the combinational circuit through the exclusive OR circuit. circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56014325A JPS57130156A (en) | 1981-02-04 | 1981-02-04 | Integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56014325A JPS57130156A (en) | 1981-02-04 | 1981-02-04 | Integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57130156A JPS57130156A (en) | 1982-08-12 |
JPS6261973B2 true JPS6261973B2 (en) | 1987-12-24 |
Family
ID=11857915
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56014325A Granted JPS57130156A (en) | 1981-02-04 | 1981-02-04 | Integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57130156A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0444856Y2 (en) * | 1986-10-22 | 1992-10-22 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0769394B2 (en) * | 1987-05-12 | 1995-07-31 | 日本電気株式会社 | Logic circuit tester |
-
1981
- 1981-02-04 JP JP56014325A patent/JPS57130156A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0444856Y2 (en) * | 1986-10-22 | 1992-10-22 |
Also Published As
Publication number | Publication date |
---|---|
JPS57130156A (en) | 1982-08-12 |
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