JPS6258649A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6258649A JPS6258649A JP19911885A JP19911885A JPS6258649A JP S6258649 A JPS6258649 A JP S6258649A JP 19911885 A JP19911885 A JP 19911885A JP 19911885 A JP19911885 A JP 19911885A JP S6258649 A JPS6258649 A JP S6258649A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- bump electrodes
- substrate
- solder
- bump electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
本発明は、半導体チップに設けられたバンプ電極が対向
する絶縁基板上に備えられた導体に融着させるフリップ
チップ方式で実装される半導体装置に関する。The present invention relates to a semiconductor device that is mounted using a flip-chip method in which bump electrodes provided on a semiconductor chip are fused to conductors provided on an opposing insulating substrate.
半導体集積回路（Ｉ Ｃ）のコンパクトな実装を実現す
るために、従来のチップ上の電極をリード線とワイヤボ
ンディングで１ｍするＩ）ＩＬパッケージから、ボリミ
イドフィルム上の銅またはすず箔導体とＩＣチップのバ
ンプ電極とを接続してパフケージに封入するＰＬＣＣ（
プラスチック・リーデツド・チップ・キャリヤ）方式に
、さらにパフケージに封入しないで裸のチップ（ベアチ
ップ）を実装する方向へ進んでいる。このようなベアチ
ップの実装には通常フリップチップ方式が採用される。
フ’Ｊ ツブチップ方式は従来比較的小面積のチップに
通用されていたが、ＩＣの技術的進歩に伴って５０−１
を越える大きさのチップにもフリップチップ方式を採用
する要求が生じている。このような大面積チップにおい
てはバンプ電極の数も増加するのが通例である。しかし
このバンプ篭手ｔを第２図のように半導体チップｌの周
辺に配置すると、バンブ電極２の間の距Ｎ１が長くなり
、第３図に示すように絶縁基板３の上の導体層４に融着
した場合、基板３の材料とチップ１の半導体との熱膨張
係数の差によりバンブ電極２に応力が加わり、このＩＣ
，にヒートサイクルが加わると電極接続不良などが生じ
る戊がある。
この問題の解決のためにバンブ電極２をチップ周辺に配
置しないで中央部に配置することが既に知られている。
しかしその場合、半導体チップが基板に中央部で支持さ
れるため、支持の安定性が悪く、バンプ？ｌｔ極にｉ械
的応力が加わり、やはり信頼性の低下を招く。In order to realize compact packaging of semiconductor integrated circuits (ICs), the conventional IL package, in which the electrodes on the chip are connected to 1m lead wires and wire bonding, has been replaced with a copper or tin foil conductor on a volimide film. PLCC (
In addition to the plastic leaded chip carrier (plastic leaded chip carrier) method, progress is being made toward mounting bare chips without encapsulating them in a puff cage. A flip-chip method is usually adopted for mounting such bare chips. The Fu'J Tsubu chip method had previously been used for chips with a relatively small area, but with the technological advancement of ICs, the 50-1
There is also a demand for the flip-chip method to be used for chips larger than 200 yen. In such a large-area chip, the number of bump electrodes usually increases. However, if this bump gauntlet t is arranged around the semiconductor chip l as shown in FIG. 2, the distance N1 between the bump electrodes 2 becomes longer, and as shown in FIG. When fused, stress is applied to the bump electrode 2 due to the difference in thermal expansion coefficient between the material of the substrate 3 and the semiconductor of the chip 1, and this IC
, when heat cycles are applied to the electrodes, electrode connection failures may occur. In order to solve this problem, it is already known to arrange the bump electrode 2 not around the chip but in the center. However, in that case, the semiconductor chip is supported at the center of the substrate, which results in poor support stability and bumps. Mechanical stress is added to the lt pole, which also leads to a decrease in reliability.
本発明は、半導体チップの中央部に設けられたバンブ電
極が対向する絶縁基板上の導体に融着される場合に、半
導体チップが基板に安定して支持され、バンブ電極に応
力が加わらないため信軌性の高い半導体装置を堤供する
ことを目的とする。In the present invention, when a bump electrode provided at the center of a semiconductor chip is fused to a conductor on an opposing insulating substrate, the semiconductor chip is stably supported by the substrate and no stress is applied to the bump electrode. The purpose is to provide semiconductor devices with high reliability.
本発明によれば、半導体層ノブの重心を通るチップ面内
の線の両側に存在する３個所以上の周辺部位とそれに対
向する絶＆！基板上の部位の少なくとも一方に突起を有
し、その突起が対向する面に係合してチップ基板間の間
隔を所定に保つことにより、チップが周辺で基板に支持
され、安定した支持が得られて上記の目的を達成する。
上述の突起を対向する基板面に当設させた場合に、半導
体チップに設けられたはんだよりなるバンブ電極が融着
前において対向する導体面との間に空隙を有することは
、融着後のバンブ電極が鼓状となることによってヒート
サイクルに対しより耐久性をもつので有効である。According to the present invention, there are three or more peripheral portions on both sides of a line in the chip surface passing through the center of gravity of the semiconductor layer knob, and an opposing absolute &! By having a protrusion on at least one of the parts on the substrate, and by engaging the protrusion with the opposing surface to maintain a predetermined distance between the chip substrates, the chip is supported by the substrate around the periphery, providing stable support. to achieve the above objectives. When the above-mentioned protrusions are placed in contact with opposing substrate surfaces, the bump electrode made of solder provided on the semiconductor chip has a gap between it and the opposing conductor surface before fusion, which means that after fusion This is effective because the bump electrode has a drum-like shape, making it more durable against heat cycles.
第１図は本発明の一実施例のＩＣチップを示し、バンブ
電極２はチップ１の中央部にまとめて配置されている。
さらにチップｌの周辺部の四すみに突起体５が設けられ
ている。突起体５はバンブ電極２と同様にはんだからな
るが、バンブ電極２より高くされる０例えばバンブ電極
の高さが５０−の場合に１００−の高さにする。このチ
ップ１を第４図（ａｌに示すようにバンプｔｔｉ面を下
にして絶ｕ！、基板３の上に載せ、基板上の表面にはん
だ層４１を被覆した配線導体層４の上にバンブ電極２が
対向するようにする。また突起体５の対向する基体部分
にも表面にはんだＩｉ！６１を被覆した導体＋１６が存
在するが、これは配″ｋｌＡ導体層とは別個に設けられ
る。
突起体５は上述のようにハンプ電極２より高いから、突
起体５がはんだ′４６１に接触した場合、バンブ電極２
ははんだ層４１に接触しない、しかし加熱すると突起体
５ははんだ層６１に融着する際す、ブ１が沈み、バンブ
電極２がはんだ１４１と接触する。
その結果、バンプ電ＦＩｉＡ２とはんだＪｉ４１との連
結部７は第４図（ｂ）に拡大して示すように鼓状となる
。
このような形状の連結部は、バンブ電極２とはんだ１６
４１に加圧しながら融着した場合に生ずる第５図に示す
ビア樽状の連結部７１にくらべてヒートサイクルに対し
て強い。このようにして絶縁基板３に対して固着された
ＩＣチップ１はバンブ電極２のみでなく周辺部の突起体
５によっても基板に支持されるので、安定した支持状態
が得られる。
上述の実施例では突起体５をバンブ電極２より高く形成
したが、同し高さでもよい、また突起体５は必ずしも基
板に対して固着する必要はない。
すなわち基板に対して接触しているだけでもバンプ１Ｅ
ｉ２が基板上に配線導体に融着されたチップｌは傾くこ
とがなく、安定して支持される。あるいは突起体をチッ
プの上でなく絶縁基板の表面に設けて、チップに固着す
るか、チップに接触させてもよく、対向部位の双方に突
起体を設けてもよい、なおまた、突起体５もチップｌの
半導体層に接続されたバンブ電極として形成し、絶縁基
板上の配線導体層に融着させてもよい０例えばＩＣチッ
プ内に集積された４個の回路を並列に外部配線と接続す
る際の接続端子として用いる四すみのバンブ電極として
用いることも有効である。
突起体は必ずしも４個所に設ける必要がない。
最小限３個所にあればチップの安定な支持に役立つ、但
しチップの重心を通るチップ面内の線の両側に分かれて
存在しなければならないことは当然である。FIG. 1 shows an IC chip according to an embodiment of the present invention, in which bump electrodes 2 are arranged together in the center of the chip 1. As shown in FIG. Furthermore, protrusions 5 are provided at the four corners of the periphery of the chip l. The protrusion 5 is made of solder like the bump electrode 2, but is made higher than the bump electrode 2.For example, when the height of the bump electrode is 50-, the height is set to 100-. This chip 1 is placed on the substrate 3 with the bump tti surface facing down as shown in FIG. The electrodes 2 are made to face each other.Furthermore, there is also a conductor +16 whose surface is coated with solder Ii!61 on the opposing base portion of the protrusion 5, but this is provided separately from the klA conductor layer. Since the protrusion 5 is higher than the hump electrode 2 as described above, when the protrusion 5 contacts the solder '461, the bump electrode 2
However, when heated, when the protrusion 5 fuses to the solder layer 61, the bump 1 sinks and the bump electrode 2 comes into contact with the solder 141. As a result, the connecting portion 7 between the bump electric field FIiA2 and the solder Ji41 becomes drum-shaped as shown in an enlarged view in FIG. 4(b). The connecting portion having such a shape connects the bump electrode 2 and the solder 16.
It is more resistant to heat cycles than the beer barrel-shaped connecting portion 71 shown in FIG. Since the IC chip 1 fixed to the insulating substrate 3 in this manner is supported by the substrate not only by the bump electrodes 2 but also by the protrusions 5 on the periphery, a stable supporting state can be obtained. In the above-described embodiment, the projection 5 is formed higher than the bump electrode 2, but the height may be the same, and the projection 5 does not necessarily need to be fixed to the substrate. In other words, even if the bump is just in contact with the substrate, it is considered as bump 1E.
The chip l, in which i2 is fused to the wiring conductor on the substrate, is stably supported without tilting. Alternatively, the protrusions may be provided on the surface of the insulating substrate instead of on the chip, and may be fixed to or in contact with the chip, or the protrusions may be provided on both opposing parts. It may also be formed as a bump electrode connected to the semiconductor layer of the chip l and fused to the wiring conductor layer on the insulating substrate.For example, four circuits integrated within an IC chip may be connected in parallel to external wiring. It is also effective to use it as bump electrodes at the four corners, which are used as connection terminals when doing so. It is not necessary to provide the protrusions at four locations. Having at least three locations will help support the chip stably; however, it goes without saying that they must be located on both sides of a line in the chip plane passing through the center of gravity of the chip.
本発明は、半導体チップの中央部にバンブ電極を設けて
対向する絶縁基板上の配線４体に融着させる半導体装置
のチップの安定した支持の達成のためにチップの周辺部
あるいはそれに対向する基板上の部位の一方もしくは双
方に突起を設けて、チップと裁板の面間の間隔を規制す
るようにしたもので、バフ１１１間の距離の小さい、ヒ
ートサイクルに対しての信鎖性の高い半導体装置を得る
ことができ、フリンブチップ方式で実装されるＩＣに限
らず、他の半導体装置に有効に適用できる。The present invention provides a bump electrode in the center of a semiconductor chip and fuses it to four wiring bodies on opposing insulating substrates to achieve stable support of the chip of a semiconductor device. A protrusion is provided on one or both of the upper parts to regulate the distance between the chip and the surface of the cutting board, and the distance between the buffs 111 is small and the reliability against heat cycles is high. A semiconductor device can be obtained, and the present invention can be effectively applied not only to ICs mounted using the flimbu chip method but also to other semiconductor devices.
第１図は本発明の一実施例のＩＣチップを示し、（ａｌ
は平面図、（ｂ）は正面図、第２図は従来例のＩＣチッ
プの平面図、第３図は第２図のチップの基板への固着状
態を示す断面図、第４図は第１図に示したＩＣチップの
絶縁基板上への装着状態を示し、＋ａ＋は設置時の断面
図、（ｂ）はバンブ電極融着後の断面図、第５図は他の
バンブ電極融着後の状態の断面図である。
１：ＩＣチップ、２：バンブ電極、３：絶縁基板、４：
導体層、４１：はんだ層、５：突起体。FIG. 1 shows an IC chip according to an embodiment of the present invention, (al
is a plan view, (b) is a front view, FIG. 2 is a plan view of a conventional IC chip, FIG. 3 is a cross-sectional view showing how the chip in FIG. 2 is fixed to a substrate, and FIG. The IC chip shown in the figure is shown mounted on an insulating substrate, +a+ is a cross-sectional view when installed, (b) is a cross-sectional view after the bump electrode is fused, and Figure 5 is a cross-sectional view after the bump electrode is fused. It is a sectional view of the state. 1: IC chip, 2: bump electrode, 3: insulating substrate, 4:
Conductor layer, 41: solder layer, 5: protrusion.
Claims (1)
縁基板上の導体に融着されるものにおいて、半導体チッ
プの重心を通るチップ面内の線の両側に存在する３個所
以上の周辺部位と該周辺部位に対向する絶縁基板上の部
位の少なくとも一方に突起を有し、該突起が対向する面
に係合してチップ基板間の間隔を所定に保つことを特徴
とする半導体装置。 ２）特許請求の範囲第１項記載の記載の装置において、
バンプ電極がはんだよりなり、半導体チップ周辺部位の
突起を対向する基板面に当接させた際、融着前のバンプ
電極と対向導体面との間に空隙が存在することを特徴と
する半導体装置。[Claims] 1) In a device in which a bump electrode provided on a semiconductor chip is fused to a conductor on an opposing insulating substrate, three locations exist on both sides of a line in the chip plane passing through the center of gravity of the semiconductor chip. At least one of the peripheral area and the area on the insulating substrate facing the peripheral area has a protrusion, and the protrusion engages with the opposing surface to maintain a predetermined distance between the chip substrates. Semiconductor equipment. 2) In the device described in claim 1,
A semiconductor device characterized in that the bump electrode is made of solder and that when the protrusions on the peripheral portion of the semiconductor chip are brought into contact with the opposing substrate surface, a gap exists between the bump electrode before fusion and the opposing conductor surface. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19911885A JPS6258649A (en) | 1985-09-09 | 1985-09-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19911885A JPS6258649A (en) | 1985-09-09 | 1985-09-09 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6258649A true JPS6258649A (en) | 1987-03-14 |
Family
ID=16402435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19911885A Pending JPS6258649A (en) | 1985-09-09 | 1985-09-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6258649A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19706983B4 (en) * | 1996-02-23 | 2009-06-18 | Denso Corporation, Kariya | Surface mounting unit and transducer assemblies using the surface mounting unit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4992548A (en) * | 1973-01-10 | 1974-09-04 | ||
| JPS58157146A (en) * | 1982-03-12 | 1983-09-19 | Fujitsu Ltd | Semiconductor device |
| JPS61159745A (en) * | 1985-01-07 | 1986-07-19 | Hitachi Ltd | Fine connecting package structure |
-
1985
- 1985-09-09 JP JP19911885A patent/JPS6258649A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4992548A (en) * | 1973-01-10 | 1974-09-04 | ||
| JPS58157146A (en) * | 1982-03-12 | 1983-09-19 | Fujitsu Ltd | Semiconductor device |
| JPS61159745A (en) * | 1985-01-07 | 1986-07-19 | Hitachi Ltd | Fine connecting package structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19706983B4 (en) * | 1996-02-23 | 2009-06-18 | Denso Corporation, Kariya | Surface mounting unit and transducer assemblies using the surface mounting unit |
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