JPS625643A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS625643A JPS625643A JP14504585A JP14504585A JPS625643A JP S625643 A JPS625643 A JP S625643A JP 14504585 A JP14504585 A JP 14504585A JP 14504585 A JP14504585 A JP 14504585A JP S625643 A JPS625643 A JP S625643A
- Authority
- JP
- Japan
- Prior art keywords
- cavity
- capacity
- wirings
- wiring
- adjacent wirings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体メモリ等の半導体集積回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor integrated circuits such as semiconductor memories.
半導体集積回路は、これまで幾何学的寸法の縮小によっ
て大容量化、高性能化を達成してきておシ、今後もさら
に進展していくことが予想される。Semiconductor integrated circuits have achieved increased capacity and improved performance by reducing their geometric dimensions, and it is expected that this will continue to progress.
幾何学的寸法の縮小を水平方向、垂直方向同一の割合で
施すと、配線抵抗の増大、エレクトロマイグレーション
による配線寿命の減少等の問題を生じる。そこで一般に
は、垂直方向は殆んど縮小せずに、水平方向のみを縮小
するという方法が採用されている。第３図に示した従来
の半導体集積回路の配線では、この様な縮小を続け、配
線断面の縦、横の寸法が同程度の大きさになってくると
大きな問題を生じてくる。隣接配線間の相互容量が総配
線容量に占める割合が加速度的に大きくなりてくるから
である。第３図の中央の配線１４に着目すると、中央の
配線１４の配線容量は半導体基板１１との間の容量と、
隣接配線１３及び隣接配線１５との間の相互容量との和
となる。従来例においては、配線−基板間、配線−配線
間は同一の絶縁性物質１２で分離されているので、その
容量比はほぼ配線の面積と配線間距離によって決まる。If the geometric dimensions are reduced at the same rate in the horizontal and vertical directions, problems such as increased wiring resistance and reduced wiring life due to electromigration will occur. Therefore, a method is generally adopted in which the image is reduced only in the horizontal direction, with almost no reduction in the vertical direction. In the conventional semiconductor integrated circuit wiring shown in FIG. 3, if such reduction continues and the vertical and horizontal dimensions of the wiring cross section become approximately the same, a big problem will arise. This is because the ratio of the mutual capacitance between adjacent wirings to the total wiring capacitance increases at an accelerating rate. Focusing on the central wiring 14 in FIG. 3, the wiring capacitance of the central wiring 14 is the capacitance between it and the semiconductor substrate 11, and
This is the sum of the mutual capacitance between the adjacent wiring 13 and the adjacent wiring 15. In the conventional example, since the wiring and the substrate and the wiring and the wiring are separated by the same insulating material 12, the capacitance ratio is determined approximately by the area of the wiring and the distance between the wirings.
従って前述した水平方向のみを縮小していく様な方法で
は、単位長さ当シの隣接間配線容量が増加していくのく
対し、配線−基板間の単位長さ当シの容量は減少するの
で隣燈配線間容量が総配線容量に占める割合が急激に大
きくなる。Therefore, in the method of reducing only the horizontal direction described above, the capacitance between adjacent wirings per unit length increases, but the capacitance per unit length between the wiring and the board decreases. Therefore, the ratio of the capacitance between adjacent light wires to the total wire capacitance increases rapidly.
隣接配線間の相互容量が総配線容量に占める割合が増加
するということは、隣接配線の電位変化の影響を大きく
受けるということであシ、動作マージンの減少、誤動作
の原因となり、半導体集積回路にとって致命的な状態と
なる。An increase in the ratio of the mutual capacitance between adjacent wirings to the total wiring capacitance means that they are greatly affected by changes in the potential of adjacent wirings, which reduces operating margins and causes malfunctions, which is detrimental to semiconductor integrated circuits. The condition becomes fatal.
上述した様に、従来の半導体集積回路においては水平方
向のみ寸法を縮小していりた場合に隣接配線間の相互容
量が支配的となシ情報の誤りを生じ易いという問題が生
ずる。As described above, in conventional semiconductor integrated circuits, when the dimensions are reduced only in the horizontal direction, a problem arises in that information errors are likely to occur due to the dominant mutual capacitance between adjacent wirings.
本発明の目的は前述の従来の半導体集積回路の問題点を
緩和し、水平方向のみを縮小していった場合でも隣接配
線間の相互容量を従来例に較べて小さくしうる半導体集
積回路を提供するととくあるＯ
〔問題点を解決するだめの手段〕
本発明は隣接する配線相互間の分離領域の一部に空洞を
介在せしめたことを特徴とする半導体集積回路である。An object of the present invention is to alleviate the problems of the conventional semiconductor integrated circuit described above, and to provide a semiconductor integrated circuit that can reduce the mutual capacitance between adjacent wirings compared to the conventional example even when the size is reduced only in the horizontal direction. [Means for solving the problem] The present invention is a semiconductor integrated circuit characterized in that a cavity is interposed in a part of the separation region between adjacent wirings.
隣接配線間の絶縁性物質に設けた空洞内の誘電率の小さ
い空気を絶縁性物質として利用し、隣接配線間相互容量
の増大を防ぐ。Air with a low dielectric constant in a cavity provided in an insulating material between adjacent wirings is used as an insulating material to prevent an increase in mutual capacitance between adjacent wirings.
以下、本発明の典を的な実施例を示す第１図を参照しな
がら本発明の詳細な説明する。Hereinafter, the present invention will be described in detail with reference to FIG. 1, which shows a typical embodiment of the present invention.
第１図は第３図に示した従来例に本発明を適用した例を
示す模式的な断面図である。第１図において、配線３と
配線４との間に空洞６を設け、また、配線４と配線５と
の間に空洞７を設けている。FIG. 1 is a schematic sectional view showing an example in which the present invention is applied to the conventional example shown in FIG. In FIG. 1, a cavity 6 is provided between the wiring 3 and the wiring 4, and a cavity 7 is provided between the wiring 4 and the wiring 5.
また絶縁性物質２による膜としては通常二酸化珪素膜が
用いられる。空洞がある場合には隣接配線間の容量は配
線と空洞間の容量、空洞部の容量。Furthermore, as the film made of the insulating material 2, a silicon dioxide film is usually used. If there is a cavity, the capacitance between adjacent wires is the capacitance between the wire and the cavity, and the capacitance of the cavity.
空洞ともう一方の配線間の容量の３つの容量が直・列に
接続されたものとみなすことができる。空洞部の容量は
絶縁性物質が比誘電率の低い空気であシ、他の部分の絶
縁性物質である二酸化珪素膜の比誘電率に較べ約１／４
の値であるので、本発明の様に空洞を設けることによシ
隣接配線間の容量は減少する。例えば空洞の幅が隣接配
線間距離の１７３の時には隣接配線間容量は空洞がない
場合の１／２になる。空洞が大きければ大きい程、隣接
配線間容量は小さくなる。又、配線と基板間の容量は空
洞の有無によらずほぼ一定となるので、隣接配線間容量
が全配線容量に占める割合は従来の構成に較べ減少する
ことになる。従って、隣接配線間の相互容量による電位
変動も減少し、従来例に較べ誤動作が生じに＜＜、又、
動作マージンが広くなる。It can be considered that three capacitances, that is, the capacitance between the cavity and the other wiring, are connected in series. The capacitance of the cavity is that the insulating material is air, which has a low dielectric constant, and is approximately 1/4 of the dielectric constant of the silicon dioxide film, which is the insulating material in other parts.
Therefore, by providing a cavity as in the present invention, the capacitance between adjacent wirings is reduced. For example, when the width of the cavity is 173 times the distance between adjacent wirings, the capacitance between adjacent wirings is 1/2 of that without a cavity. The larger the cavity, the smaller the capacitance between adjacent wires. Furthermore, since the capacitance between the wiring and the substrate is approximately constant regardless of the presence or absence of a cavity, the ratio of the capacitance between adjacent wirings to the total wiring capacitance is reduced compared to the conventional configuration. Therefore, potential fluctuations due to mutual capacitance between adjacent wirings are also reduced, and malfunctions are less likely to occur than in the conventional example.
The operating margin becomes wider.
隣接する配線相互間の絶縁性物質２内に空洞を形成する
のは簡単である。隣接配線間の相互容量が問題となる状
況、すなわち隣接配線間距離が小さく、配線膜厚が厚い
状態では、配線形成後１１通常用いられているＣＶＤ法
によシ絶縁性物質２を被着することにより容易に空洞は
形成される。但し、この場合には空洞は配線底面よシ若
干浮いた位置に形成される。第１図に示す様に空洞６，
７を充分深い位置に形成するには、配線形成時にオー／
４エツチを行ない、配線３，４．５間の下部にある絶縁
性物質２のみを多少エツチングして、第２″図に示す形
状とし、この上にＣＶＤ法によシ絶縁性物質２を被着す
ればよい。It is easy to form cavities in the insulating material 2 between adjacent wires. In a situation where the mutual capacitance between adjacent wirings is a problem, that is, when the distance between adjacent wirings is small and the wiring film thickness is thick, an insulating material 2 is deposited by the commonly used CVD method after the wiring is formed. As a result, cavities are easily formed. However, in this case, the cavity is formed at a position slightly lifted from the bottom surface of the wiring. As shown in Fig. 1, the cavity 6,
In order to form 7 at a sufficiently deep position, it is necessary to
4. Then, only the insulating material 2 at the bottom between the wirings 3 and 4.5 is slightly etched to form the shape shown in FIG. Just wear it.
以上述べた様に、本発明によれば、隣接配線間の相互容
量が全体の配線容量に占める割合を小さく抑えることが
でき、したがって誤動作が生じ難く、動作マージンの広
い半導体集積回路を得ることができる効果を有するもの
である。As described above, according to the present invention, the proportion of the mutual capacitance between adjacent wirings in the overall wiring capacitance can be suppressed to a small value, and therefore it is possible to obtain a semiconductor integrated circuit that is less likely to malfunction and has a wide operating margin. It has the effect that it can.
第１−４図は本発明の一実施例の模式的断面図、第２図
は空洞形成要領の説明図、第３図は従来の半導体集積回
路の模式的断面図である。
ｌ・・・半導体基板、２・・・二酸化珪素膜（絶縁性物
質）、３，４．５・・・配線、６，７・・・空洞。
第１図
第２図1-4 are schematic cross-sectional views of an embodiment of the present invention, FIG. 2 is an explanatory view of the procedure for forming a cavity, and FIG. 3 is a schematic cross-sectional view of a conventional semiconductor integrated circuit. 1... Semiconductor substrate, 2... Silicon dioxide film (insulating material), 3, 4.5... Wiring, 6, 7... Cavity. Figure 1 Figure 2
Claims (1)
在せしめたことを特徴とする半導体集積回路。(1) A semiconductor integrated circuit characterized in that a cavity is interposed in a part of a separation region between adjacent wirings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14504585A JPS625643A (en) | 1985-07-01 | 1985-07-01 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14504585A JPS625643A (en) | 1985-07-01 | 1985-07-01 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS625643A true JPS625643A (en) | 1987-01-12 |
Family
ID=15376109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14504585A Pending JPS625643A (en) | 1985-07-01 | 1985-07-01 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS625643A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0473964A (en) * | 1990-07-16 | 1992-03-09 | Sony Corp | Semiconductor memory |
| EP0766290A3 (en) * | 1995-09-27 | 1997-05-14 | Sgs Thomson Microelectronics | |
| US5668398A (en) * | 1994-05-27 | 1997-09-16 | Texas Instruments Incorporated | Multilevel interconnect structure with air gaps formed between metal leads |
| US5837618A (en) * | 1995-06-07 | 1998-11-17 | Advanced Micro Devices, Inc. | Uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines |
| US5861674A (en) * | 1997-02-20 | 1999-01-19 | Nec Corporation | Multilevel interconnection in a semiconductor device and method for forming the same |
| US6093633A (en) * | 1996-02-29 | 2000-07-25 | Nec Corporation | Method of making a semiconductor device |
| US6146989A (en) * | 1996-11-20 | 2000-11-14 | Nec Corporation | Method of fabricating semiconductor device with cavity interposed between wirings |
| US6191467B1 (en) * | 1998-05-08 | 2001-02-20 | Hyundai Electronics Industries Co., Ltd. | Semiconductor device and method for fabricating the same |
| US6242336B1 (en) | 1997-11-06 | 2001-06-05 | Matsushita Electronics Corporation | Semiconductor device having multilevel interconnection structure and method for fabricating the same |
| US6376357B1 (en) | 1997-05-30 | 2002-04-23 | Nec Corporation | Method for manufacturing a semiconductor device with voids in the insulation film between wirings |
| JP2005512342A (en) * | 2001-12-08 | 2005-04-28 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Trench type semiconductor device and manufacturing method thereof |
| US7504699B1 (en) * | 1997-01-21 | 2009-03-17 | George Tech Research Corporation | Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections |
-
1985
- 1985-07-01 JP JP14504585A patent/JPS625643A/en active Pending
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0473964A (en) * | 1990-07-16 | 1992-03-09 | Sony Corp | Semiconductor memory |
| US5668398A (en) * | 1994-05-27 | 1997-09-16 | Texas Instruments Incorporated | Multilevel interconnect structure with air gaps formed between metal leads |
| US5936295A (en) * | 1994-05-27 | 1999-08-10 | Texas Instruments Incorporated | Multilevel interconnect structure with air gaps formed between metal leads |
| US5837618A (en) * | 1995-06-07 | 1998-11-17 | Advanced Micro Devices, Inc. | Uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines |
| US5960311A (en) * | 1995-09-27 | 1999-09-28 | Stmicroelectronics, Inc. | Method for forming controlled voids in interlevel dielectric |
| EP0766290A3 (en) * | 1995-09-27 | 1997-05-14 | Sgs Thomson Microelectronics | |
| US5847464A (en) * | 1995-09-27 | 1998-12-08 | Sgs-Thomson Microelectronics, Inc. | Method for forming controlled voids in interlevel dielectric |
| US6093633A (en) * | 1996-02-29 | 2000-07-25 | Nec Corporation | Method of making a semiconductor device |
| US6146989A (en) * | 1996-11-20 | 2000-11-14 | Nec Corporation | Method of fabricating semiconductor device with cavity interposed between wirings |
| US7504699B1 (en) * | 1997-01-21 | 2009-03-17 | George Tech Research Corporation | Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections |
| US5861674A (en) * | 1997-02-20 | 1999-01-19 | Nec Corporation | Multilevel interconnection in a semiconductor device and method for forming the same |
| US6239016B1 (en) | 1997-02-20 | 2001-05-29 | Nec Corporation | Multilevel interconnection in a semiconductor device and method for forming the same |
| US6376357B1 (en) | 1997-05-30 | 2002-04-23 | Nec Corporation | Method for manufacturing a semiconductor device with voids in the insulation film between wirings |
| US6242336B1 (en) | 1997-11-06 | 2001-06-05 | Matsushita Electronics Corporation | Semiconductor device having multilevel interconnection structure and method for fabricating the same |
| US6545361B2 (en) | 1997-11-06 | 2003-04-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having multilevel interconnection structure and method for fabricating the same |
| US6191467B1 (en) * | 1998-05-08 | 2001-02-20 | Hyundai Electronics Industries Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP2005512342A (en) * | 2001-12-08 | 2005-04-28 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Trench type semiconductor device and manufacturing method thereof |
| JP4804715B2 (en) * | 2001-12-08 | 2011-11-02 | エヌエックスピー ビー ヴィ | Manufacturing method of trench type semiconductor device |
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