JPS6247191A - Printed wiring board and manufacture thereof - Google Patents
Printed wiring board and manufacture thereofInfo
- Publication number
- JPS6247191A JPS6247191A JP18789485A JP18789485A JPS6247191A JP S6247191 A JPS6247191 A JP S6247191A JP 18789485 A JP18789485 A JP 18789485A JP 18789485 A JP18789485 A JP 18789485A JP S6247191 A JPS6247191 A JP S6247191A
- Authority
- JP
- Japan
- Prior art keywords
- resist layer
- conductor pattern
- resist
- wiring board
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
(産業上の利用分野)
この発明は、各種電子部品取付用のプリント配線板およ
びその製造方法に関し、更に詳しくは半田ブリッジを防
止するためのダブルレジストが施されたプリント配線板
およびダブルレジストを施す方法に関するものである。Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a printed wiring board for mounting various electronic components and a method for manufacturing the same, and more specifically to a printed wiring board with double resist applied to prevent solder bridging. The present invention relates to a wiring board and a method for applying double resist.
(従来の技術)
従来から、半田ブリッジを防止する手段としては第3図
に示すようにダブルレジストを採用したプリント配線板
がある。絶縁基板1上に導電体がプリント印刷された導
電体パターン2が形成され、この導電体パターン2の導
電体りにランド3を残して全面レジスト層4がシルク印
刷で形成され、さらに少なくともランド3間、ここでは
連続したランド3の周囲を一体に矩形状に覆う部分レジ
スト層5が同様にシルク印刷で全面レジスト層4に重ね
て形成されている。(Prior Art) Conventionally, as a means for preventing solder bridging, there is a printed wiring board employing double resist as shown in FIG. A conductor pattern 2 in which a conductor is printed is formed on an insulating substrate 1, and a resist layer 4 is formed on the entire surface of the conductor pattern 2 by silk printing, leaving lands 3 on the conductor, and furthermore, at least the lands 3 are formed on the conductor pattern 2 by silk printing. Meanwhile, here, a partial resist layer 5 that integrally covers the periphery of the continuous land 3 in a rectangular shape is similarly formed by silk printing to overlap the entire surface resist layer 4.
(発明が解決しようとする問題点)
しかしながら、このようなプリント配線板では、半田ブ
リッジを防止するため、」ユ記の手段が採られているが
、部分レジスト層が全面レジスト層の後工程で作られる
こととなっているため、部分レジス1一層が剥がれ易い
という問題があった。また、この部分レジス1一層はラ
ンド等の形状に合オ)せて、タブルレシス1〜を設ける
位Illや形状を決めるため、該当する箇所ごとに指定
した版■を作製する必要があり、かなり人手や時間等を
要するという問題があった。(Problem to be Solved by the Invention) However, in such a printed wiring board, in order to prevent solder bridges, the method described in "U" is adopted, but the partial resist layer is formed in the post-process of the entire resist layer. Since the partial resist 1 layer is to be manufactured, there is a problem in that the partial resist 1 layer is easily peeled off. In addition, in order to match the shape of this partial resist 1 layer to the shape of the land, etc., and to determine the Ill and shape of the double resist 1~, it is necessary to prepare a specified plate (■) for each corresponding location, which requires a considerable amount of manpower. There is a problem that it takes a lot of time and time.
(発明の目的)
この発明は、部分レジスI〜層が剥がれ難く、シかも廉
価なプリント配線板を提供するとともに、製作時間を短
縮しうるプリント配線板の製造方法を提供することを目
的としている。(Objective of the Invention) An object of the present invention is to provide a printed wiring board in which the partial resist I layer is difficult to peel off and is inexpensive, as well as to provide a method for manufacturing a printed wiring board that can shorten the manufacturing time. .
(問題点を解決するための手段)
そこで、この発明は、上記[1的を達成するために、第
1発明は、絶縁基板には導電体パターンが形成され、前
記絶縁基板の+?if記導電体パターンが形成されてい
ない部分に第1レジスト層が形成され、さらに該第ルシ
ス1一層と前記導電体パターンとの1−にランドを残し
て全血的に第2レジスト層が形成されたプリン1−配線
板とし、第2発明は、絶縁基板に導電体を一面に形成し
7、該導電体に導電体パターン用版下でフォトエツチン
グにより、導電体パターンを形成し7、M?i記導電導
電体パターン用版下ジネガをjヴ!転した第1レジスト
層塗布用版下で第1レジス1〜層を形成し、ランドを残
した第2レジスト層用版下で前記導電体パターンと1前
記第ルジスl〜層との1−に第2レジスト層を形成する
プリント配線板の製造方法としている。(Means for Solving the Problems) Therefore, the present invention provides the above-mentioned [In order to achieve the first object, the first invention provides that a conductive pattern is formed on an insulating substrate, and a conductor pattern is formed on the insulating substrate, and a conductor pattern is formed on the insulating substrate. If a first resist layer is formed on the portion where the conductor pattern is not formed, and further a second resist layer is formed on the whole blood leaving a land between the first Lucis 1 layer and the conductor pattern. In the second invention, a conductor is formed on one surface of an insulating substrate, and a conductor pattern is formed on the conductor by photo-etching using a plate for conductor patterns. ? I have created a negative plate for conductive conductor patterns! Form the first resist layer 1 to 1 on the transferred first resist layer coating plate, and then form the first resist layer 1 to 1 on the conductive pattern and the first resist layer 1 to 1 on the second resist layer coating plate with the land left. This is a method for manufacturing a printed wiring board in which a second resist layer is formed.
(作 用)
部分レジスト層である第1レジスト層タ全面!ノジス1
へ層である第2レジス1〜層で覆りおり、第1レジスト
層は剥がれ難い。また、導電体パターン用版下のポジネ
ガを逆転して第ルジス1一層用版ドを作ることができる
ので、人手や時間を省くことができ、この版ドで導電体
パターンが形成されていない部分に第1レジスト層を形
成することができる。(Function) The entire surface of the first resist layer, which is a partial resist layer! Nojis 1
The second resist layer is covered with the first resist layer, and the first resist layer is difficult to peel off. In addition, since the positive and negative sides of the conductor pattern plate can be reversed to create a plate for the 1st layer of Lugis, manpower and time can be saved, and the parts on which the conductor pattern is not formed can be created using this plate. A first resist layer can be formed on the substrate.
(実施例)
次に図面に基づいてこの発明製説明する。第1図および
第2図はこの発明の一実施例を示す図である。従来と同
一ないし均等な部位又は部材については同一・符号を付
して重複した説明を省略する。(Example) Next, the invention will be explained based on the drawings. FIG. 1 and FIG. 2 are diagrams showing one embodiment of the present invention. Portions or members that are the same or equivalent to those in the prior art will be given the same reference numerals and redundant explanations will be omitted.
第1図および第2図において、絶縁基板1−1−には導
電体パターン2プリン1〜印刷によって形成されている
。この導電体パターン2は、絶縁基板1の一面ty導電
体層が形成され、導電体パターン用版lりを用いてフ第
1・エツチングされて形成されている。導電体パターン
2が形成された絶縁基板1の而には、導電体パターン用
版下のポジネガを逆転した第ルジス1一層用版下で導電
体パターン2が形成されていない部分に第1レジス1〜
層6が形成されている。このポジネガを逆転して版下を
作ることは、従来の部分レジスト層5をシルク印刷のた
めに作る版下のように、この部分の塗装のためだけ、寸
法や位置を指定して特別に作るのに比へて、大変に簡l
ltに光学的に行なえる。したがって、導電体パターン
2のない部分、すなわちフォトエツチングで導電体が除
去されて四部となっている部分に、第】レジス1一層6
が充填して形成されている状態である。しかしながら、
導電体パタ一ン2の厚みと第1レジスト層6との厚みは
図において同一であるが、同一である必要はない。In FIGS. 1 and 2, a conductor pattern 2 is formed on an insulating substrate 1-1- by printing. The conductor pattern 2 is formed by forming a conductor layer on one surface of the insulating substrate 1 and then etching it using a conductor pattern plate. On the insulating substrate 1 on which the conductor pattern 2 is formed, a first resist 1 is placed on the part where the conductor pattern 2 is not formed using the first resist 1, which is a negative/positive version of the conductor pattern base. ~
Layer 6 is formed. Creating a block copy by reversing this positive/negative is similar to the conventional block copy made for silk printing using the partial resist layer 5, and is made specially by specifying the dimensions and position just for painting this part. It is very simple compared to
It can be done optically. Therefore, in the portion where the conductor pattern 2 is not present, that is, the portion where the conductor has been removed by photoetching and has become four parts, the resist 1 layer 6 is etched.
It is in a state where it is filled with. however,
Although the thickness of the conductor pattern 2 and the thickness of the first resist layer 6 are the same in the figure, they do not need to be the same.
この導電体パターン2および第1レジスト層6が形成さ
れた絶縁基板1の而にランド3を残して全面的に第2レ
ジス1〜層7がシルク印刷等で形成されている。この第
2レジス1一層7は従来の技術で述べた全面レジスト層
4に相当し、この印刷に用いられるラント3を残した第
21ノジスト用版下は従来の技術で用いるものと同様で
第2レジス1へ層用版下とは全く別個に準備しなければ
ならないものである。On the insulating substrate 1 on which the conductive pattern 2 and the first resist layer 6 are formed, second resists 1 to 7 are formed by silk printing or the like over the entire surface, leaving lands 3. This second resist 1 layer 7 corresponds to the entire surface resist layer 4 described in the conventional technique, and the 21st resist layer 7, which is used for this printing and leaves the runt 3, is the same as that used in the conventional technique. This must be prepared completely separately from the layer for resist 1.
このような、構造をしたプリント配線板にあっては、部
分レジス1へ層となる第1レジスト層6が全面レジスト
層となる第2レジスト層7の+側となるため、種々の角
部が表面にでて引っ掛かるようなことがなく、あるいは
経時的にも空気や湿気が接着面へ浸透し難いので剥がれ
が生じ難い。In a printed wiring board having such a structure, the first resist layer 6 that forms the layer for the partial resist 1 is on the positive side of the second resist layer 7 that forms the entire surface resist layer. It does not get stuck on the surface, and it is difficult for air and moisture to penetrate into the adhesive surface over time, so it is difficult to peel off.
なお、8は図示しない電子部品のリード端子を挿入し、
ランド3と半Fl付けさせる貫通孔である。In addition, 8 inserts a lead terminal of an electronic component (not shown),
This is a through hole that connects the land 3 with a half-Fl.
(発明の効果)
以」二説明してきたように、この発明によれば、レジス
1〜層の剥がれが生じ鐙い信頼性のあるプリント配線板
を提供するとともに、導電体パターン用版ドのポジネガ
を逆転した第2レジスト用版下を使用することから、製
造容易で工数を短縮できるプリント配線板の製造方法を
提供することができる。(Effects of the Invention) As described above, according to the present invention, it is possible to provide a highly reliable printed wiring board in which peeling of the resist layers 1 to 10 occurs, and also to provide a printed wiring board that is highly reliable in the case where the resist 1 layer is peeled off. Since the second resist printing plate is used, it is possible to provide a method for manufacturing a printed wiring board that is easy to manufacture and can reduce the number of man-hours.
第1図および第2図は、この発明のプリン1へ配線板の
一実施例を示すもので、第1図は第2図の1−1相当断
面図、第2図は部分的に切欠した部分平面図、第3図は
従来のプリント配線板の第2図と同様な図である。
1・・・絶縁基板 2・・・導電体パターン3・
ランド 6・・・第1レジスト層7・・・第
2レジスト層
第1図
第2図
第3図Figures 1 and 2 show an embodiment of the wiring board for printer 1 of the present invention. Figure 1 is a sectional view corresponding to 1-1 in Figure 2, and Figure 2 is a partially cutaway view. The partial plan view, FIG. 3, is similar to FIG. 2 of the conventional printed wiring board. 1... Insulating substrate 2... Conductor pattern 3.
Land 6...First resist layer 7...Second resist layer Figure 1 Figure 2 Figure 3
Claims (2)
基板の前記導電体パターンが形成されていない部分に第
1レジスト層が形成され、さらに該第1レジスト層と前
記導電体パターンとの上にランドを残して全面的に第2
レジスト層が形成されたことを特徴とするプリント配線
板。(1) A conductor pattern is formed on an insulating substrate, a first resist layer is formed on a portion of the insulating substrate where the conductor pattern is not formed, and further on the first resist layer and the conductor pattern. The second land is completely left in the second position.
A printed wiring board characterized by forming a resist layer.
電体パターン用版下でフォトエッチングにより、導電体
パターンを形成し、前記導電体パターン用版下のポジネ
ガを逆転した第1レジスト層用版下で第1レジスト層を
形成し、ランドを残した第2レジスト層用版下で前記導
電体パターンと前記第1レジスト層との上に第2レジス
ト層を形成することを特徴とするプリント配線板の製造
方法。(2) A conductor is formed on one surface of an insulating substrate, a conductor pattern is formed on the conductor by photo-etching using a conductor pattern plate, and the positive/negative of the conductor pattern plate is reversed. A first resist layer is formed under a resist layer printing plate, and a second resist layer is formed on the conductive pattern and the first resist layer using a second resist layer printing plate leaving a land. A method for manufacturing a printed wiring board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18789485A JPS6247191A (en) | 1985-08-26 | 1985-08-26 | Printed wiring board and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18789485A JPS6247191A (en) | 1985-08-26 | 1985-08-26 | Printed wiring board and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6247191A true JPS6247191A (en) | 1987-02-28 |
Family
ID=16214054
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18789485A Pending JPS6247191A (en) | 1985-08-26 | 1985-08-26 | Printed wiring board and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6247191A (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5550685A (en) * | 1978-10-11 | 1980-04-12 | Shigeki Shimamura | Method of manufacturing printed board |
JPS57128096A (en) * | 1981-01-30 | 1982-08-09 | Elna Co Ltd | Method of producing printed circuit board |
JPS6072294A (en) * | 1983-09-28 | 1985-04-24 | 富士通株式会社 | Method of forming solder resist |
JPS61242095A (en) * | 1985-04-19 | 1986-10-28 | ソニー株式会社 | Manufacture of printed wiring circuit board |
-
1985
- 1985-08-26 JP JP18789485A patent/JPS6247191A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5550685A (en) * | 1978-10-11 | 1980-04-12 | Shigeki Shimamura | Method of manufacturing printed board |
JPS57128096A (en) * | 1981-01-30 | 1982-08-09 | Elna Co Ltd | Method of producing printed circuit board |
JPS6072294A (en) * | 1983-09-28 | 1985-04-24 | 富士通株式会社 | Method of forming solder resist |
JPS61242095A (en) * | 1985-04-19 | 1986-10-28 | ソニー株式会社 | Manufacture of printed wiring circuit board |
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