JPS6246551A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6246551A JPS6246551A JP60185682A JP18568285A JPS6246551A JP S6246551 A JPS6246551 A JP S6246551A JP 60185682 A JP60185682 A JP 60185682A JP 18568285 A JP18568285 A JP 18568285A JP S6246551 A JPS6246551 A JP S6246551A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- layer
- mim capacitor
- capacitor
- built
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、金属−絶縁膜−金属構造（以下ＭＩＭ構造と
いう）のコンデンサを含み、かつ二層配線構造を有する
半導体集積回路装置に関するものである。Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device that includes a metal-insulating film-metal structure (hereinafter referred to as MIM structure) capacitor and has a two-layer wiring structure. be.
剛化が活発に行なわれつつある。例えば、ガリウムヒ素
（ＧａＡｓ ）を用いたマイクロ波帯用の増幅装置は、
その最も代表的なものの１つである。このマイクロ波帯
用の増幅装置等のＧａＡｓ半導体集積回路装置は、通常
ＧａＡｓ＋ ＦＥＴ、インダクタ、コンデンサ等で構成
されている。とのコンデンサを形成する方法としては、
各種の方法があるが、非常に小さな容量値である場合を
除いて、ＭＩＭ構造を用いる場合が多い。このＭＩＭ構
造のコンデンサは、絶縁膜（Ｉ層）の厚さが薄い程、単
位面積当りの容量値が大きくなるので、コンデンサの占
有面積は小さくてよい。Rigidization is being actively carried out. For example, a microwave band amplifier using gallium arsenide (GaAs) is
It is one of the most representative ones. GaAs semiconductor integrated circuit devices such as amplifiers for microwave bands are usually composed of GaAs+ FETs, inductors, capacitors, and the like. As a method of forming a capacitor with
Although there are various methods, an MIM structure is often used except in cases where the capacitance value is very small. In a capacitor having this MIM structure, the thinner the insulating film (I layer) is, the larger the capacitance value per unit area is, so the area occupied by the capacitor may be small.
一方、ＧａＡｓ半導体集積回路装置では、各素子間の配
線は眉間絶縁膜を挾んで上下に電極・配線層を配した二
層配線構造で形成されている。従って、ＭＩＭ構造のコ
ンデンサを含むＧａＡｓ半導体集積回路装置では、一般
に第２図に示すように、ＭＩＭコンデンサの絶縁膜と二
層配線間の絶縁膜とが同一の ゛絶縁膜で構成されてい
た。なおこの図で、ｌはＭＩＭコンデンサ部、２は抵抗
素子部、３はＦＥＴ部、４は半絶縁性のＧａＡｓ基板、
５は注入層、６は下部電極・配線層、６ａ、６ｂはそれ
ぞれＦＥＴのソース、ドレイン電極、７はダート電極、
８は絶縁膜、９は上部電極・配線層である。On the other hand, in a GaAs semiconductor integrated circuit device, wiring between each element is formed in a two-layer wiring structure in which electrode/wiring layers are arranged above and below with an insulating film between the eyebrows in between. Therefore, in a GaAs semiconductor integrated circuit device including a capacitor having an MIM structure, as shown in FIG. 2, the insulating film of the MIM capacitor and the insulating film between the two-layer interconnects are generally composed of the same insulating film. In this figure, l is the MIM capacitor section, 2 is the resistance element section, 3 is the FET section, 4 is the semi-insulating GaAs substrate,
5 is an injection layer, 6 is a lower electrode/wiring layer, 6a and 6b are FET source and drain electrodes, respectively, 7 is a dirt electrode,
8 is an insulating film, and 9 is an upper electrode/wiring layer.
（発明が解決しようとする問題点）
しかしながら、上記のような構成では、ＭＩＭコンデン
サの絶縁膜と二層配線間の眉間絶縁膜とが同一の絶縁膜
８で構成されているために、下記のような不都合があっ
た。ＭＩＭコンデンサの単位面積当たシの容量を大きく
して集積回路装置のチップサイズを小さくするために、
絶縁膜の厚さを薄くすれば、同時にＦＥＴの配線容量等
の寄生容量が増大し、集積回路装置の高い周波数領域に
おける特性を悪化させる。逆に、配線による寄生容量を
小さくするために絶縁膜の厚さを厚くすれば、ＭＩＭコ
ンデンサの単位面積当たシの容量が小さくなって、コン
デンサの占有面積が大きくなるという問題が生じ、いず
れにしても実用上の大きな問題でおりた。(Problems to be Solved by the Invention) However, in the above configuration, since the insulating film of the MIM capacitor and the glabellar insulating film between the two-layer wiring are composed of the same insulating film 8, the following problem occurs. There was such an inconvenience. In order to increase the capacitance per unit area of MIM capacitors and reduce the chip size of integrated circuit devices,
If the thickness of the insulating film is reduced, parasitic capacitance such as FET wiring capacitance increases at the same time, which deteriorates the characteristics of the integrated circuit device in a high frequency range. Conversely, if the thickness of the insulating film is increased to reduce the parasitic capacitance due to wiring, the capacitance per unit area of the MIM capacitor will become smaller, causing the problem that the area occupied by the capacitor will increase. However, it was a big practical problem.
（問題点を解決するための手段）
上記問題点を解決するために、本発明の半導体集積回路
装置では、層間絶縁膜を二層の積層構造とし、その二層
のうちの何れか一方をコンデンサの絶縁膜として使用す
るものである。(Means for Solving the Problems) In order to solve the above problems, in the semiconductor integrated circuit device of the present invention, the interlayer insulating film has a two-layer laminated structure, and one of the two layers is connected to a capacitor. It is used as an insulating film.
（作用）
この構成によって、眉間絶縁膜をＭＩＭコンデンサの絶
縁膜よりも厚くすることができ、配線による寄生容量を
極力小さくし、ＭＩＭコンデンサの単位面積当たりの容
量値を大きくすることが可能になる。(Function) With this configuration, the insulating film between the eyebrows can be made thicker than the insulating film of the MIM capacitor, the parasitic capacitance due to wiring can be minimized, and the capacitance value per unit area of the MIM capacitor can be increased. .
（実施例）
以下、本発明の一実施例について、図面を参照しながら
説明する。第１図は、本発明の一実施例におけるＧａＡ
ｇ半導体集積回路装置の断面を示したものである。なお
、第２図と同一符号のものは同一のものを示している。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows GaA in one embodiment of the present invention.
g shows a cross section of a semiconductor integrated circuit device. Note that the same reference numerals as in FIG. 2 indicate the same parts.
まず半絶縁性ＧａＡ＠基板４にＳｔのイオン注入を行な
い、注入層５を形成する。First, St ions are implanted into the semi-insulating GaA@substrate 4 to form an implantation layer 5.
その後、 ＭＩＭコンデンサの下部電極、およびＦＥＴ
。Then the bottom electrode of the MIM capacitor and the FET
.
抵抗素子のオーミック金属を構成する下部電極・配線層
６をＡｕＧｅ／Ｎｉ／Ａｕで、／ｆた、ＦＥＴのゲート
電極７をＴｉ／Ａｔで形成する。ここで絶縁膜を形成す
るが、本実施例では、まず第一層目の絶縁膜Ａｌｌとし
一’ｃ ５ｔｏ２ｓ ｏ ｏ ＯＸをＣＶＤ法で形成し
た後、ＭＩＭコンデンサ部分のみ、このＳｉＯ□膜を除
去し、次いでその上に第二層目の絶縁膜Ｂ１２として５
１３Ｎ４３０００Ｘをプラ、Ｉ” マＣ’ＶＤ法で形成
する。The lower electrode/wiring layer 6 constituting the ohmic metal of the resistance element is formed of AuGe/Ni/Au, and the gate electrode 7 of the FET is formed of Ti/At. Here, an insulating film is formed. In this example, first, a first layer of insulating film All is formed by CVD method, and then this SiO□ film is removed only from the MIM capacitor part. Then, on top of that, a second insulating film B12 is formed.
13N43000X is formed using the plastic, I'', and C'VD method.
その後、 Ｔｉ／ＡｕでＭＩＭコンデンサの上部電極を
含む上部電極・配線層９を形成する。Thereafter, an upper electrode/wiring layer 9 including the upper electrode of the MIM capacitor is formed using Ti/Au.
以上のように、本実施例では、 ＭＩＭコンデンサの絶
縁膜としては、５ｔｓＮ４３０００ Ａのみが用いられ
ており、眉間絶縁膜としては、８１０２５０００ Ｘ／
５ｉ３Ｎ４３０００１の二層構造となっている。As described above, in this example, only 5tsN43000A is used as the insulating film of the MIM capacitor, and 81025000X/
It has a two-layer structure of 5i3N430001.
ＭＩＭ構造のコンデンサの容量Ｃは、次式で与えられる
。The capacitance C of a capacitor with an MIM structure is given by the following equation.
ここで、εｒは絶縁膜の比誘電率、ε０は真空の誘電率
、Ｓは電極面積、ｄは絶縁膜厚である。この式から明ら
かなように、本発明の構造では、絶縁膜厚ｄの差による
効果と共に、絶縁膜を構成する材料の種類を適当に選ぶ
ことによって、比誘電率の差による効果も期待すること
ができる。Here, εr is the dielectric constant of the insulating film, ε0 is the dielectric constant of vacuum, S is the electrode area, and d is the thickness of the insulating film. As is clear from this equation, in the structure of the present invention, in addition to the effect due to the difference in the insulating film thickness d, it is also possible to expect the effect due to the difference in dielectric constant by appropriately selecting the type of material that constitutes the insulating film. Can be done.
本実施例においては、例えば絶縁膜として５ｉＯ２５０
００Ｘを用いた従来構成に比べて、ＭＩＭコンデンサの
容量は約２．９倍に増加し、逆に配線による寄生容量は
約０８７４倍と減少する。また、絶縁膜として５ｉ３Ｎ
４３０００Ｘを用いた場合の従来構成に比べて、ＭＩＭ
コンデンサの容量は変わらないが、配線による寄生容量
は約０．２５倍に小さくなる。In this example, for example, 5iO250 is used as the insulating film.
Compared to the conventional configuration using 00X, the capacitance of the MIM capacitor increases about 2.9 times, and conversely, the parasitic capacitance due to wiring decreases to about 0874 times. In addition, as an insulating film, 5i3N
Compared to the conventional configuration using 43000X, MIM
Although the capacitance of the capacitor remains the same, the parasitic capacitance due to wiring is reduced by about 0.25 times.
また、本発明の構造は、前述のように、絶縁膜厚の差に
よる効果だけではなく、絶縁膜Ａ、Ｂの比誘電率の差に
よれ効果も期待できる。例えば、ＭＩＮコンデンサの絶
縁膜Ｂとして、比誘電率の大きな材料を用いてＭＩＭコ
ンデンサの単位面積当たりの容量値をできる限シ大きく
すると共に、絶縁膜Ａとして、比誘電率の小さな材料を
用いて配線による寄生容量を極力小さくすることが可能
である。Further, the structure of the present invention can be expected to have an effect not only due to the difference in insulating film thickness, but also due to the difference in dielectric constant between the insulating films A and B, as described above. For example, as the insulating film B of a MIN capacitor, a material with a high relative permittivity is used to increase the capacitance value per unit area of the MIM capacitor as much as possible, and as the insulating film A, a material with a small relative permittivity is used. It is possible to minimize the parasitic capacitance due to wiring.
なお１本実施例では、第一層目の絶縁膜としてＳｉＯ２
を、第二層目の絶縁膜としてＳ ｉ ３Ｎ４を用いだが
、他の絶縁膜でもよい。まだ、第一層、第二層が同−組
成の絶縁膜であってもよい。さらに、本実施例では、Ｇ
ａＡｓ ｆ用いた半導体集積回路装置で説明したが、
Ｓｉあるいは他の化合物手導体を用いた集積回路装置で
もよいことは言うまでもない。Note that in this example, SiO2 is used as the first layer insulating film.
Although S i 3N4 is used as the second layer insulating film, other insulating films may be used. However, the first layer and the second layer may be insulating films having the same composition. Furthermore, in this example, G
Although it was explained using a semiconductor integrated circuit device using aAs f,
It goes without saying that an integrated circuit device using Si or other compound conductors may also be used.
（発明の効果）
以上のように本発明では、ＭＩＭ構造のコンデンサを含
み、かつ層間絶縁膜を挾んで上下に電極・配線層を配し
た二層配線構造を有する半導体集積回路装置において、
眉間絶縁膜を二層の積層構造とし、ＭＺＭコンデンサの
絶縁膜上そのいずれか一方の絶縁膜のみで構成すること
によシ、層間絶縁膜ｉ ＭＩＭコンデンサの絶縁膜より
も厚くして配線による寄生容量を極力小さくし、ＭＩＭ
コンデンサの単位面積当たりの容量値を大きくすること
ができ、その実用的効果は大なるものがある。(Effects of the Invention) As described above, the present invention provides a semiconductor integrated circuit device that includes a capacitor with an MIM structure and has a two-layer wiring structure in which electrodes and wiring layers are arranged above and below with an interlayer insulating film in between.
By making the insulating film between the eyebrows a two-layer laminated structure and consisting of only one of the two insulating films on the MZM capacitor's insulating film, the interlayer insulating film is thicker than the MIM capacitor's insulating film to prevent parasitics caused by wiring. Minimize the capacity and use MIM
The capacitance value per unit area of the capacitor can be increased, which has great practical effects.
第１図は、本発明の一実施例におけるＧａＡｓ ＃４体
集積回路装置の断面図、第２図は、従来のにａＡｇ半導
体集積回路装置の断面図である。FIG. 1 is a sectional view of a GaAs #4 integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional aAg semiconductor integrated circuit device.
Claims (1)
層を配した二層配線構造と、金属−絶縁膜−金属構造の
コンデンサとを備え、前記層間絶縁膜が二層の積層構造
を有するとともに、前記コンデンサの絶縁膜が前記層間
絶縁膜の二層のうちのいずれか一方と同一組成からなる
ことを特徴とする半導体集積回路装置。A semiconductor substrate has a two-layer wiring structure in which electrodes and wiring layers are arranged above and below with an interlayer insulating film in between, and a capacitor having a metal-insulating film-metal structure, and the interlayer insulating film has a laminated structure of two layers. A semiconductor integrated circuit device comprising: an insulating film of the capacitor having the same composition as either one of the two layers of the interlayer insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60185682A JPS6246551A (en) | 1985-08-26 | 1985-08-26 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60185682A JPS6246551A (en) | 1985-08-26 | 1985-08-26 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6246551A true JPS6246551A (en) | 1987-02-28 |
Family
ID=16175023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60185682A Pending JPS6246551A (en) | 1985-08-26 | 1985-08-26 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6246551A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02226755A (en) * | 1989-02-28 | 1990-09-10 | Nec Corp | Semiconductor device |
| US5162258A (en) * | 1988-10-17 | 1992-11-10 | Lemnios Zachary J | Three metal personalization of application specific monolithic microwave integrated circuit |
| US6420739B1 (en) | 1998-05-19 | 2002-07-16 | Murata Manufacturing Co., Ltd. | GaAs semiconductor device having a capacitor |
| US6476427B2 (en) | 2000-02-08 | 2002-11-05 | Fujitsu Quantum Devices Limited | Microwave monolithic integrated circuit and fabrication process thereof |
-
1985
- 1985-08-26 JP JP60185682A patent/JPS6246551A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5162258A (en) * | 1988-10-17 | 1992-11-10 | Lemnios Zachary J | Three metal personalization of application specific monolithic microwave integrated circuit |
| JPH02226755A (en) * | 1989-02-28 | 1990-09-10 | Nec Corp | Semiconductor device |
| US6420739B1 (en) | 1998-05-19 | 2002-07-16 | Murata Manufacturing Co., Ltd. | GaAs semiconductor device having a capacitor |
| US6476427B2 (en) | 2000-02-08 | 2002-11-05 | Fujitsu Quantum Devices Limited | Microwave monolithic integrated circuit and fabrication process thereof |
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