JPS6245064A - Semiconductor element - Google Patents
Semiconductor elementInfo
- Publication number
- JPS6245064A JPS6245064A JP18497685A JP18497685A JPS6245064A JP S6245064 A JPS6245064 A JP S6245064A JP 18497685 A JP18497685 A JP 18497685A JP 18497685 A JP18497685 A JP 18497685A JP S6245064 A JPS6245064 A JP S6245064A
- Authority
- JP
- Japan
- Prior art keywords
- inas
- gasb
- layers
- hetero junction
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 230000005684 electric field Effects 0.000 claims abstract description 15
- 229910005542 GaSb Inorganic materials 0.000 abstract description 35
- 229910000673 Indium arsenide Inorganic materials 0.000 abstract description 23
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 abstract description 22
- 239000004047 hole gas Substances 0.000 abstract description 7
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 6
- 125000005842 heteroatom Chemical group 0.000 abstract 5
- 239000002184 metal Substances 0.000 abstract 1
- 230000007704 transition Effects 0.000 description 8
- 238000000034 method Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 241000700560 Molluscum contagiosum virus Species 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 229910052752 metalloid Inorganic materials 0.000 description 1
- 150000002738 metalloids Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高速動作が要求されるスイッチング素子とし
て用いて最適な半導体素子に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device that is optimal for use as a switching device that requires high-speed operation.
本発明は、半導体素子において、第１の半導体層と、そ
の価電子帯端のエネルギーＥｖが上記第１の半導体層の
伝導帯端のエネルギーＥＣよりも高い第２の半導体層と
の少なくとも２層から成るヘテロ接合を具備させ、上記
ヘテロ接合界面に垂直な方向に電圧を印加した状態で上
記ヘテロ接合界面に平行な方向に電界を印加することに
より上記ヘテロ接合界面に垂直な方向に電流を流すよう
にすることによって、第１及び第２の半導体層が上記電
界の印加により極めて短時間で半金属に相転移した状態
でヘテロ接合界面に垂直な方向に電流を流すことを可能
にし、これにより高速動作を可能にすると共に、大電流
を流すことを可能にしたものである。The present invention provides a semiconductor device that includes at least two layers including a first semiconductor layer and a second semiconductor layer whose valence band edge energy Ev is higher than the conduction band edge energy EC of the first semiconductor layer. A current is caused to flow in a direction perpendicular to the heterojunction interface by applying an electric field in a direction parallel to the heterojunction interface while applying a voltage in a direction perpendicular to the heterojunction interface. By doing so, it is possible to flow a current in a direction perpendicular to the heterojunction interface in a state in which the first and second semiconductor layers undergo a phase transition to a semimetal in an extremely short period of time by applying the above-mentioned electric field. This enables high-speed operation and allows large currents to flow.
近年、超高速素子としてヘテロ接合バイポーラトランジ
スタ（ｌｌｅｔｅｒｏｊｕｎｃｔｉｏｎ Ｂｉｐｏｌａ
ｒ Ｔｒａｎｓｉｓ−ｔｏｒ、 ＨＢＴ）が知られてい
るが、研究が進むにつれて次第にその動作速度の限界が
明らかになってきた。これは、ＨＢＴを例えばマイクロ
波素子やスイッチング素子として用いる場合、その動作
速度は電子がエミッタからコレクタへ走行するのに要す
る時間よりもむしろエミ・ノターベー入間及びベース−
コレクタ間のＲＣ時定数で決められてしまうためである
。In recent years, heterojunction bipolar transistors have been developed as ultrahigh-speed devices.
(Transistor, HBT) is known, but as research progresses, the limits of its operating speed gradually become clear. This means that when an HBT is used, for example, as a microwave device or a switching device, its operating speed is determined by the time required for electrons to travel from the emitter to the collector, rather than the time required for electrons to travel from emitter to collector.
This is because it is determined by the RC time constant between the collectors.
このＲＣ時定数を小さくするための方法としてベースの
不純物濃度及び厚さやエミ・ツタ及びコレクタの不純物
濃度を最適化する方法があるが、これによっても限界が
ある。すなわち、例えばベース抵抗を低くするためにベ
ース不純物濃度を高くするとＨＢＴの特性が劣化したり
、ベースを厚くすると電子のベース走行時間が大きくな
ったり、コレクタ容量を小さくするためにコレクタ不純
物濃度を下げるとコレクタの空乏層の幅が大きくなり、
この結果コレクタ走行時間が大きくなったりしてしまう
ためである。As a method for reducing the RC time constant, there is a method of optimizing the impurity concentration and thickness of the base and the impurity concentration of the emitter/vine and collector, but this method also has its limits. That is, for example, if the base impurity concentration is increased to lower the base resistance, the characteristics of the HBT will deteriorate, if the base is made thicker, the base transit time of electrons will increase, or if the collector impurity concentration is lowered to decrease the collector capacitance. and the width of the collector depletion layer increases,
This is because the collector running time becomes longer as a result.
本発明は、従来技術が有する上述のような問題を回避し
た、従来とは動作原理が全く異なる極めて新規な半導体
素子を提供することを目的とする。An object of the present invention is to provide an extremely novel semiconductor device that avoids the above-mentioned problems of the prior art and has a completely different operating principle from the prior art.
本発明に係る半導体素子は、第１の半導体層（例えばＩ
ｎＡｓ層１）と、その価電子帯端のエネルギーＥｖが上
記第１の半導体層の伝導帯端のエネルギーＥＣよりも高
い第２の半導体層（例えばＧａＳｂ層２）との少なくと
も２層から成るヘテロ接合を具備し、上記ヘテロ接合界
面に垂直な方向に電圧を印加した状態で上記ヘテロ接合
界面に平行な方向に電界を印加することにより上記ヘテ
ロ接合界面に垂直な方向に電流を流すようにしている。The semiconductor device according to the present invention has a first semiconductor layer (for example, I
A heterostructure consisting of at least two layers: an nAs layer 1) and a second semiconductor layer (for example, a GaSb layer 2) whose valence band edge energy Ev is higher than the conduction band edge energy EC of the first semiconductor layer. A current is caused to flow in a direction perpendicular to the heterojunction interface by applying an electric field in a direction parallel to the heterojunction interface while applying a voltage in a direction perpendicular to the heterojunction interface. There is.
このように構成することによって、ヘテロ接合界面に平
行な方向に印加された電界によって第１及び第２の半導
体層が半金属に相転移した状態でヘテロ接合界面に垂直
な方向に電流を流すことができる。With this configuration, a current can be caused to flow in a direction perpendicular to the heterojunction interface while the first and second semiconductor layers undergo a phase transition to a semimetal due to an electric field applied in a direction parallel to the heterojunction interface. I can do it.
以下本発明に係る半導体素子をＩｎＡｓ−ＧａＳｂ超格
子素子に適用した一実施例につき図面を参照しながら説
明する。An embodiment in which a semiconductor device according to the present invention is applied to an InAs-GaSb superlattice device will be described below with reference to the drawings.
第１図に示すように、本実施例によるＩｎＡｓ−ＧａＳ
ｂ超格子素子においては、それぞれ例えば膜厚４００人
のＩｎＡｓ層１及びＧａＳｂ層２が交互に多層積層され
て超格子構造が形成されている。そしてこれらのＩｎＡ
ｓ層１及びＧａＳｂ層２間にヘテロ接合３が形成されて
いる。なおこれらのＩｎＡｓ層１及びＧａＳｂ層２は、
数１０人オーダーで膜厚制御可能なＭＢＥ法、ＭＯＣＶ
Ｄ法等により形成することが可能である。As shown in FIG. 1, InAs-GaS according to this embodiment
In the b superlattice element, a superlattice structure is formed by alternately stacking InAs layers 1 and GaSb layers 2, each having a thickness of 400, for example. and these InA
A heterojunction 3 is formed between the s layer 1 and the GaSb layer 2. Note that these InAs layer 1 and GaSb layer 2 are
MBE method, MOCV that allows film thickness to be controlled on the order of several dozen people
It can be formed by the D method or the like.
また最上層及び最下層のＩｎＡｓ層１には電極４．５が
それぞれ形成されていると共に、これらのＩｎＡｓ層１
及びＧａＳｂ層２の両端面には電極６．７がそれぞれ形
成されている。なおＩｎＡｓ及びＧａＳｂの格子定数は
それぞれ６．０５８人及び６．０９５人であるので、Ｉ
ｎＡｓ層１とＧａＳｂ層２との格子整合は良好であり、
従ってヘテロ各接合３は極めて良好である。In addition, electrodes 4.5 are formed on the top and bottom InAs layers 1, respectively, and these InAs layers 1
Electrodes 6.7 are formed on both end faces of the GaSb layer 2. Note that the lattice constants of InAs and GaSb are 6.058 and 6.095, respectively, so I
The lattice matching between the nAs layer 1 and the GaSb layer 2 is good,
Therefore, each heterojunction 3 is extremely good.
第２図に本実施例で用いるＩｎＡｓ及びＧａＳｂのエネ
ルギー帯構造を比較して示す。この第２図から明らかな
ように、Ｉ ｎＡｓの伝導帯端ＥｃｔとＧａＳｂの伝導
帯端Ｅｃ２とのエネルギー差ΔＥＣがＧａＳｂのエネル
ギーギャップよりも大きいため、ＩｎＡｓの伝導帯端Ｅ
ｅｌがＧａＳｂの価電子帯端ＥｖｚよりもＥｓ （〜
０．１４ｅＶ）だけ下方に位置している。従って本実施
例によるＩｎＡｓ−ＧａＳｂ超格子素子のエネルギー帯
構造は第３図に示すようになり、各ヘテロ接合界面にお
いてはＩｎＡｓ側に移動度μ。が〜１０６ｃ＋ｄ／Ｖｓ
と極めて高い二次元電子ガス８が形成され、ＧａＳｂ側
には二次元正孔ガス９が形成されている。なおこの第３
図に示す状態ではヘテロ接合界面に垂直な方向、すなわ
ち電極４．５間に電流は流れないと考えられる。FIG. 2 shows a comparison of the energy band structures of InAs and GaSb used in this example. As is clear from FIG. 2, the energy difference ΔEC between the conduction band edge Ect of InAs and the conduction band edge Ec2 of GaSb is larger than the energy gap of GaSb.
Es (~
0.14 eV). Therefore, the energy band structure of the InAs-GaSb superlattice element according to this example is as shown in FIG. 3, with a mobility μ on the InAs side at each heterojunction interface. ~106c+d/Vs
A two-dimensional electron gas 8 with an extremely high concentration is formed, and a two-dimensional hole gas 9 is formed on the GaSb side. Note that this third
In the state shown in the figure, it is considered that no current flows in the direction perpendicular to the heterojunction interface, that is, between the electrodes 4.5.
次に上−述のように構成された本実施例によるＩｎＡｓ
−ＧａＳｂ超格子素子の動作原理につき説明する。Next, the InAs according to this embodiment configured as described above
- The operating principle of the GaSb superlattice element will be explained.
まず第１図の電極４．５間に電圧を印加した状態で電極
６．７間に電圧を印加することにより各ヘテロ接合界面
に平行な方向に電界を印加して、第３図に示す二次元電
子ガス８及び二次元正孔ガス９をヘテロ接合界面に平行
な方向に加速して加熱する。この時、二次元電子ガス８
の電子及び二次元正孔ガス９の正孔の平均エネルギーは
増大してホ、ツトな状態となる結果、二次元電子ガス８
からΔＥｅを越えて電子がＧａＳｂ層２に注入されてそ
の伝導帯にたまると共に、二次元正孔ガス９から正孔が
ＩｎＡｓ層１に注入されてその価電子帯にたまる。この
結果、ＧａＳｂ及びＩｎＡｓの伝導帯及び価電子帯の曲
率が小さくなって、ＩｎＡｓ −ＧａＳｂ超格子は第４
図に示すように全てのＩｎＡｓ層１及びＧａＳｂ層２に
亘る電子のサブバンドＥ１及び重い正孔の準位ＨＨ＋が
存在する半金属に相転移する。この半金属に相転移した
時に、電極４．５間に印加されている電圧により上記サ
ブバンドＥ１を通してこれらの電極４．５間に電子が流
れ、従って電流が流れる。First, an electric field is applied in a direction parallel to each heterojunction interface by applying a voltage between electrodes 6 and 7 while applying a voltage between electrodes 4 and 5 in FIG. The dimensional electron gas 8 and the two-dimensional hole gas 9 are accelerated and heated in a direction parallel to the heterojunction interface. At this time, two-dimensional electron gas 8
The average energy of the electrons and holes in the two-dimensional hole gas 9 increases and becomes a hot state, resulting in the two-dimensional electron gas 8
Electrons are injected into the GaSb layer 2 beyond ΔEe from ΔEe and accumulate in its conduction band, and holes from the two-dimensional hole gas 9 are injected into the InAs layer 1 and accumulate in its valence band. As a result, the curvature of the conduction band and valence band of GaSb and InAs becomes smaller, and the InAs-GaSb superlattice becomes
As shown in the figure, the electron subband E1 and the heavy hole level HH+ across all the InAs layers 1 and GaSb layers 2 undergo a phase transition to a semimetal. When the phase transition to semimetal occurs, electrons flow between the electrodes 4.5 through the subband E1 due to the voltage applied between the electrodes 4.5, and thus a current flows.
なお第４図に示す半金属の状態は、ＧａＳｂ層２の伝導
帯に電子が、またＩｎＡｓＪｔｉｌの価電子帯に正孔が
たまっている間だけ保たれるが、この時間は素子を低温
に保持することによって長くすることができる。The semimetal state shown in Figure 4 is maintained only while electrons are accumulated in the conduction band of the GaSb layer 2 and holes are accumulated in the valence band of InAsJtil, but during this time the element is kept at a low temperature. You can make it longer by doing this.
次に本実施例によるＩｎＡｓ −ＧａＳｂ超格子素子の
動作速度につき説明する。このために二次元電子ガス８
の電子かヘテロ接合界面に平行な方向に加速されてホッ
トな状態になってΔＥｃを越えるのに要する時間を計算
すると次のようになる。Next, the operating speed of the InAs-GaSb superlattice element according to this example will be explained. For this purpose, two-dimensional electron gas 8
Calculating the time required for an electron to be accelerated in a direction parallel to the heterojunction interface, become hot and exceed ΔEc, is as follows.
電子は加速されている間散乱されないと仮定し、電子の
電荷、質量、速度をそれぞれｅ、ｍ、ｖ、電極６．７間
に印加される電界をＥｃ電子がΔＥｃを越えるのに要す
る時間をむで表せば、ｔ
−ｍ ｖ ” −ｅΔＥ ｃ−−−−−■が成立する。Assuming that the electron is not scattered while being accelerated, let the charge, mass, and velocity of the electron be e, m, and v, respectively, and the electric field applied between the electrodes 6.7 and Ec be the time required for the electron to exceed ΔEc. Expressed in terms of water, t −m v ” −eΔE c−−−−−■ holds true.
今、仮にΔＥｃ＝ ０．７Ｖ、ＩｎＡｓ中の電子の有効
質量ｍ” −０，０２７ｍとすると、ΔＥＣを越えるた
めに必要な■は０式より、
−３ＸＩＱ８ｃｍ／ｓ
となる。また例えばＥ＝ １ ｋＶ／ｃｍ （電極６．
７間の距離が１μｍである時にｏ、ｉｖを印加した場合
に相当する）とすると０式より、
Ｅ
Ｏ，０２７Ｘ ９ Ｘｌ０−２８Ｘ ３ Ｘ １０’１
．６Ｘ１０−Ｉ２Ｘ Ｌ Ｘ １０３＝ ４．６Ｘ１０
−１２９
＝ ４．６ ｐｓ
が得られる。すなわち、電子がΔＥｃを越えるのに要す
る時間は約５ ｐｓであることがわかる。さらニＥ＝
１０ ｋＶ／ｃｍとすれば、ｔ ＝ ０．５ ｐｓが得
られることも上述と同様な計算をすることにより明らか
である。Now, if we assume that ΔEc = 0.7V and the effective mass of electrons in InAs m'' -0,027m, then the amount of ■ required to exceed ΔEC is -3XIQ8cm/s from equation 0.For example, E = 1 kV/cm (electrode 6.
Corresponding to the case where o and iv are applied when the distance between
．． 6X10-I2X L X 103= 4.6X10
-129 = 4.6 ps is obtained. That is, it can be seen that the time required for the electron to exceed ΔEc is about 5 ps. Sarani E=
It is also clear from calculations similar to those described above that if the voltage is 10 kV/cm, t = 0.5 ps can be obtained.
次にホットになった電子がどれ位の量だけＧａＳｂ層２
に注入されるとバンドがどの程度へこむかを計算してお
く。Next, how much of the hot electrons are in the GaSb layer 2?
Calculate how much the band will dent when it is injected.
まず電子が一様に分布すると仮定する。ヘテロ接合界面
からＧａＳｂ層２の内部に向かって測った距離をＸ、単
位体積当たりの電子の個数をＮ、 ＧａＳｂの誘電率を
ε、バンドのへこみ量をφで表せば、が成立する。この
■式において例えばＸ＝１００人とすると、ε＝ Ｉ
Ｘ １０−１２Ｆ／ｃｍであるから、Ｎ＝１０′９／ｃ
ｆｆｉ３の場合にはφ＝ ０．８Ｖとなり、Ｎ ＝１０
”／ ｃｍ”の場合にはφ＝０．０８■トナル。First, assume that the electrons are uniformly distributed. If the distance measured from the heterojunction interface toward the inside of the GaSb layer 2 is represented by X, the number of electrons per unit volume is represented by N, the dielectric constant of GaSb is represented by ε, and the amount of band depression is represented by φ, then the following holds true. In this formula, if X = 100 people, ε = I
Since X 10-12F/cm, N=10'9/c
In the case of ffi3, φ = 0.8V, and N = 10
In the case of "/cm", φ=0.08■tonal.
上述のΔＥｃを越えるのに要する時間の考察かられかる
ように、本実施例によるＩｎＡｓ −ＧａＳｂ超格子素
子は、電極６．７間に印加する電界を１ ｋＶ／ｃｍ以
上とすればこの電界を印加してから５ｐｓ以内の極めて
短い時間内に半金属に相転移して電極４．５間に電流が
流れ、従って高速のスイッチング動作が可能である。As can be seen from the consideration of the time required to exceed ΔEc mentioned above, the InAs-GaSb superlattice element according to this example can suppress this electric field by setting the electric field between the electrodes 6 and 7 to 1 kV/cm or more. A phase transition to a semimetal occurs within an extremely short time of 5 ps after application, and a current flows between the electrodes 4.5, thus enabling high-speed switching operation.
このように、上述の実施例によれば、第２図に示すよう
なエネルギー帯構造を有するＩｎＡｓ層１及びＧａＳｂ
層２を交互に積層する。ことにより形成されたＩｎＡｓ
−ＧａＳｂ超格子のヘテロ接合界面に垂直な方向に電
極４．５を用いて電圧を印加した状態で、このヘテロ接
合界面に平行な方向に電界を印加することにより超格子
を半金属状態に転移させ、この半金属状態でヘテロ接合
界面に垂直な方向に電流を流しているので、上述のよう
に高速のスイッチング動作が可能であるのみならず、抵
抗の低い半金属状態で電流が流れるので大電流を流すこ
とが可能である。しかも電流４．５間に小さな電圧を印
加するだけで大電流を流すことが可能である。As described above, according to the above-described embodiment, the InAs layer 1 and the GaSb layer 1 having the energy band structure as shown in FIG.
Layers 2 are stacked alternately. InAs formed by
-The superlattice is transformed into a semimetallic state by applying an electric field in a direction parallel to the heterojunction interface while applying a voltage using the electrode 4.5 in a direction perpendicular to the heterojunction interface of the GaSb superlattice. In this semimetallic state, a current is passed in a direction perpendicular to the heterojunction interface, which not only enables high-speed switching operation as described above, but also allows a large current to flow in a semimetallic state with low resistance. It is possible to conduct current. Moreover, it is possible to flow a large current by simply applying a small voltage between the currents.
以上本発明の一実施例につき説明したが、本発明は上述
の実施例に限定されるものではなく、本発明の技術的思
想に基づく各種の変形が可能である。例えば上述の実施
例におけるＩｎＡｓ層１及びＧａ５ｂ層２の層数や厚さ
は必要に応じて選定し得るものである。しかしこれらの
ＩｎＡｓ層１及びＧａＳｂＮ２の厚さが約１２０人にな
ると超格子が半導体から半金属に相転移することが知ら
れているので、この値から離れた厚さとする必要がある
。これらの厚さとしては、上述の１２０人よりも充分に
大きい３００〜５００人の範囲の厚さが好ましい。Although one embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various modifications can be made based on the technical idea of the present invention. For example, the number and thickness of the InAs layer 1 and the Ga5b layer 2 in the above embodiment can be selected as required. However, it is known that when the thickness of the InAs layer 1 and the GaSbN2 becomes about 120 nm, the superlattice undergoes a phase transition from a semiconductor to a metalloid, so it is necessary to set the thickness apart from this value. The thickness is preferably in the range of 300 to 500 people, which is sufficiently larger than the above-mentioned 120 people.
また上述の実施例においては、ＩｎＡｓ −ＧａＳｂ超
格子で半導体素子を構成したが、第２図に示すと同様な
エネルギー帯構造の関係を有する２種類の半導体層、す
なわち一方の価電子帯端Ｅｖが他方の伝導帯端Ｅｃより
も高い２種類の半導体層により構成されるその他の超格
子によって半導体素子を構成することも可能である。Furthermore, in the above-mentioned embodiment, the semiconductor element was constructed with an InAs-GaSb superlattice, but as shown in FIG. It is also possible to construct a semiconductor element using other superlattices constructed of two types of semiconductor layers in which conduction band edge Ec is higher than the other conduction band edge Ec.
本発明によれば、ヘテロ接合界面に平行な方向に印加さ
れる電界によって第１及び第２の半導体層を極めて短時
間で半金属に相転移させた状態でヘテロ接合界面に垂直
な方向に電流を流すことができるので、高速動作が可能
であるのみならず、低電圧で大電流を流すことが可能で
ある。According to the present invention, an electric field applied in a direction parallel to the heterojunction interface causes the first and second semiconductor layers to undergo a phase transition to a semimetal in an extremely short period of time, and a current is applied in a direction perpendicular to the heterojunction interface. , which not only allows high-speed operation but also allows large current to flow at low voltage.
第１図は本発明の一実施例によるＩｎＡｓ −ＧａＳｂ
超格子素子を示す断面図、第２図はＩｎＡｓ及びＧａＳ
ｂのエネルギー帯構造を比較して示す模式図、第３図は
第１図に示すＩｎＡｓ −ＧａＳｂ超格子素子において
ヘテロ接合界面に平行な方向に電界を印加してぃない半
導体状態におけるＩｎＡｓ −ＧａＳｂ超格子のエネル
ギー帯構造を示す模式図、第４図は第１図に示すＩｎＡ
ｓ −ＧａＳｂ超格子素子においてヘテロ接合界面に平
行な方向に電界を印加して半金属に相転移させた状態に
おけるＩｎＡｓ −ＧａＳｂ超格子のエネルギー帯構造
を示す模式図である。
なお、図面に用いた符号において、
１−−−−−−−−−−−−−−・・・−ＩｎＡｓ層２
−・−−＝−−−−−−−−−−Ｇ ａ Ｓ ｂ Ｎ３
・・−−一−−−−・・−・−ヘテロ接合４．５．６．
７−・−・・−・電極
８−・−−−一−−−−・−・・−・・−二次元電子ガ
ス９−・・・−−−−−ｍ−−−・−・−二次元正孔ガ
スである。FIG. 1 shows InAs-GaSb according to an embodiment of the present invention.
A cross-sectional view showing a superlattice element, Figure 2 shows InAs and GaS
Fig. 3 is a schematic diagram showing a comparison of the energy band structures of the InAs - GaSb superlattice shown in Fig. 1 in a semiconductor state in which no electric field is applied in the direction parallel to the heterojunction interface. A schematic diagram showing the energy band structure of the superlattice, Figure 4 is the InA shown in Figure 1.
FIG. 2 is a schematic diagram showing the energy band structure of an InAs-GaSb superlattice in a state where an electric field is applied in a direction parallel to a heterojunction interface in an s-GaSb superlattice element to cause a phase transition to a semimetal. In addition, in the symbols used in the drawings, 1-------------InAs layer 2
−・−−=−−−−−−−−−G a S b N3
・・−−1−−−−・・−・−Heterojunction 4.5.6.
7-・-・・-・Electrode 8-・−-−1−−−・−・・−・・−Two-dimensional electron gas 9−・・−−−−−m−−−・−・− It is a two-dimensional hole gas.
Claims (1)
上記第１の半導体層の伝導帯端のエネルギーＥｃよりも
高い第２の半導体層との少なくとも２層から成るヘテロ
接合を具備し、 上記ヘテロ接合界面に垂直な方向に電圧を印加した状態
で上記ヘテロ接合界面に平行な方向に電界を印加するこ
とにより上記ヘテロ接合界面に垂直な方向に電流を流す
ようにした半導体素子。[Claims] Consists of at least two layers: a first semiconductor layer and a second semiconductor layer whose valence band edge energy Ev is higher than the conduction band edge energy Ec of the first semiconductor layer. A heterojunction is provided, and a current is caused to flow in a direction perpendicular to the heterojunction interface by applying an electric field in a direction parallel to the heterojunction interface while applying a voltage in a direction perpendicular to the heterojunction interface. semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18497685A JPS6245064A (en) | 1985-08-22 | 1985-08-22 | Semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18497685A JPS6245064A (en) | 1985-08-22 | 1985-08-22 | Semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6245064A true JPS6245064A (en) | 1987-02-27 |
Family
ID=16162632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18497685A Pending JPS6245064A (en) | 1985-08-22 | 1985-08-22 | Semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6245064A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0322773A2 (en) * | 1987-12-26 | 1989-07-05 | Fujitsu Limited | Semiconductor device with semimetal |
| US5221849A (en) * | 1992-06-16 | 1993-06-22 | Motorola, Inc. | Semiconductor device with active quantum well gate |
| WO1994002961A1 (en) * | 1992-07-17 | 1994-02-03 | Golding Terry D | Optical switches and detectors utilizing indirect narrow-gap superlattices as the optical material |
| US5326985A (en) * | 1992-09-28 | 1994-07-05 | Motorola, Inc. | Bipolar doped semiconductor structure and method for making |
| US5410160A (en) * | 1992-06-08 | 1995-04-25 | Motorola, Inc. | Interband tunneling field effect transistor |
| US5412224A (en) * | 1992-06-08 | 1995-05-02 | Motorola, Inc. | Field effect transistor with non-linear transfer characteristic |
| US5449561A (en) * | 1992-07-17 | 1995-09-12 | University Of Houston | Semimetal-semiconductor heterostructures and multilayers |
-
1985
- 1985-08-22 JP JP18497685A patent/JPS6245064A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0322773A2 (en) * | 1987-12-26 | 1989-07-05 | Fujitsu Limited | Semiconductor device with semimetal |
| US5410160A (en) * | 1992-06-08 | 1995-04-25 | Motorola, Inc. | Interband tunneling field effect transistor |
| US5412224A (en) * | 1992-06-08 | 1995-05-02 | Motorola, Inc. | Field effect transistor with non-linear transfer characteristic |
| US5221849A (en) * | 1992-06-16 | 1993-06-22 | Motorola, Inc. | Semiconductor device with active quantum well gate |
| WO1994002961A1 (en) * | 1992-07-17 | 1994-02-03 | Golding Terry D | Optical switches and detectors utilizing indirect narrow-gap superlattices as the optical material |
| US5449561A (en) * | 1992-07-17 | 1995-09-12 | University Of Houston | Semimetal-semiconductor heterostructures and multilayers |
| US5477377A (en) * | 1992-07-17 | 1995-12-19 | University Of Houston | Optical switches and detectors utilizing indirect narrow-gap superlattices as the optical materials |
| US5686351A (en) * | 1992-07-17 | 1997-11-11 | The University Of Houston | Semimetal-semiconductor heterostructures and multilayers |
| US5326985A (en) * | 1992-09-28 | 1994-07-05 | Motorola, Inc. | Bipolar doped semiconductor structure and method for making |
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