JPS6244442U - - Google Patents

Info

Publication number
JPS6244442U
JPS6244442U JP1985136046U JP13604685U JPS6244442U JP S6244442 U JPS6244442 U JP S6244442U JP 1985136046 U JP1985136046 U JP 1985136046U JP 13604685 U JP13604685 U JP 13604685U JP S6244442 U JPS6244442 U JP S6244442U
Authority
JP
Japan
Prior art keywords
solid
image sensor
state image
substrate
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985136046U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985136046U priority Critical patent/JPS6244442U/ja
Publication of JPS6244442U publication Critical patent/JPS6244442U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案に係るハイブリツド集積回路の
一実施例の構造を示す斜視図、第２図は本考案に
係るハイブリツド集積回路の一実施例の組立て斜
視図、第３図は従来のハイブリツド集積回路の構
造を示す斜視図、第４図は本考案に係るハイブリ
ツド集積回路と従来のハイブリツド集積回路の厚
さを比較するための各々の側面図を示し、同図Ａ
は本考案に係るハイブリツド集積回路の側面図、
同図Ｂは従来のハイブリツド集積回路の側面図で
ある。 ２……ハイブリツド集積回路、１０……基板、
１２……固体撮像素子、１４，２２……ボンデイ
ングパツド、２０……凹部、３０……ボンデイン
グワイヤ。 FIG. 1 is a perspective view showing the structure of an embodiment of a hybrid integrated circuit according to the present invention, FIG. 2 is an assembled perspective view of an embodiment of the hybrid integrated circuit according to the present invention, and FIG. 3 is a conventional hybrid integrated circuit. FIG. 4 is a perspective view showing the structure of the circuit, and FIG. 4 is a side view for comparing the thickness of the hybrid integrated circuit according to the present invention and a conventional hybrid integrated circuit.
is a side view of the hybrid integrated circuit according to the present invention,
Figure B is a side view of a conventional hybrid integrated circuit. 2...hybrid integrated circuit, 10...substrate,
12... Solid-state imaging device, 14, 22... Bonding pad, 20... Recessed portion, 30... Bonding wire.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ＣＣＤ等の固体撮像素子を含んで構成されるハ
イブリツド集積回路において、基板に前記固体撮
像素子を収容する凹部を形成すると共に該凹部は
該固体撮像素子を収容した際に固体撮像素子表面
と基板表面とが略同一面状になるように形成され
、前記基板と固体撮像素子とは前記凹部に固体撮
像素子の収容状態で、固体撮像素子及び基板の表
面に各々設けられたボンデイングパツドをテープ
状のボンデイングワイヤで接合されていることを
特徴とするハイブリツド集積回路。 In a hybrid integrated circuit including a solid-state image sensor such as a CCD, a recess for accommodating the solid-state image sensor is formed in the substrate, and when the solid-state image sensor is accommodated, the recess is formed between the surface of the solid-state image sensor and the surface of the substrate. The substrate and the solid-state image sensor are formed so that they are substantially flush with each other, and the bonding pads provided on the surfaces of the solid-state image sensor and the substrate are bonded in a tape-like manner, with the solid-state image sensor accommodated in the recess. A hybrid integrated circuit characterized in that it is bonded with bonding wire.
JP1985136046U 1985-09-04 1985-09-04 Pending JPS6244442U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985136046U JPS6244442U (en) 1985-09-04 1985-09-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985136046U JPS6244442U (en) 1985-09-04 1985-09-04

Publications (1)

Publication Number Publication Date
JPS6244442U true JPS6244442U (en) 1987-03-17

Family

ID=31038798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985136046U Pending JPS6244442U (en) 1985-09-04 1985-09-04

Country Status (1)

Country Link
JP (1) JPS6244442U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4911066A (en) * 1972-05-26 1974-01-31
JPS5433660A (en) * 1977-08-22 1979-03-12 Hitachi Ltd Bonding wire

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4911066A (en) * 1972-05-26 1974-01-31
JPS5433660A (en) * 1977-08-22 1979-03-12 Hitachi Ltd Bonding wire

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