JPS6240857B2 - - Google Patents
Info
- Publication number
- JPS6240857B2 JPS6240857B2 JP12090582A JP12090582A JPS6240857B2 JP S6240857 B2 JPS6240857 B2 JP S6240857B2 JP 12090582 A JP12090582 A JP 12090582A JP 12090582 A JP12090582 A JP 12090582A JP S6240857 B2 JPS6240857 B2 JP S6240857B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- substrate
- trench
- semiconductor
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.
従来、集積回路製造の際、各トランジスタ間の
素子分離のため、第１図に示す如くシリコン半導
体基板１（以下基板１と略す）の表面に薄い酸化
膜２、窒化膜３を形成し、その後写真蝕刻技術に
より所望の個所に穴を開け、基板１と同種の不純
物を拡散４する。窒化膜３をマスクにして酸化す
ると、第２図の如く各トランジスタ間のチヤネル
ストツパー６，７と厚い酸化膜領域ができる。こ
の厚い酸化膜形成時、窒化膜の下部へ酸化膜が食
い込むように成長するため、厚い酸化膜領域が広
がり微細なトランジスタ形成、集積回路の集積度
向上および高速用トランジスタ製造の障害となつ
ている。 Conventionally, when manufacturing integrated circuits, a thin oxide film 2 and a nitride film 3 are formed on the surface of a silicon semiconductor substrate 1 (hereinafter referred to as substrate 1), as shown in FIG. 1, in order to isolate each transistor. Holes are made at desired locations by photolithography, and impurities of the same type as the substrate 1 are diffused 4 . When oxidation is performed using the nitride film 3 as a mask, channel stoppers 6 and 7 between each transistor and a thick oxide film region are formed as shown in FIG. When this thick oxide film is formed, the oxide film grows into the bottom of the nitride film, which causes the thick oxide film region to spread and become an obstacle to the formation of fine transistors, the improvement of the degree of integration of integrated circuits, and the manufacture of high-speed transistors. .
次に第３図の如くMOS型集積回路のソース、
ドレインを形成する時、前記チヤンネルストツパ
ー領域６、とソース、ドレイン領域１０，１１，
１２，１３と接触し、即ち高濃度不純物領域が接
触し耐圧の低下、接合容量の増加となり、ICの
高耐圧化、高速化の障害となつている。 Next, as shown in Figure 3, the source of the MOS type integrated circuit,
When forming a drain, the channel stopper region 6, source and drain regions 10, 11,
12 and 13, that is, the high-concentration impurity regions come into contact, resulting in a decrease in breakdown voltage and an increase in junction capacitance, which is an obstacle to increasing the breakdown voltage and speed of the IC.
本発明の目的は、この従来の障害を除いた半導
体装置の製造方法を提供することにある。 An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates this conventional obstacle.
本発明の特徴は、半導体基板表面に薄い酸化膜
と誘電体膜を形成する工程と、写真蝕刻により部
分的にこの基板面を露出する工程とこの露出部の
基板を蝕刻し溝部を設ける工程と、この溝部に基
板と同種の不純物を注入する工程と、この溝部の
み選択的に酸化する工程と、この溝部の酸化膜を
残し基板の誘電体膜と酸化膜を除去する工程と、
この溝部のみ多結晶半導体を他部には基板と同種
不純物の単結晶半導体を同時にエピタキシヤル成
長する工程と、この溝部の多結晶半導体部を酸化
することで溝部を酸化膜で埋める工程を有する半
導体装置の製造方法にある。 The features of the present invention include a step of forming a thin oxide film and a dielectric film on the surface of a semiconductor substrate, a step of partially exposing the substrate surface by photolithography, and a step of etching the exposed portion of the substrate to form a groove. , a step of implanting impurities of the same type as the substrate into this groove portion, a step of selectively oxidizing only this groove portion, a step of removing a dielectric film and an oxide film of the substrate while leaving an oxide film in this groove portion,
A semiconductor product that has a process of epitaxially growing a polycrystalline semiconductor only in this groove and a single crystal semiconductor with the same type of impurity as the substrate in other parts, and a process of filling the groove with an oxide film by oxidizing the polycrystalline semiconductor part of this groove. It is in the manufacturing method of the device.
以下、本発明実施例の第４図から第８図につい
て説明する。第４図の如く基板１４上に酸化膜１
５、窒化膜１６を形成後、ホトレジスト１７を塗
布し写真蝕刻技術により現像する。ホトレジスト
１７をマスクとして窒化膜１６、酸化膜１５を除
去する。基板１４上に溝部１８，１９を設ける
が、この際のマスクはホトレジスト１７、あるい
は窒化膜１６のどちらを使用してもよい。 Hereinafter, FIGS. 4 to 8 of the embodiment of the present invention will be explained. As shown in FIG. 4, an oxide film 1 is formed on the substrate 14.
5. After forming the nitride film 16, a photoresist 17 is applied and developed by photolithography. The nitride film 16 and oxide film 15 are removed using the photoresist 17 as a mask. Grooves 18 and 19 are provided on the substrate 14, and either the photoresist 17 or the nitride film 16 may be used as a mask at this time.
窒化膜１６あるいはホトレジスト１７をマスク
に溝部１８，１９の低部へ基板１４と同種の不純
物をイオン注入する。これがチヤンネルストツパ
ー部２０である。第５図は窒化膜１６をマスクと
し溝部１８，１９の低部、側面を酸化した状態で
ある。次に第５図の窒化膜１６を除去し、酸化膜
１５の全面と酸化膜２２，２３の一部を除去す
る。ここで溝部の酸化膜２２，２３の一部を残す
ことが特徴である。その後基板表面にエピタキシ
ヤル成長を行う。この際第６図に示す如く、酸化
膜のある溝部２４，２５は多結晶半導体２７，２
８が成長し、他部は基板１４と同種の不純物を有
する単結晶半導体１６が成長する。この後全面を
酸化すると溝部のポリシリ２７，２８は単結晶部
より20〜50％酸化速度が早いので、溝部２９，３
０が全て酸化膜となる。この時、多結晶部が酸化
膜へ変わると体積が30％〜40％増加するため第７
図の如く、溝部２９，３０は酸化膜で埋つてしま
う。その後、トランジスタのソース、ドレイン部
を形成すると第８図の如くなるが、チヤンネルス
トツパー部２０，２１とソース、ドレイン領域３
１，３２，３３，３４は接触しないため、ソー
ス、ドレイン領域の接合容量は増さず、また、高
耐圧トランジスタに適する。 Using the nitride film 16 or the photoresist 17 as a mask, ions of impurities of the same type as the substrate 14 are implanted into the lower parts of the grooves 18 and 19. This is the channel stopper section 20. FIG. 5 shows a state in which the bottom and side surfaces of the grooves 18 and 19 are oxidized using the nitride film 16 as a mask. Next, the nitride film 16 shown in FIG. 5 is removed, and the entire surface of the oxide film 15 and part of the oxide films 22 and 23 are removed. The feature here is that a portion of the oxide films 22 and 23 in the groove portions are left. Epitaxial growth is then performed on the substrate surface. At this time, as shown in FIG.
A single crystal semiconductor 16 having the same type of impurity as that of the substrate 14 is grown in the other portion. After that, when the entire surface is oxidized, the oxidation rate of the polysilicon 27 and 28 in the grooves is 20 to 50% faster than that of the single crystal part, so the grooves 29 and 3
All 0's become oxide films. At this time, when the polycrystalline part changes to an oxide film, the volume increases by 30% to 40%, so the seventh
As shown in the figure, the grooves 29 and 30 are filled with an oxide film. After that, when the source and drain parts of the transistor are formed, the result will be as shown in FIG.
Since 1, 32, 33, and 34 are not in contact with each other, the junction capacitance of the source and drain regions does not increase, and is suitable for a high voltage transistor.
更に従来技術による第３図と本発明の第８図を
比較すると、第３図では厚い酸化膜８，９を形成
する際横方向に深さ方向とほぼ同じだけ酸化膜が
成長するのに対し、第８図では厚い酸化膜２０，
２１を形成してもほとんど横方向に酸化膜が広が
らない。従つてトランジスタの微細化、高速化に
対して現状の製法に比し、有利となる。 Furthermore, when comparing FIG. 3 according to the prior art and FIG. 8 according to the present invention, it is found that when forming the thick oxide films 8 and 9 in FIG. , in FIG. 8, the thick oxide film 20,
Even if 21 is formed, the oxide film hardly spreads in the lateral direction. Therefore, this method is more advantageous than the current manufacturing method for miniaturizing and increasing the speed of transistors.
以上MOS型集積回路について述べたがバイポ
ーラ型集積回路の各素子間の誘電体分離へも同様
に適用できることは明らかである。 Although MOS type integrated circuits have been described above, it is clear that the present invention can be similarly applied to dielectric isolation between elements of bipolar type integrated circuits.
第１図、第２図、第３図は各々従来技術の製法
を工程順に示す断面図、第４図、第５図、第６
図、第７図、第８図は各々本発明の実施例の工程
順断面図、である。
なお図において、１……シリコン半導体基板、
２……薄い酸化膜、３……窒化膜、４，５……チ
ヤンネルストツパー用領域、６，７……チヤンネ
ルストツパー用領域、８，９……厚い酸化膜、１
０，１１，１２，１３……ソース、ドレイン領
域、１４……シリコン半導体基板、１５……薄い
酸化膜、１６……窒化膜、１７……ホトレジス
ト、１８，１９……半導体基板上の溝部、２０，
２１……チヤンネルストツパー領域、２２，２
３，２４，２５……溝部の酸化膜、２６……エピ
タキシヤル成長した単結晶半導体部、２７，２８
……溝部へ成長した多結晶半導体部、２９，３０
……溝部の酸化膜、３１，３２，３３，３４……
ソース、ドレイン領域、である。
Figures 1, 2, and 3 are cross-sectional views showing the conventional manufacturing method in order of process, and Figures 4, 5, and 6 are
7, and 8 are sectional views in the order of steps of an embodiment of the present invention. In the figure, 1... silicon semiconductor substrate,
2... Thin oxide film, 3... Nitride film, 4, 5... Channel stopper area, 6, 7... Channel stopper area, 8, 9... Thick oxide film, 1
0, 11, 12, 13... Source, drain region, 14... Silicon semiconductor substrate, 15... Thin oxide film, 16... Nitride film, 17... Photoresist, 18, 19... Groove portion on semiconductor substrate, 20,
21...Channel stopper area, 22,2
3, 24, 25... Oxide film in the trench, 26... Epitaxially grown single crystal semiconductor part, 27, 28
...Polycrystalline semiconductor portion grown into the groove, 29, 30
...Oxide film in the groove, 31, 32, 33, 34...
These are the source and drain regions.
Claims (1)
体膜を形成する工程と、写真蝕刻により部分的に
該基板面を露出する工程と、該露出部の該基板を
蝕刻し溝部を設ける工程と、該溝部に一導電型不
純物を注入する工程と、該溝部のみ選択的に酸化
する工程と、該溝部の酸化膜を残し該基板の誘電
体膜と酸化膜を除去する工程と、該溝部のみ多結
晶半導体を他部には一導電型の単結晶半導体を同
時にエピタキシヤル成長する工程と、該溝部の多
結晶半導体部を酸化することで該溝部を酸化膜で
埋める工程を有することを特徴とする半導体装置
の製造方法。1. A step of forming a thin oxide film and a dielectric film on the surface of a semiconductor substrate of one conductivity type, a step of partially exposing the surface of the substrate by photolithography, and a step of etching the exposed portion of the substrate to form a groove. , a step of implanting one conductivity type impurity into the trench, a step of selectively oxidizing only the trench, a step of removing a dielectric film and an oxide film of the substrate leaving an oxide film in the trench, and a step of removing only the trench. It is characterized by comprising the steps of simultaneously epitaxially growing a polycrystalline semiconductor and a single-crystalline semiconductor of one conductivity type on other parts, and filling the trench with an oxide film by oxidizing the polycrystalline semiconductor part in the trench. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12090582A JPS5911645A (en) | 1982-07-12 | 1982-07-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12090582A JPS5911645A (en) | 1982-07-12 | 1982-07-12 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5911645A JPS5911645A (en) | 1984-01-21 |
| JPS6240857B2 true JPS6240857B2 (en) | 1987-08-31 |
Family
ID=14797895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12090582A Granted JPS5911645A (en) | 1982-07-12 | 1982-07-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5911645A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5008180A (en) * | 1989-04-07 | 1991-04-16 | Eastman Kodak Company | Photographic recording material containing a cyan dye-forming coupler |
| KR960014452B1 (en) * | 1993-12-22 | 1996-10-15 | 금성일렉트론 주식회사 | Method of isolation of a semiconductor device |
| US5438016A (en) * | 1994-03-02 | 1995-08-01 | Micron Semiconductor, Inc. | Method of semiconductor device isolation employing polysilicon layer for field oxide formation |
| US5472904A (en) * | 1994-03-02 | 1995-12-05 | Micron Technology, Inc. | Thermal trench isolation |
| US5753962A (en) * | 1996-09-16 | 1998-05-19 | Micron Technology, Inc. | Texturized polycrystalline silicon to aid field oxide formation |
| KR100444607B1 (en) * | 2002-10-24 | 2004-08-16 | 주식회사 하이닉스반도체 | Method of forming an isolation layer in a semiconductor device |
-
1982
- 1982-07-12 JP JP12090582A patent/JPS5911645A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5911645A (en) | 1984-01-21 |
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