JPS6240847U - - Google Patents

Info

Publication number
JPS6240847U
JPS6240847U JP13112085U JP13112085U JPS6240847U JP S6240847 U JPS6240847 U JP S6240847U JP 13112085 U JP13112085 U JP 13112085U JP 13112085 U JP13112085 U JP 13112085U JP S6240847 U JPS6240847 U JP S6240847U
Authority
JP
Japan
Prior art keywords
photoelectric conversion
driving
output signal
input
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13112085U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13112085U priority Critical patent/JPS6240847U/ja
Publication of JPS6240847U publication Critical patent/JPS6240847U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Facsimiles In General (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第1図は本考案の一実施例の斜視図、第2図及
び第3図はそれぞれ従来の密着形センサの第1及
び第2の例の斜視図である。 1……基板、2……光電変換素子群、3……個
別配線、4,4′……駆動用ICチツプ、5……
ボンデイングワイヤ、6……駆動用IC接続配線
層、7……入出力用信号配線端子、8……入出力
用信号配線。

Claims (1)

    【実用新案登録請求の範囲】
  1. 光電変換素子を一列に複数個配置した光電変換
    素子群と、該光電変換素子群を順次駆動させるた
    めの複数個の駆動用ICチツプを同一基板上に搭
    載した密着形イメージセンサにおいて、前記駆動
    用ICチツプ内部の入出力用信号配線をクロスオ
    ーバーさせ、入出力用信号配線端子を左右対称の
    2組となるように配置したことを特徴とする密着
    形イメージセンサ。
JP13112085U 1985-08-27 1985-08-27 Pending JPS6240847U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13112085U JPS6240847U (ja) 1985-08-27 1985-08-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13112085U JPS6240847U (ja) 1985-08-27 1985-08-27

Publications (1)

Publication Number Publication Date
JPS6240847U true JPS6240847U (ja) 1987-03-11

Family

ID=31029266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13112085U Pending JPS6240847U (ja) 1985-08-27 1985-08-27

Country Status (1)

Country Link
JP (1) JPS6240847U (ja)

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