JPS623978Y2 - - Google Patents
Info
- Publication number
- JPS623978Y2 JPS623978Y2 JP1978160912U JP16091278U JPS623978Y2 JP S623978 Y2 JPS623978 Y2 JP S623978Y2 JP 1978160912 U JP1978160912 U JP 1978160912U JP 16091278 U JP16091278 U JP 16091278U JP S623978 Y2 JPS623978 Y2 JP S623978Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- frequency
- luminance signal
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000003111 delayed effect Effects 0.000 claims description 14
- 238000006243 chemical reaction Methods 0.000 claims description 9
- 238000000926 separation method Methods 0.000 claims description 5
- 230000001934 delay Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 12
- 230000010355 oscillation Effects 0.000 description 6
- 238000001514 detection method Methods 0.000 description 5
- 230000003321 amplification Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Landscapes
- Television Signal Processing For Recording (AREA)
Description
【考案の詳細な説明】
本考案は水平同期周期に関して連続する再生信
号を合成するスローモーシヨン再生回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a slow motion reproduction circuit that synthesizes successive reproduction signals with respect to a horizontal synchronization period.
記録トラツクを所定回数ずつ再生走査し乍らス
ローモーシヨン再生画像を得るように構成したビ
デオテープレコーダは走査の途中でトラツクを跨
いで再生走査を為すことがある。よつて隣接トラ
ツクが互に水平同期信号をトラツクの幅方向に並
べて記録しない限りトラツクを跨いで走査をした
瞬間に水平同期周期が乱れる。そこで従来装置の
多くはトラツクの幅方向に水平同期信号を並べて
記憶する所謂Hアライメント記録をしていた。し
かし長時間記録再生の要請により高密度記録を為
すビデオテープレコーダの多くはHアライメント
記録方式を採らず、スローモーシヨン再生に際し
て水平同期周期の乱れを免れ得ない。 A video tape recorder configured to obtain a slow-motion reproduced image while reproducing and scanning a recording track a predetermined number of times may perform reproduction scanning across tracks in the middle of scanning. Therefore, unless adjacent tracks record horizontal synchronization signals side by side in the track width direction, the horizontal synchronization period will be disrupted the moment scanning is performed across tracks. Therefore, most conventional devices have performed so-called H-alignment recording in which horizontal synchronizing signals are stored side by side in the width direction of the track. However, many video tape recorders that perform high-density recording due to the demand for long-time recording and playback do not employ the H alignment recording method, and are inevitably subject to disturbances in the horizontal synchronization period during slow-motion playback.
そこで本考案は上述の点に鑑み、スローモーシ
ヨン再生時も水平同期周期を乱すことのないスロ
ーモーシヨン再生回路を提案せんとするものであ
る。 Therefore, in view of the above-mentioned points, the present invention aims to propose a slow motion reproduction circuit that does not disturb the horizontal synchronization period even during slow motion reproduction.
以下本考案を図示せる一実施例に従い説明す
る。 The present invention will be described below with reference to an illustrative embodiment.
本実施例は、アジマスを異にする一対の回転磁
気ヘツドにより、一走査当り1フイールド分の映
像信号を同一トラツクに順次記録し、走査方向に
0.75H(Hは1水平同期期間)づつずれて形成さ
れる記録トラツクを、再生時に記録時の1/3のス
ピードでテープを走行せしめ乍ら、各々回転磁気
ヘツドが記録したトラツクを、1/3倍のスローモ
ーシヨン再生を為すビデオテープレコーダのスロ
ーモーシヨン再生回路である。 In this embodiment, a pair of rotating magnetic heads with different azimuths are used to sequentially record video signals for one field per scan on the same track.
During playback, the recording tracks formed with a difference of 0.75H (H is one horizontal synchronization period) are run at 1/3 the speed of recording, and the tracks recorded by each rotating magnetic head are shifted by 1/3. This is a slow motion playback circuit for a video tape recorder that performs 3x slow motion playback.
第1図は、記録走査跡と、再生走査跡の関係を
模式的に示す図であり水平線は記録走査跡の中心
線、斜線は再生走査跡の中心線をそれぞれ示し、
実線はAヘツド、点線はBヘツドの走査跡の中心
線をそれぞれし、第2図は再生ヘツド出力レベル
の変化を模式的に示す図である。よつて両図より
明らかな如く、再生時Aヘツドの第1走査SA1
によつてAヘツドの第1トラツクTA1が再生さ
れ、続くBヘツドの第1走査SB1によつて点P
を境として前半Bヘツドの第1トラツクTB1
が、また後半Bヘツドの第0トラツク(図示省
略)が再生され、更にAヘツドの第2走査SA2
によつてAヘツドの第1トラツクTA1が再生さ
れ、又更にBヘツドの第2走査SB2によつてB
ヘツドの第1トラツクTB1が再生され、続くA
ヘツドの第3走査SA3によつて点qを境として
前半Aヘツドの第2トラツクTA2が後半第1ト
ラツクTA1が再生される。 FIG. 1 is a diagram schematically showing the relationship between recording scanning traces and reproduction scanning traces, where the horizontal line indicates the center line of the recording scanning trace, and the diagonal line indicates the center line of the reproduction scanning trace, respectively.
The solid line indicates the center line of the scan trace of the A head, and the dotted line indicates the center line of the scan trace of the B head. FIG. 2 is a diagram schematically showing changes in the output level of the reproduction head. Therefore, as is clear from both figures, the first scan SA1 of the A head during reproduction
The first track TA1 of the A head is reproduced by the first scan SB1 of the B head, and the point P is reproduced by the first scan SB1 of the B head.
1st track TB1 of head B in the first half
However, the 0th track (not shown) of the second half B head is reproduced, and the second scan SA2 of the A head is also reproduced.
The first track TA1 of the A head is reproduced, and the second track TA1 of the B head is reproduced by the second scan SB2 of the B head.
The first track TB1 of the head is played, and the following A
By the third scan SA3 of the head, the second track TA2 of the first half of the A head and the first track TA1 of the second half are reproduced from the point q.
従つて、本実施例では、3走査毎に走査の途中
(p点、q点、r点……)で再生する記録トラツ
クが変更され、変更によつて再生出力の水平同期
周期が不連続になる。水平同期周期のずれは、隣
接トラツクのずれが0.75Hであることから、Aト
ラツク、Bトラツクに関してそれぞれ1.5H即ち
0.5Hである。 Therefore, in this embodiment, the recording track to be reproduced is changed every three scans in the middle of the scan (point p, point q, point r...), and due to the change, the horizontal synchronization period of the reproduction output becomes discontinuous. Become. Since the difference in the horizontal synchronization period is 0.75H for adjacent tracks, the difference in horizontal synchronization period is 1.5H for A track and B track, or 1.5H for each track.
It is 0.5H.
そこで本実施例ではp点、q点、r点……で再
生出力を0.5H遅延せしめた出力と非遅延の再生
出力を交互に切換導出することにより水平同期周
期の連続する再生出力を合成している。 Therefore, in this embodiment, the playback output with continuous horizontal synchronization periods is synthesized by alternately switching and deriving the playback output delayed by 0.5H and the non-delayed playback output at points p, q, r, etc. ing.
以下、本実施例の回路動作を第3図の回路ブロ
ツクを中心に従い説明する。本実施例では、Aヘ
ツドHA及びBヘツドHBより交互に再生導出され
る再生FM信号は各々第1、第2ヘツドアンプ
1,2を介してそれぞれヘツド出力切換回路3に
入力されヘツドの回転に関連する切換パルスによ
つて連続する再生出力を合成導出し、次に該出力
を高域通過フイルタ4及び低域通過フイルタ5に
それぞれ入力し、前記高域通過フイルタ4からは
FM映像信号の輝度成分を、前記低域通過フイル
タ5からは低域変換色信号を分離導出する。導出
されたFM映像信号輝度成分はリミツタ6を介し
て高域変換回路7に入力されキヤリアの中心周波
数3.6MHzより7.2MHzに変換して中心周波数に対
する周波数偏移の比率を相対的に半減せしめ、第
1スイツチング回路8と第1遅延回路9に入力す
る。2倍に高域変換された輝度成分は、前記第1
遅延回路9にて周波数特性を損なわれることなく
0.5H遅延せしめられて前記第1スイツチング回
路8に入力される。該スイツチング回路8は回転
磁気ヘツドHA,HBが記録トラツクを変更走査す
る時点に同期して導出されるスイツチングパルス
Pによつて水平同期周期の連続する輝度成分を導
出して復調回路10に入力し、輝度信号を導出す
る。導出された輝度信号は映像増幅回路11にて
増幅された後混合回路に入力される。一方前記低
域通過フイルタ5より導出された688KHzの低域
変換色信号は、ACC回路13に入力されて、出
力レベルを調整された後、次段の周波数変換回路
14に入力されて3.58MHzのカラー信号に高域変
換される。導出されたカラー信号は、3.58MHzの
第1バンドパスフイルタ15を通して第2スイツ
チング回路16と第2遅延回路17に入力され、
該第2遅延回路17が導出する0.5H遅延出力と
バンドパスフイルタ出力を前記第2スイツチング
回路16にてスイツチングパルスPを基準に切換
導出し、水平同期周期に関して連続する色信号を
合成する。更に該出力は、櫛型フイルタ18を介
して色信号中に残された輝度成分を解消して、次
段の整流回路19とゲインコントロール回路22
に入力される。前記整流回路19に入力されて更
にローパスフイルタ20を介して導出されたエン
ベロープ信号は、所定のレベルを設定するレベル
比較回路21に入力され、エンベロープ出力が所
定レベル以下のノイズレベルを検出したとき、前
記ゲインコントロール回路22を閉じ単独で存在
するノイズ成分の導出を阻止している。単独で存
在するノイズ信号を阻止された色信号は前記混合
回路12に入力されて色信号を含む映像信号が導
出される。一方前記ACC回路15に入力すべき
水平同期信号は、混合回路12の出力を水平同期
分離回路23に入力して得られる水平同期信号を
第3スイツチング回路24と第3遅延回路25に
入力し、水平同期信号と0.5H遅延水平同期信号
をスイツチングパルスPにより切換導出して得ら
れる切換信号を用いるものとする。 Hereinafter, the circuit operation of this embodiment will be explained with reference to the circuit blocks shown in FIG. 3. In this embodiment, the reproduced FM signals alternately reproduced and derived from the A head H A and the B head H B are input to the head output switching circuit 3 via the first and second head amplifiers 1 and 2, respectively, to rotate the head. successive reproduction outputs are synthesized and derived by switching pulses associated with
The luminance component of the FM video signal is separated and derived from the low-pass filter 5 as a low-pass converted color signal. The derived FM video signal luminance component is input to the high frequency conversion circuit 7 via the limiter 6, converts the carrier's center frequency from 3.6MHz to 7.2MHz, and relatively halves the ratio of frequency deviation with respect to the center frequency. The signal is input to the first switching circuit 8 and the first delay circuit 9. The luminance component that has been subjected to double high-frequency conversion is
Without damaging frequency characteristics in delay circuit 9
The signal is input to the first switching circuit 8 with a delay of 0.5H. The switching circuit 8 derives a luminance component with a continuous horizontal synchronization period by a switching pulse P derived in synchronization with the time when the rotating magnetic heads H A and H B change and scan the recording track, and outputs luminance components that are continuous in the horizontal synchronization period to the demodulation circuit 10 . and derive the luminance signal. The derived luminance signal is amplified by the video amplification circuit 11 and then input to the mixing circuit. On the other hand, the 688KHz low-pass conversion color signal derived from the low-pass filter 5 is input to the ACC circuit 13, where the output level is adjusted, and then input to the next stage frequency conversion circuit 14, where the 3.58MHz High-frequency conversion is performed to a color signal. The derived color signal is inputted to a second switching circuit 16 and a second delay circuit 17 through a 3.58MHz first bandpass filter 15.
The 0.5H delay output and the bandpass filter output derived by the second delay circuit 17 are switched and derived by the second switching circuit 16 based on the switching pulse P, and a continuous color signal with respect to the horizontal synchronization period is synthesized. Furthermore, the output is passed through a comb filter 18 to eliminate the luminance component left in the color signal, and then sent to the next stage rectifier circuit 19 and gain control circuit 22.
is input. The envelope signal input to the rectifier circuit 19 and further derived via the low-pass filter 20 is input to the level comparison circuit 21 which sets a predetermined level, and when the envelope output detects a noise level below the predetermined level, The gain control circuit 22 is closed to prevent noise components that exist alone from being derived. The color signal from which the noise signal existing alone has been blocked is input to the mixing circuit 12, and a video signal including the color signal is derived. On the other hand, the horizontal synchronization signal to be input to the ACC circuit 15 is obtained by inputting the output of the mixing circuit 12 to the horizontal synchronization separation circuit 23, and inputting the horizontal synchronization signal obtained to the third switching circuit 24 and the third delay circuit 25. A switching signal obtained by switching and deriving a horizontal synchronizing signal and a 0.5H delayed horizontal synchronizing signal using a switching pulse P is used.
また前記周波数変換回路14に入力される
4.72MHzの信号は、水平同期周波数の44倍の周波
数を中心周波数とする第1可変発振回路26の出
力と3.57MHzの周波数を中心周波数とする第2可
変発振回路27の出力を平衡変調回路28に入力
し更に次段の第2バンドパスフイルター29にて
加算周波数である4.27MHzの信号を合成して得ら
れる。尚前記第1可変発振回路26の制御信号
は、該第1可変発振出力を1/44分周回路30に入
力して得られる基準信号と水平同期分離出力(比
較信号)をAFC位相検波回路31に入力して得
られる出力であり、前記第2可変発振回路27の
制御信号は、3.58MHzの発振回路32の出力(基
準信号)と、混合回路出力を入力とするバースト
分離回路33のバースト出力(比較信号)を
APC検波回路34に入力して得られる出力であ
る。 Also input to the frequency conversion circuit 14
The 4.72MHz signal is transmitted to a balanced modulation circuit 28 by combining the output of the first variable oscillation circuit 26 whose center frequency is 44 times the horizontal synchronization frequency and the output of the second variable oscillation circuit 27 whose center frequency is 3.57MHz. The signal is input to the second band pass filter 29 in the next stage and is synthesized with a signal of 4.27 MHz, which is the addition frequency. The control signal of the first variable oscillation circuit 26 is a reference signal obtained by inputting the first variable oscillation output to a 1/44 frequency divider circuit 30 and a horizontal synchronization separation output (comparison signal). The control signal of the second variable oscillation circuit 27 is the output obtained by inputting the 3.58 MHz oscillation circuit 32 output (reference signal) and the burst output of the burst separation circuit 33 which receives the mixing circuit output as input. (comparison signal)
This is the output obtained by inputting it to the APC detection circuit 34.
尚スイツチングパルスPの導出は、第2図にも
図示せる再生出力の減衰点を検出して行なうもの
とする。即ち第4図及び第5図に図示せるスイツ
チングパルス発生回路は、まず、連続する再生出
力aをエンベロープ検波回路35に入力して包絡
線出力を導出し、次に所定レベル以下に対応する
区間でローレベルとなる比較出力bを次段のレベ
ル比較回路36より導出し、更に比較出力bのロ
ーレベル域の中央のトラツク変更時点に一致する
遅延出力cを後段の移相回路37より導出し、該
遅延出力をフリツプフロツプ回路38に入力して
スイツチングパルスPを導出している。 It is assumed that the switching pulse P is derived by detecting the attenuation point of the reproduced output, which is also shown in FIG. That is, the switching pulse generation circuit shown in FIGS. 4 and 5 first inputs the continuous reproduced output a to the envelope detection circuit 35 to derive an envelope output, and then derives the envelope output from a section corresponding to a predetermined level or lower. A comparison output b that becomes a low level is derived from the level comparison circuit 36 in the next stage, and a delayed output c that coincides with the track change point in the center of the low level region of the comparison output b is derived from the phase shift circuit 37 in the subsequent stage. , the delayed output is input to a flip-flop circuit 38 to derive a switching pulse P.
斯るスイツチングパルスPを導出する別のスイ
ツチングパルス発生回路としては、第6図及び第
7図に図示せる如く、コントロール信号dを移送
回路39にて1.5フイールド遅延し、該遅延出力
eを準安定期間を3フイールドとする単安定マル
チ回路40に入力して該出力をスイツチングパル
スPとする回路や、第8図及び第9図に図示せる
如く、前記AFC位相検波回路31が導出する位
相変動検出出力をローパスフイルター41を介し
て導出し、水平同期周期が0.5H乱れたとき導出
される高レベルの位相変動検出出力のみをパルス
分離回路42より検出し、該出力を次段の整形回
路43で波形整形した後、フリツプフロツプ回路
44に入力してスイツチングパルスを形成する回
路がある。 As shown in FIGS. 6 and 7, another switching pulse generation circuit for deriving such a switching pulse P delays the control signal d by 1.5 fields in a transfer circuit 39, and outputs the delayed output e. As shown in FIGS. 8 and 9, the AFC phase detection circuit 31 derives the output from a monostable multi-circuit 40 with a metastable period of 3 fields and outputs it as a switching pulse P, as shown in FIGS. 8 and 9. The phase fluctuation detection output is derived through the low-pass filter 41, and only the high-level phase fluctuation detection output derived when the horizontal synchronization period is disturbed by 0.5H is detected by the pulse separation circuit 42, and this output is used for shaping in the next stage. There is a circuit that shapes the waveform in a circuit 43 and then inputs it to a flip-flop circuit 44 to form a switching pulse.
上述せる如く本実施例によれば、走査途中でト
ラツクを変更走査するタイミングで映像信号の遅
延出力と非遅延出力を交互に選択導出するよう構
成することにより水平同期周期を連続せしめたた
め、再生画像の同期乱れが解消されその効果は大
である。 As described above, according to this embodiment, the delayed output and non-delayed output of the video signal are alternately selected and derived at the timing of changing the track during scanning, thereby making the horizontal synchronization period continuous. The synchronization disorder is eliminated, and the effect is great.
第1図は、記録走査跡と再生走査跡の関係を示
す図、第2図は再生出力の変化を示す図、第3図
は本考案の一実施回路ブロツク図、第4図は、要
部回路ブロツク図、第5図は同波形説明図、第6
図は要部回路ブロツク図の他の実施例、第7図は
同波形説明図、第8図は要部回路ブロツク図の更
に他の実施例、第9図は同波形説明図をそれぞれ
示す。
主な図番の説明、9,17,25……遅延回
路、8,16,24……スイツチング回路、P…
…スイツチングパルス。
Fig. 1 is a diagram showing the relationship between recording scanning traces and reproduction scanning traces, Fig. 2 is a diagram showing changes in reproduction output, Fig. 3 is a block diagram of an implementation circuit of the present invention, and Fig. 4 is a diagram showing the main parts. Circuit block diagram, Figure 5 is an explanatory diagram of the same waveforms, Figure 6
The figure shows another embodiment of the main part circuit block diagram, FIG. 7 shows the same waveform explanatory diagram, FIG. 8 shows still another embodiment of the main part circuit block diagram, and FIG. 9 shows the same waveform explanatory diagram. Explanation of main drawing numbers, 9, 17, 25...delay circuit, 8, 16, 24...switching circuit, P...
...Switching pulse.
Claims (1)
り走査域を走査方向に0.25(1+2n)H〔Hは水
平同期周期、nは整数)づつ変更して成る記録ト
ラツク上にFM輝度信号と低域変換カラー信号と
を周波数多重して成る記録信号を記録して成るビ
デオテープを低速度再生すべく、 スローモーシヨン再生時前記回転磁気ヘツドが
再生走査中に同一アジマス記録トラツクを変更走
査する時点に同期してスイツチングパルスを発生
するスイツチングパルス発生回路と、 再生FM輝度信号を高域変換輝度信号に変換す
る高域変換回路と、 該高域変換輝度信号を0.5H遅延して遅延高域
変換輝度信号を導出する第1遅延回路と、 該遅延高域変換輝度信号と前記高域変換輝度信
号とを前記スイツチングパルスに基づいて連続輝
度信号を選択導出する第1スイツチング回路と、 該第1スイツチング回路出力をFM復調する復
調回路と、 再生低域変換カラー信号を元の周波数の再生カ
ラー信号に周波数変換する周波数変換回路と、 該再生カラー信号を0.5H遅延して遅延再生カ
ラー信号を導出する第2遅延回路と、 該遅延カラー信号と前記再生カラー信号とを前
記スイツチングパルスに基づいて前記連続輝度信
号に対応する連続カラー信号を選択導出する第2
スイツチング回路と、 前記連続輝度信号より連続水平同期信号を分離
する水平同期分離回路と、 該連続水平同期信号を0.5H遅延して遅延同期
信号を導出する第3遅延回路と、 該遅延同期信号と前記連続水平同期信号とを前
記スイツチングパルスに基づいて不連続水平同期
信号を選択導出する第3スイツチング回路と、 前記周波数変換回路の前段に於て該不連続水平
同期信号に基づいて前記低域変換カラー信号のレ
ベルをコントロールするACC回路とを、 それぞれ配して成るスローモーシヨン再生回
路。[Claims for Utility Model Registration] On a recording track formed by changing the scanning area by 0.25 (1+2n)H [H is the horizontal synchronization period, n is an integer] in the scanning direction by a pair of rotating magnetic heads with different azimuths. In order to play back at low speed a videotape on which a recording signal formed by frequency multiplexing an FM luminance signal and a low-frequency conversion color signal is recorded, the rotating magnetic head moves the same azimuth recording track during playback scanning during slow motion playback. A switching pulse generation circuit that generates a switching pulse in synchronization with the time of change scanning, a high-frequency conversion circuit that converts the reproduced FM luminance signal into a high-frequency converted luminance signal, and a 0.5H delay for the high-frequency converted luminance signal. a first delay circuit that derives a delayed high-frequency converted luminance signal based on the switching pulse; and a first switching circuit that selects and derives a continuous luminance signal from the delayed high-frequency converted luminance signal and the high-frequency converted luminance signal based on the switching pulse. a demodulation circuit for FM demodulating the output of the first switching circuit; a frequency conversion circuit for frequency converting the reproduced low frequency converted color signal to the reproduced color signal at the original frequency; a second delay circuit for deriving a delayed reproduced color signal; and a second delay circuit for selectively deriving a continuous color signal corresponding to the continuous luminance signal based on the switching pulse from the delayed color signal and the reproduced color signal.
a switching circuit; a horizontal synchronization separation circuit that separates the continuous horizontal synchronization signal from the continuous luminance signal; a third delay circuit that delays the continuous horizontal synchronization signal by 0.5H to derive the delayed synchronization signal; and the delayed synchronization signal. a third switching circuit for selectively deriving the discontinuous horizontal synchronizing signal from the continuous horizontal synchronizing signal based on the switching pulse; A slow motion reproduction circuit consisting of an ACC circuit that controls the level of the converted color signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1978160912U JPS623978Y2 (en) | 1978-11-20 | 1978-11-20 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1978160912U JPS623978Y2 (en) | 1978-11-20 | 1978-11-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5576575U JPS5576575U (en) | 1980-05-27 |
JPS623978Y2 true JPS623978Y2 (en) | 1987-01-29 |
Family
ID=29155121
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1978160912U Expired JPS623978Y2 (en) | 1978-11-20 | 1978-11-20 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS623978Y2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51212A (en) * | 1974-06-18 | 1976-01-05 | Matsushita Electric Ind Co Ltd | |
JPS53131722A (en) * | 1977-04-21 | 1978-11-16 | Matsushita Electric Ind Co Ltd | Still and slow-motion reproduction method |
-
1978
- 1978-11-20 JP JP1978160912U patent/JPS623978Y2/ja not_active Expired
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51212A (en) * | 1974-06-18 | 1976-01-05 | Matsushita Electric Ind Co Ltd | |
JPS53131722A (en) * | 1977-04-21 | 1978-11-16 | Matsushita Electric Ind Co Ltd | Still and slow-motion reproduction method |
Also Published As
Publication number | Publication date |
---|---|
JPS5576575U (en) | 1980-05-27 |
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