JPS6238665B2 - - Google Patents
Info
- Publication number
- JPS6238665B2 JPS6238665B2 JP54047644A JP4764479A JPS6238665B2 JP S6238665 B2 JPS6238665 B2 JP S6238665B2 JP 54047644 A JP54047644 A JP 54047644A JP 4764479 A JP4764479 A JP 4764479A JP S6238665 B2 JPS6238665 B2 JP S6238665B2
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- JP
- Japan
- Prior art keywords
- phase
- output
- signal
- delayed feedback
- synthesis loop
- Prior art date
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- Expired
Links
- 230000003111 delayed effect Effects 0.000 claims description 55
- 230000015572 biosynthetic process Effects 0.000 claims description 40
- 238000003786 synthesis reaction Methods 0.000 claims description 40
- 230000001360 synchronised effect Effects 0.000 claims description 24
- 230000010363 phase shift Effects 0.000 claims description 6
- 238000001228 spectrum Methods 0.000 description 20
- 238000010586 diagram Methods 0.000 description 11
- 239000002131 composite material Substances 0.000 description 7
- 238000001514 detection method Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 239000000284 extract Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
- G01S7/285—Receivers
- G01S7/32—Shaping echo pulse signals; Deriving non-pulse signals from echo pulse signals
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Measuring Frequencies, Analyzing Spectra (AREA)
- Pulse Circuits (AREA)
- Radar Systems Or Details Thereof (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
【発明の詳細な説明】
この発明は例えば高周波パルス信号を遅延させ
たり、パルス変調波の搬送波周波数を測定したり
する場合に用いられる遅延帰還合成式のパルス幅
伸長装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delayed feedback synthesis type pulse width expansion device used, for example, when delaying a high frequency pulse signal or measuring the carrier frequency of a pulse modulated wave.
従来における遅延帰還合成ループの基本的構成
を第1図に示す。 The basic configuration of a conventional delayed feedback synthesis loop is shown in FIG.
図中、1はパルス幅制限器、2は遅延時間τを
もつた遅延線、3は重畳回路、4は補償増幅器、
5はゲートスイツチ、6は可変移相器である。か
かる遅延帰還合成ループにおいて入力信号101
はパルス幅制限器1に入力される。パルス幅制限
器1は入力信号101を遅延帰還ループの遅延時
間τと等しい長さに制限する機能を備えている。
補償増幅器4は遅延帰還ループのループ利得を1
に合せる機能をもつ。 In the figure, 1 is a pulse width limiter, 2 is a delay line with delay time τ, 3 is a superimposition circuit, 4 is a compensation amplifier,
5 is a gate switch, and 6 is a variable phase shifter. In such a delayed feedback synthesis loop, the input signal 101
is input to the pulse width limiter 1. The pulse width limiter 1 has a function of limiting the input signal 101 to a length equal to the delay time τ of the delay feedback loop.
Compensation amplifier 4 sets the loop gain of the delayed feedback loop to 1.
It has the function to match.
入力信号101は第2図aの波形であり、第3
図aのようなスペクトラムを持ち、パルス幅制限
器1から出る短パルス信号102は第2図bに示
す波形となり、その周波数スペクトラムは第3図
bのようである。これらの波形とスペクトルは
(1a)式及び(1b)式で表される
f1(t)=Arect(t/τ)ej2〓f 0 t……(1a)
F1(f)=Aτsinπ(f−f0τ)/π(f−f0)
τ……(1b)
但しrect(t/τ)はパルス幅τのt=0を中心と
する短形パルスである。短パルス信号102はn
回帰還合成ループを通りゲートスイツチ5をオフ
することにより第2図cのような伸長パルス出力
信号103を得る。伸長パルス出力信号103の
スペクトラムは第3図cのようである。これらを
式で表すと(2a)式及び(2b)式となる。 The input signal 101 has the waveform shown in FIG.
The short pulse signal 102, which has a spectrum as shown in Figure a, and output from the pulse width limiter 1 has a waveform as shown in Figure 2b, and its frequency spectrum is as shown in Figure 3b. These waveforms and spectra are expressed by equations (1a) and (1b) f 1 (t) = Arect (t/τ) e j2 〓 f 0 t ... (1a) f-f 0 τ)/π(f-f 0 )
τ...(1b) However, rect(t/τ) is a rectangular pulse with pulse width τ centered at t=0. The short pulse signal 102 is n
By passing through the feedback synthesis loop and turning off the gate switch 5, an expanded pulse output signal 103 as shown in FIG. 2c is obtained. The spectrum of the expanded pulse output signal 103 is as shown in FIG. 3c. Expressing these as formulas, they become formulas (2a) and (2b).
但しθ:パルス接合部の位相差
2πf0τ=2nπ+△φ(n:整数)
△f=△φ/2πτ
f1=f0+△f
故に
Fn(f)
=Aτsinπ(f−f0)τ/π(f−f0)τ×
sin2πn(f−f1)τ/sinπ(f−f1)τ
……
(2b)
即ち
f0≠n/τ ∴△φ≠0 ……(3)
の場合には第2図cの各短パルスの接合部の位相
が不連続となり伸長パルス出力信号103のスペ
クトラムは第3図cの様になつて入力信号101
の搬送波周波数f0と出力信号103の搬送波周波
数f1とは等しくならない。 However, θ: Phase difference at pulse junction 2πf 0 τ = 2nπ + △φ (n: integer) △f = △φ/2πτ f 1 = f 0 + △f Therefore, Fn(f) = Aτsinπ (f - f 0 ) τ /π(f−f 0 )τ×
sin2πn(f- f1 )τ/sinπ(f- f1 )τ
...(2b) That is, f 0 ≠n/τ ∴△φ≠0 ...(3) In the case of (3), the phase of the junction of each short pulse in Fig. 2c becomes discontinuous, and the spectrum of the expanded pulse output signal 103 The input signal 101 becomes as shown in Fig. 3c.
The carrier wave frequency f 0 of the output signal 103 and the carrier wave frequency f 1 of the output signal 103 are not equal.
なお、△φは位相不連続を表わす量である。 Note that Δφ is a quantity representing phase discontinuity.
f0=n/τ ∴△φ=0 ……(4)
の場合には、出力信号103の短パルス接合部の
位相不連続が無くなり、スペクトラムは第3図d
の様にf0=f1となり側帯波成分は最小になる。 In the case of f 0 =n/τ ∴△φ=0...(4), the phase discontinuity at the short pulse junction of the output signal 103 disappears, and the spectrum becomes as shown in Fig. 3d.
As in, f 0 = f 1 and the sideband component becomes minimum.
従つて搬送波周波数を変えないでパルス幅を伸
長する為には、移相器6を可変にして、(4)式を満
足する値に合わせてやる必要がある。従来は、こ
の遅延ループの移相量を自動的に合せる適当な手
段が無かつたので、位相不連続を残したままで使
用したり、伸長パルス出力をスペクトル分析器を
用いて観測しスペクトルが第3図dの様に成る様
に可変移相器6を手動で調整して伸長パルス内の
位相不連続を最小に調整していた。また、この遅
延ループの移相量を自動的に合せる為、従来は第
4図に示すような方式が考えられているが、入力
信号に含まれる雑音や、遅延帰還ループ内で発生
する雑音の影響を受けて安定に動作させるのが非
常に難かしい。 Therefore, in order to extend the pulse width without changing the carrier frequency, it is necessary to make the phase shifter 6 variable and adjust it to a value that satisfies equation (4). Conventionally, there was no suitable means to automatically match the phase shift amount of this delay loop, so it was used with the phase discontinuity remaining, or the elongated pulse output was observed with a spectrum analyzer to determine the spectrum. The variable phase shifter 6 was manually adjusted to minimize the phase discontinuity in the extended pulse as shown in Figure 3d. In addition, in order to automatically match the phase shift amount of this delay loop, a method as shown in Figure 4 has been considered in the past, but this method reduces the noise contained in the input signal and the noise generated in the delay feedback loop. It is very difficult to operate stably due to the influence.
第4図に示す方式は第5図aに示す入力信号1
01のパルス幅制限値以上の残余の部分と、1回
以上遅延帰還回路を通つて遅れて来た信号104
との位相差を位相検波器7で検出してこの位相差
が零になるように移相器6を制御する。第4図に
示す方式は、第1図に示す遅延帰還合成ループに
自動位相合せ回路を付加したものであり、位相合
せ回路は位相検波器7において上記遅延帰還合成
ループで1回以上遅延帰還された遅延信号{第5
図c}とパルス幅制限回路1へ入力する入力信号
{第5図a}との位相差を検出し、この位相差に
比例した検出信号を第5図dに示す波形にて取り
出す。そして、該検出信号はサンプルホールド回
路8に入力され第5図eに示すようにサンプルホ
ールドされ、サンプルホールド信号はAPCルー
プフイルタ9にてサンプルホールドレベルに比例
した制御信号となり、結局この制御信号を出力す
る。この制御信号は上記可変移送器6に供給さ
れ、上記位相差が零となるように可変移相器6は
制御される。この方式では入力信号のパルス幅が
パルス幅制限値τの約2倍以上必要である欠点を
有する他位相誤差を検出する時間がτ0−τで短
時間になるので検出系の帯域幅を広くする必要が
生じ雑音の影響を受け易いという欠点もある。 The method shown in Fig. 4 is based on the input signal 1 shown in Fig. 5a.
01 and the signal 104 which has passed through the delay feedback circuit one or more times and is delayed.
The phase detector 7 detects the phase difference between the two and the phase shifter 6 is controlled so that this phase difference becomes zero. The system shown in FIG. 4 is a system in which an automatic phase matching circuit is added to the delayed feedback synthesis loop shown in FIG. delayed signal {5th
c} and the input signal {Fig. 5a} input to the pulse width limiting circuit 1 is detected, and a detection signal proportional to this phase difference is extracted with the waveform shown in Fig. 5d. The detection signal is then input to the sample and hold circuit 8 and sampled and held as shown in FIG. Output. This control signal is supplied to the variable phase shifter 6, and the variable phase shifter 6 is controlled so that the phase difference becomes zero. This method has the disadvantage that the pulse width of the input signal needs to be approximately twice the pulse width limit value τ.In addition, the time to detect the phase error is short at τ 0 −τ, so the bandwidth of the detection system can be widened. It also has the disadvantage of being susceptible to noise.
この発明は遅延帰還合成ループの移相量を自動
的に制御する安定な自動位相制御回路(APC回
路)を持ち、広い周波数範囲に亘つて安定に動作
する遅延帰還ループを用いたパルス変調波のパル
ス幅伸長装置の提供を目的とする。 This invention has a stable automatic phase control circuit (APC circuit) that automatically controls the amount of phase shift of a delayed feedback synthesis loop, and can generate pulse modulated waves using a delayed feedback loop that operates stably over a wide frequency range. The purpose of this invention is to provide a pulse width stretching device.
以下第6図に示すこの発明の一実施例について
説明する。第6図の実施例にはまず、電子制御発
振器(VCO)20の出力を局部信号として動作
する第1の周波数変換器22の後段に形成された
中間周波回路にパルス幅制限器1、遅延線2、重
畳回路3、補償増幅器4、ゲートスイツチ5、可
変移送器6で構成された遅延帰還合成ループがあ
ることは第1図と同じである。そしてこの上記電
子制御発振器(以下VCOと呼ぶ)20と第1の
周波数変換器22の他、位相検波器7、基準信号
発振器23、及び位相同期ループフイルタ21で
構成され、上記遅延帰還合成ループの出力信号1
03の搬送波成分と基準信号発振器23の出力1
19{第8図c、第9図b、第10図b}とを位
相同期させる様に上記VCO20を自動制御する
位相同期回路(以下PLL回路と呼ぶ)が上記遅延
帰還ループに付加される。またPLL回路の残留位
相誤差を上記位相検波器の出力107{第9図
c、第10図c}から取り出し、遅延帰還合成出
力103の位相リツプル成分を検出して遅延帰還
合成ループの開ループ伝達位相量を自動制御する
ために、帯域通過フイルタ11、同期復調器1
2、積分ホールド回路8、APCループフイルタ
9及びタイミングパルス発生器13で構成される
自動位相合せ回路(以下APC回路と呼ぶ)も付
加されている。遅延帰還合成ループの動作につい
ては信号が中間周波信号に変換されて以後通る点
を除けば、先に第1図、第2図及び第3図を用い
て説明したものと全く同じであるのでここでは説
明を省略しPLL系とAPC系について説明する。
第6図の各部の波形を第7図に示し、信号スペク
トラムを第8図、第9図、第10図に各々示して
いる。 An embodiment of the present invention shown in FIG. 6 will be described below. In the embodiment shown in FIG. 6, first, a pulse width limiter 1 and a delay line are connected to an intermediate frequency circuit formed after a first frequency converter 22 which operates using the output of an electronically controlled oscillator (VCO) 20 as a local signal. 2. As in FIG. 1, there is a delayed feedback synthesis loop composed of a superimposing circuit 3, a compensation amplifier 4, a gate switch 5, and a variable shifter 6. In addition to the electronically controlled oscillator (hereinafter referred to as VCO) 20 and the first frequency converter 22, it is composed of a phase detector 7, a reference signal oscillator 23, and a phase-locked loop filter 21, and the delayed feedback synthesis loop is Output signal 1
03 carrier wave component and the output 1 of the reference signal oscillator 23
19 {FIG. 8c, FIG. 9b, and FIG. 10b} A phase synchronization circuit (hereinafter referred to as a PLL circuit) that automatically controls the VCO 20 so as to phase-synchronize the VCO 20 is added to the delay feedback loop. In addition, the residual phase error of the PLL circuit is extracted from the output 107 of the phase detector (Fig. 9 c, Fig. 10 c), and the phase ripple component of the delayed feedback synthesis output 103 is detected and the open loop transmission of the delayed feedback synthesis loop is performed. In order to automatically control the phase amount, a bandpass filter 11 and a synchronous demodulator 1 are used.
2. An automatic phase matching circuit (hereinafter referred to as APC circuit) consisting of an integral hold circuit 8, an APC loop filter 9, and a timing pulse generator 13 is also added. The operation of the delayed feedback synthesis loop is exactly the same as that explained earlier using Figures 1, 2, and 3, except that the signal is converted to an intermediate frequency signal and then passes through the loop, so it will be explained here. Now, I will omit the explanation and explain the PLL system and APC system.
The waveforms of each part in FIG. 6 are shown in FIG. 7, and the signal spectra are shown in FIGS. 8, 9, and 10, respectively.
第8図はPLL回路、APC回路共にロツクオン
していない状態のスペクトラムであり、第9図は
PLL回路がロツクオンして、APC回路はロツク
オフ状態のスペクトラムであり、第10図はPLL
回路とAPC回路とが共にロツクオンした状態に
於るスペクトラムを各々示している。 Figure 8 shows the spectrum when neither the PLL circuit nor the APC circuit is locked on, and Figure 9 shows the spectrum when both the PLL circuit and APC circuit are not locked on.
The PLL circuit is locked on and the APC circuit is locked off. Figure 10 shows the spectrum of the PLL circuit.
The spectra are shown when both the circuit and the APC circuit are locked on.
第8図及び以下の説明は仮に入力信号101の
搬送波周波数f0と第7図aの中間周波信号102
の搬送波周波数fIFO及び電子制御発振器20の
出力118の周波数fVCOの関係は次式であると
して説明する。 FIG. 8 and the following explanation assume that the carrier frequency f 0 of the input signal 101 and the intermediate frequency signal 102 of FIG.
The relationship between the carrier wave frequency f IFO and the frequency f VCO of the output 118 of the electronically controlled oscillator 20 will be explained as follows.
fIFO=f0−fVCO ……(1)
しかしながら、(1)式に限らず次の(2)式において
も適用することができる。 f IFO = f 0 - f VCO (1) However, it is applicable not only to equation (1) but also to equation (2) below.
fIFO=mf0±n fVCO(m、n:任意
の整数) ……(2)
位相検波器7は第8図bに示すスペクトラムを
持つ遅延帰還合成出力信号103と第8図cに示
す周波数fREFの基準信号との位相差を検出して
第7図cに示す波形を得る。 f IFO = mf 0 ±n f VCO (m, n: arbitrary integers) ...(2) The phase detector 7 generates a delayed feedback composite output signal 103 having the spectrum shown in FIG. 8b and a delayed feedback composite output signal 103 having the spectrum shown in FIG. 8c. The phase difference between the frequency f REF and the reference signal is detected to obtain the waveform shown in FIG. 7c.
PLL回路は位相検波回路のこの低周波及び直流
分のみをPLLループフイルタにより取出して
VCO20の発振周波数を変化させ、もつて中間
周波信号の周波数を変化させる事によつて第8図
bに示す遅延帰還合成出力の搬送波成分f1を基準
信号119{第8図c}と位相同期させる。従つ
てPLL回路がロツクオンした状態では、f1=fRE
Fとなり、第9図に示すスペクトラムとなる。 The PLL circuit extracts only this low frequency and DC component of the phase detection circuit using a PLL loop filter.
By changing the oscillation frequency of the VCO 20 and thereby changing the frequency of the intermediate frequency signal, the phase of the carrier component f 1 of the delayed feedback composite output shown in FIG. 8b is synchronized with the reference signal 119 {FIG. 8c}. let Therefore, when the PLL circuit is locked on, f 1 = f RE
F , resulting in the spectrum shown in FIG.
APC回路はこのPLL回路がロツクオンした状
態に於ける位相検波器7の出力信号{第7図dに
示す}が通過中心周波数が1/τ(Hz){但しτ
=短パルスのパルス幅(sec)}に等しい帯域通過
フイルタを通してf≒1/τの成分{第9図aに
示す遅延帰還合成出力103の第1側帯波成分に
よつて生ずる成分のみ}を取出し、第7図eに示
すリツプル(波形)信号を得る。このリツプル信
号を位相リツプル信号108と称しスペクトルは
第9図dに示すようになり、また振幅は第9図a
に示す側帯波成分の振幅に比例し遅延帰還ループ
出力の位相誤差△φの正弦値sin△φに比例す
る。 In the APC circuit, when the PLL circuit is locked on, the output signal of the phase detector 7 {shown in FIG. 7d} has a passing center frequency of 1/τ (Hz) {however, τ
= short pulse width (sec)}, extract the component of f≒1/τ {only the component generated by the first sideband component of the delayed feedback composite output 103 shown in FIG. 9a}. , a ripple (waveform) signal shown in FIG. 7e is obtained. This ripple signal is called a phase ripple signal 108, and its spectrum is as shown in FIG. 9d, and the amplitude is as shown in FIG. 9a.
It is proportional to the amplitude of the sideband component shown in , and is proportional to the sine value sin Δφ of the phase error Δφ of the output of the delayed feedback loop.
一方、パルス幅制限器1の動作時間を検出した
信号タイミングパルス信号109でタイミングパ
ルス発生器13を動作させて遅延帰還合成ループ
に於ける短パルスの循環サイクルに同期した第7
図fに示す周期τの同期タイミングパルス信号1
10を発生する。 On the other hand, the timing pulse generator 13 is operated by the signal timing pulse signal 109 which detects the operation time of the pulse width limiter 1, and the seventh
Synchronous timing pulse signal 1 with period τ shown in Figure f
Generate 10.
次に同期復調器12で上記位相リツプル信号1
08を同期タイミングパルス信号110を基準に
して同期検波し遅延帰還合成ループに於ける短パ
ルス信号の循環サイクルに同期した第7図gに示
すようなパルス成分111を取り出す。このまま
ではパルス成分111の波形は第7図に示す通り
全波整流波形の断続する幅nτのパルス状である
ため、次段の積分ホールド回路8で各パルス毎の
直流成分を取り出し、ストレツチして第7図hに
示すような直流電圧信号112に変換する。この
直流電圧信号112は遅延帰還合成ループのルー
プ位相誤差△φの正弦値sin△φに比例する。よ
つてこの△φの値を位相誤差電圧信号112と呼
ぶ。この位相誤差電圧信号112をAPCループ
フイルタ9を通して遅延帰還合成ループの可変移
送器6に帰還して遅延帰還合成ループの移相量を
制御して常にループ位相誤差△φが零になるよう
に制御する。なお、上記同期復調器12は周期τ
の基準タイミングパルスと同期する成分のみを取
り出すので、位相検波器7と同期復調器12の間
に入れた帯域通過フイルタ11は不可欠なもので
はない。 Next, the synchronous demodulator 12 outputs the phase ripple signal 1.
08 is subjected to synchronous detection using the synchronous timing pulse signal 110 as a reference, and a pulse component 111 as shown in FIG. 7g, which is synchronized with the circulation cycle of the short pulse signal in the delayed feedback synthesis loop, is extracted. As it is, the waveform of the pulse component 111 is a full-wave rectified waveform with an intermittent width nτ as shown in FIG. It is converted into a DC voltage signal 112 as shown in FIG. 7h. This DC voltage signal 112 is proportional to the sine value sinΔφ of the loop phase error Δφ of the delayed feedback synthesis loop. Therefore, this value of Δφ is called a phase error voltage signal 112. This phase error voltage signal 112 is fed back to the variable transfer device 6 of the delayed feedback synthesis loop through the APC loop filter 9 to control the amount of phase shift of the delayed feedback synthesis loop so that the loop phase error △φ is always zero. do. Note that the synchronous demodulator 12 has a period τ
Since only the components that are synchronized with the reference timing pulse are extracted, the bandpass filter 11 inserted between the phase detector 7 and the synchronous demodulator 12 is not essential.
従つてPLL回路、APC回路の両方がロツク・
オンした状態では
となる。 Therefore, both the PLL circuit and the APC circuit are locked.
When turned on becomes.
この状態では各部の信号スペクトラムは第10
図に示すようになり、第10図aに示す遅延帰還
合成ループ出力103は第10図bの基準信号1
19と位相同期しており側帯波成分もほぼ無くな
るのでその波形は位相変動の無い連続的な長パル
ス変調波となり、その搬送波周波数f1は
f1=fIFO・(=fREF)
である。従つてこの遅延帰還合成出力103を
VCO20の出力118を用いて第2の周波数変
換器24で再度周波数変換すれば、その出力12
0として搬送波周波数が
fIFO+fVCO=f0
の位相変動の無い連続的な長パルス変調波が得ら
れる。用途によつてはこの第2の周波数変換器2
4は無くても、入力搬送波周波数f0と出力搬送波
周波数fIFO及び、局部信号周波数fVCOとの間に
同期が取れて
fIFO=f0−fVCO=fREF
の関係が保たれるだけで良い場合も有り得る。 In this state, the signal spectrum of each part is 10th
As shown in the figure, the delayed feedback synthesis loop output 103 shown in FIG. 10a is the reference signal 1 in FIG.
Since the phase is synchronized with 19 and the sideband component is almost eliminated, the waveform becomes a continuous long pulse modulated wave with no phase fluctuation, and the carrier frequency f 1 is f 1 =f IFO ·(=f REF ). Therefore, this delayed feedback composite output 103
If the second frequency converter 24 converts the frequency again using the output 118 of the VCO 20, the output 12
When the carrier frequency is set to 0, a continuous long pulse modulated wave with no phase fluctuation with a carrier frequency of f IFO + f VCO = f 0 is obtained. Depending on the application, this second frequency converter 2
4, the input carrier frequency f 0 , the output carrier frequency f IFO , and the local signal frequency f VCO can be synchronized, and the relationship f IFO = f 0 − f VCO = f REF can be maintained. There may be cases where this is fine.
この方式では遅延帰還合成出力103の搬送波
成分を基準信号と同期させる様にPLL回路を用い
て局部信号を制御し、次に遅延帰還合成出力10
3の位相変動の遅延帰還合成サイクルに同期した
成分のみを同期復調によつて取出してAPC回路
の位相誤差検出電圧にしているため、遅延帰還サ
イクルに起因して生じた位相変化を効率的に検出
できるので位相誤差検出系のS/Nを大幅に改善
することができ、遅延帰還合成ループ内部で発生
する雑音や入力RF信号の熱雑音等によつて生ず
る制御誤差や変動が著しく小さくなり、安定な自
動位相制御を行うことができる。更に遅延帰還合
成ループを中間周波回路中に構成し局部発振器を
位相同期制御するPLL回路の中に組込むために遅
延帰還合成ループの所要帯域幅は著しく狭帯域化
され、PLL回路がロツク・オンした状態において
はほぼ基準信号の周波数fREFと一致するため遅
延帰還合成ループの周波数−位相特性による制御
誤差を無くする事が出来る。 In this method, a PLL circuit is used to control the local signal so that the carrier component of the delayed feedback composite output 103 is synchronized with the reference signal, and then the delayed feedback composite output 10
Only the components synchronized with the delayed feedback synthesis cycle of phase fluctuations in step 3 are extracted by synchronous demodulation and used as the phase error detection voltage of the APC circuit, so phase changes caused by the delayed feedback cycle can be efficiently detected. As a result, the S/N ratio of the phase error detection system can be significantly improved, and control errors and fluctuations caused by noise generated inside the delayed feedback synthesis loop and thermal noise of the input RF signal are significantly reduced, resulting in stable Automatic phase control can be performed. Furthermore, in order to configure the delayed feedback synthesis loop in the intermediate frequency circuit and incorporate it into the PLL circuit that controls the phase synchronization of the local oscillator, the required bandwidth of the delayed feedback synthesis loop was significantly narrowed, and the PLL circuit was locked on. In this state, the frequency f REF almost matches the reference signal, so that control errors due to the frequency-phase characteristics of the delayed feedback synthesis loop can be eliminated.
次に第11図はこの発明の他の実施例を示し第
12図は第11図の各部の信号波形図である。こ
の実施例はパルス幅伸長装置の出力に高周波ゲー
ト回路28を設け、遅延パルス発生器29により
第12図dに示す信号入力タイミング109から
第12図eに示すように任意の時間遅れたタイミ
ングで任意の時間だけ信号を断続することによつ
て、入力の短パルス変調波と同じ搬送波周波数を
有し、しかも任意の時間遅れて、任意のパルス幅
を持つた第10図fに示すパルス変調波に変換す
る機能を付加したものである。なお、本実施例で
は高周波ゲート回路28は第2の周波数変換器2
4の前段又は後段のいずれに設けてもよい。 Next, FIG. 11 shows another embodiment of the present invention, and FIG. 12 is a signal waveform diagram of each part in FIG. 11. In this embodiment, a high frequency gate circuit 28 is provided at the output of the pulse width expansion device, and a delay pulse generator 29 is used to generate the signal at an arbitrary time delayed timing from the signal input timing 109 shown in FIG. 12d to the timing shown in FIG. 12e. By interrupting the signal for an arbitrary period of time, the pulse modulated wave shown in Fig. 10f, which has the same carrier frequency as the input short pulse modulated wave, is delayed by an arbitrary time, and has an arbitrary pulse width can be generated. It has the added function of converting to . Note that in this embodiment, the high frequency gate circuit 28 is connected to the second frequency converter 2.
It may be provided at either the front stage or the rear stage of 4.
以上の様に、この発明に係る遅延帰還合成式の
パルス幅伸長装置は、自動位相制御回路(APC
回路)を有する遅延帰還合成ループを中間周波回
路に構成し、周波数変換用の局部信号発振器を制
御する位相同期制御回路(PLL回路)を設けて、
遅延帰還合成出力の搬送波成分が基準信号と位相
同期するように制御すると同時にこのAPC回路
の働きによりこのPLL回路の位相制御の残留誤差
から遅延帰還合成ループの遅延帰還サイクルに同
期する成分を取出すことによつて遅延帰還合成出
力に於るパルス接合部分の位相不連続を検出しこ
の位相不連続が零になるように遅延帰還合成ルー
プ内に設けた可変移相器を制御するように構成し
ている。そのため遅延帰還合成ループ内に発生す
る雑音や入力信号に含まれる熱雑音その他の外来
雑音に対して安定に遅延帰還合成ループの自動位
相制御を行う事ができ、常に位相連続かつ搬送波
周波数のずれないパルス幅伸長出力を得ることが
できる。また、PLL回路の働きによつて遅延帰還
合成ループの出力信号の搬送波周波数は高周波入
力周波数にかかわらず基準信号周波数に等しく保
たれるので、遅延帰還合成ループの所要帯域幅が
高周波入力周波数範囲と関係無く非常に狭くなり
遅延帰還合成ループの開ループ周波数特性の影響
を避けることができる。 As described above, the delayed feedback synthesis type pulse width stretching device according to the present invention has an automatic phase control circuit (APC).
A delayed feedback synthesis loop with a circuit) is configured in an intermediate frequency circuit, and a phase-locked control circuit (PLL circuit) is provided to control a local signal oscillator for frequency conversion.
The carrier wave component of the delayed feedback synthesis output is controlled to be phase-synchronized with the reference signal, and at the same time, the component synchronized with the delayed feedback cycle of the delayed feedback synthesis loop is extracted from the residual error of the phase control of this PLL circuit by the action of this APC circuit. is configured to detect phase discontinuity in the pulse junction portion of the delayed feedback synthesis output and to control a variable phase shifter provided in the delayed feedback synthesis loop so that this phase discontinuity becomes zero. There is. Therefore, automatic phase control of the delayed feedback synthesis loop can be performed stably against noise generated in the delayed feedback synthesis loop, thermal noise included in the input signal, and other external noise, and the phase is always continuous and the carrier frequency does not shift. A pulse width expanded output can be obtained. In addition, due to the function of the PLL circuit, the carrier frequency of the output signal of the delayed feedback synthesis loop is kept equal to the reference signal frequency regardless of the high frequency input frequency, so the required bandwidth of the delayed feedback synthesis loop is equal to the high frequency input frequency range. Regardless, it becomes very narrow and the influence of the open-loop frequency characteristic of the delayed feedback synthesis loop can be avoided.
第1図は一搬の遅延帰還合成ループの基本的構
成を示すブロツク構成図、第2図は第1図の各部
の波形を示す波形図、第3図は第2図の各部の波
形の周波数スペクトラム図、第4図は従来の自動
移相合せ機能を持つ遅延帰還合成ループを示すブ
ロツク構成図、第5図は第4図の系の各部の波形
を示す波形図、第6図はこの発明の一実施例を示
すブロツク構成図、第7図は第6図の系の各部の
波形を示す波形図、第8図、第9図、第10図は
第7図の各部における波形の周波数スペクトラム
図、第11図、第13図はこの発明の他の実施例
を示すブロツク構成図、第12図は第11図の実
施例の各部における信号波形図である。
図中、1はパルス幅制限器、2は遅延線、3は
重畳回路、5はゲートスイツチ、6は移相器、7
は位相検波器、8は積分ホールド回路、9は
APCループフイルタ、12は同期復調器、13
はタイミングパルス発生器、20は電子制御発振
器、21はPLLループフイルタ、22は第1の周
波数変換器、23は基準信号発振器、24は周波
数変換器である。なお、図中同一符号は同一又は
相当部分を示す。
Figure 1 is a block configuration diagram showing the basic configuration of a single-carrier delayed feedback synthesis loop, Figure 2 is a waveform diagram showing the waveforms of each part in Figure 1, and Figure 3 is the frequency of the waveform of each part in Figure 2. Spectrum diagram, Figure 4 is a block configuration diagram showing a conventional delayed feedback synthesis loop with an automatic phase matching function, Figure 5 is a waveform diagram showing waveforms of each part of the system in Figure 4, and Figure 6 is a diagram showing the waveform of the system of the present invention. A block configuration diagram showing one embodiment, Fig. 7 is a waveform diagram showing waveforms of each part of the system in Fig. 6, and Figs. 8, 9, and 10 show frequency spectra of waveforms in each part of the system shown in Fig. 7. 11 and 13 are block diagrams showing other embodiments of the present invention, and FIG. 12 is a signal waveform diagram at each part of the embodiment of FIG. 11. In the figure, 1 is a pulse width limiter, 2 is a delay line, 3 is a superimposition circuit, 5 is a gate switch, 6 is a phase shifter, and 7
is a phase detector, 8 is an integral hold circuit, 9 is a
APC loop filter, 12 is a synchronous demodulator, 13
20 is a timing pulse generator, 20 is an electronically controlled oscillator, 21 is a PLL loop filter, 22 is a first frequency converter, 23 is a reference signal oscillator, and 24 is a frequency converter. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
パルス変調波のパルス幅を伸長するパルス幅伸長
装置において、電子制御発振器と、この電子制御
発振器の出力を局部信号にして上記遅延帰還合成
ループの入力信号を中間周波信号に変換する周波
数変換器と、基準信号発振器と、この基準信号発
振器の基準出力と上記遅延帰還合成ループの出力
との位相差を検出する位相検波器とを有し、上記
位相検波器の出力により上記遅延帰還合成ループ
出力の搬送波成分の位相が上記基準出力の位相と
同期するように上記電子制御発振器の出力を可変
する位相同期回路、及び、上記遅延帰還合成ルー
プの循環サイクルに同期した同期タイミング信号
を発生する基準タイミングパルス発生器と、この
同期タイミング信号を用いて上記位相検波器の出
力から上記遅延帰還合成ループの循環サイクルに
同期した成分を検出しこの出力により上記移相器
の移相量を可変する同期復調器とを有し、上記同
期復調器の出力によりこの出力が零になるように
上記移相器の移相量を可変する自動位相合せ回路
とを備えたパルス幅伸長装置。1. In a pulse width stretching device that stretches the pulse width of a pulse modulated wave using a delayed feedback synthesis loop having a phase shifter, an electronically controlled oscillator and an output of the electronically controlled oscillator are used as local signals for the delayed feedback synthesis loop. a frequency converter for converting an input signal into an intermediate frequency signal; a reference signal oscillator; and a phase detector for detecting a phase difference between a reference output of the reference signal oscillator and an output of the delayed feedback synthesis loop; a phase synchronization circuit that varies the output of the electronically controlled oscillator so that the phase of the carrier component of the output of the delayed feedback synthesis loop is synchronized with the phase of the reference output by the output of the phase detector; and circulation of the delayed feedback synthesis loop. A reference timing pulse generator generates a synchronized timing signal synchronized with the cycle, and a component synchronized with the circulation cycle of the delayed feedback synthesis loop is detected from the output of the phase detector using this synchronized timing signal. a synchronous demodulator that varies the amount of phase shift of the phase shifter; and an automatic phase matching circuit that varies the amount of phase shift of the phase shifter so that the output of the synchronous demodulator becomes zero. Equipped with a pulse width stretching device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4764479A JPS55140178A (en) | 1979-04-18 | 1979-04-18 | Pulse duration lengthening device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4764479A JPS55140178A (en) | 1979-04-18 | 1979-04-18 | Pulse duration lengthening device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55140178A JPS55140178A (en) | 1980-11-01 |
JPS6238665B2 true JPS6238665B2 (en) | 1987-08-19 |
Family
ID=12780945
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4764479A Granted JPS55140178A (en) | 1979-04-18 | 1979-04-18 | Pulse duration lengthening device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55140178A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8149035B2 (en) | 2010-02-02 | 2012-04-03 | International Business Machines Corporation | Multi-output PLL output shift |
-
1979
- 1979-04-18 JP JP4764479A patent/JPS55140178A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS55140178A (en) | 1980-11-01 |
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